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TOMOYO Linux Cross Reference
Linux/arch/mips/pci/pci-octeon.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 2005-2009 Cavium Networks
  7  */
  8 #include <linux/kernel.h>
  9 #include <linux/init.h>
 10 #include <linux/pci.h>
 11 #include <linux/interrupt.h>
 12 #include <linux/time.h>
 13 #include <linux/delay.h>
 14 #include <linux/platform_device.h>
 15 #include <linux/swiotlb.h>
 16 
 17 #include <asm/time.h>
 18 
 19 #include <asm/octeon/octeon.h>
 20 #include <asm/octeon/cvmx-npi-defs.h>
 21 #include <asm/octeon/cvmx-pci-defs.h>
 22 #include <asm/octeon/pci-octeon.h>
 23 
 24 #include <dma-coherence.h>
 25 
 26 #define USE_OCTEON_INTERNAL_ARBITER
 27 
 28 /*
 29  * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
 30  * addresses. Use PCI endian swapping 1 so no address swapping is
 31  * necessary. The Linux io routines will endian swap the data.
 32  */
 33 #define OCTEON_PCI_IOSPACE_BASE     0x80011a0400000000ull
 34 #define OCTEON_PCI_IOSPACE_SIZE     (1ull<<32)
 35 
 36 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
 37 #define OCTEON_PCI_MEMSPACE_OFFSET  (0x00011b0000000000ull)
 38 
 39 u64 octeon_bar1_pci_phys;
 40 
 41 /**
 42  * This is the bit decoding used for the Octeon PCI controller addresses
 43  */
 44 union octeon_pci_address {
 45         uint64_t u64;
 46         struct {
 47                 uint64_t upper:2;
 48                 uint64_t reserved:13;
 49                 uint64_t io:1;
 50                 uint64_t did:5;
 51                 uint64_t subdid:3;
 52                 uint64_t reserved2:4;
 53                 uint64_t endian_swap:2;
 54                 uint64_t reserved3:10;
 55                 uint64_t bus:8;
 56                 uint64_t dev:5;
 57                 uint64_t func:3;
 58                 uint64_t reg:8;
 59         } s;
 60 };
 61 
 62 int __initconst (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
 63                                          u8 slot, u8 pin);
 64 enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
 65 
 66 /**
 67  * Map a PCI device to the appropriate interrupt line
 68  *
 69  * @dev:    The Linux PCI device structure for the device to map
 70  * @slot:   The slot number for this device on __BUS 0__. Linux
 71  *               enumerates through all the bridges and figures out the
 72  *               slot on Bus 0 where this device eventually hooks to.
 73  * @pin:    The PCI interrupt pin read from the device, then swizzled
 74  *               as it goes through each bridge.
 75  * Returns Interrupt number for the device
 76  */
 77 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 78 {
 79         if (octeon_pcibios_map_irq)
 80                 return octeon_pcibios_map_irq(dev, slot, pin);
 81         else
 82                 panic("octeon_pcibios_map_irq not set.");
 83 }
 84 
 85 
 86 /*
 87  * Called to perform platform specific PCI setup
 88  */
 89 int pcibios_plat_dev_init(struct pci_dev *dev)
 90 {
 91         uint16_t config;
 92         uint32_t dconfig;
 93         int pos;
 94         /*
 95          * Force the Cache line setting to 64 bytes. The standard
 96          * Linux bus scan doesn't seem to set it. Octeon really has
 97          * 128 byte lines, but Intel bridges get really upset if you
 98          * try and set values above 64 bytes. Value is specified in
 99          * 32bit words.
100          */
101         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
102         /* Set latency timers for all devices */
103         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
104 
105         /* Enable reporting System errors and parity errors on all devices */
106         /* Enable parity checking and error reporting */
107         pci_read_config_word(dev, PCI_COMMAND, &config);
108         config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
109         pci_write_config_word(dev, PCI_COMMAND, config);
110 
111         if (dev->subordinate) {
112                 /* Set latency timers on sub bridges */
113                 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
114                 /* More bridge error detection */
115                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
116                 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
117                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
118         }
119 
120         /* Enable the PCIe normal error reporting */
121         config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
122         config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
123         config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
124         config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
125         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
126 
127         /* Find the Advanced Error Reporting capability */
128         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
129         if (pos) {
130                 /* Clear Uncorrectable Error Status */
131                 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
132                                       &dconfig);
133                 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
134                                        dconfig);
135                 /* Enable reporting of all uncorrectable errors */
136                 /* Uncorrectable Error Mask - turned on bits disable errors */
137                 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
138                 /*
139                  * Leave severity at HW default. This only controls if
140                  * errors are reported as uncorrectable or
141                  * correctable, not if the error is reported.
142                  */
143                 /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
144                 /* Clear Correctable Error Status */
145                 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
146                 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
147                 /* Enable reporting of all correctable errors */
148                 /* Correctable Error Mask - turned on bits disable errors */
149                 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
150                 /* Advanced Error Capabilities */
151                 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
152                 /* ECRC Generation Enable */
153                 if (config & PCI_ERR_CAP_ECRC_GENC)
154                         config |= PCI_ERR_CAP_ECRC_GENE;
155                 /* ECRC Check Enable */
156                 if (config & PCI_ERR_CAP_ECRC_CHKC)
157                         config |= PCI_ERR_CAP_ECRC_CHKE;
158                 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
159                 /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
160                 /* Report all errors to the root complex */
161                 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
162                                        PCI_ERR_ROOT_CMD_COR_EN |
163                                        PCI_ERR_ROOT_CMD_NONFATAL_EN |
164                                        PCI_ERR_ROOT_CMD_FATAL_EN);
165                 /* Clear the Root status register */
166                 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
167                 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
168         }
169 
170         dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops;
171 
172         return 0;
173 }
174 
175 /**
176  * Return the mapping of PCI device number to IRQ line. Each
177  * character in the return string represents the interrupt
178  * line for the device at that position. Device 1 maps to the
179  * first character, etc. The characters A-D are used for PCI
180  * interrupts.
181  *
182  * Returns PCI interrupt mapping
183  */
184 const char *octeon_get_pci_interrupts(void)
185 {
186         /*
187          * Returning an empty string causes the interrupts to be
188          * routed based on the PCI specification. From the PCI spec:
189          *
190          * INTA# of Device Number 0 is connected to IRQW on the system
191          * board.  (Device Number has no significance regarding being
192          * located on the system board or in a connector.) INTA# of
193          * Device Number 1 is connected to IRQX on the system
194          * board. INTA# of Device Number 2 is connected to IRQY on the
195          * system board. INTA# of Device Number 3 is connected to IRQZ
196          * on the system board. The table below describes how each
197          * agent's INTx# lines are connected to the system board
198          * interrupt lines. The following equation can be used to
199          * determine to which INTx# signal on the system board a given
200          * device's INTx# line(s) is connected.
201          *
202          * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
203          * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
204          * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
205          * INTD# = 3)
206          */
207         switch (octeon_bootinfo->board_type) {
208         case CVMX_BOARD_TYPE_NAO38:
209                 /* This is really the NAC38 */
210                 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
211         case CVMX_BOARD_TYPE_EBH3100:
212         case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
213         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
214                 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
215         case CVMX_BOARD_TYPE_BBGW_REF:
216                 return "AABCD";
217         case CVMX_BOARD_TYPE_CUST_DSR1000N:
218                 return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
219         case CVMX_BOARD_TYPE_THUNDER:
220         case CVMX_BOARD_TYPE_EBH3000:
221         default:
222                 return "";
223         }
224 }
225 
226 /**
227  * Map a PCI device to the appropriate interrupt line
228  *
229  * @dev:    The Linux PCI device structure for the device to map
230  * @slot:   The slot number for this device on __BUS 0__. Linux
231  *               enumerates through all the bridges and figures out the
232  *               slot on Bus 0 where this device eventually hooks to.
233  * @pin:    The PCI interrupt pin read from the device, then swizzled
234  *               as it goes through each bridge.
235  * Returns Interrupt number for the device
236  */
237 int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
238                                       u8 slot, u8 pin)
239 {
240         int irq_num;
241         const char *interrupts;
242         int dev_num;
243 
244         /* Get the board specific interrupt mapping */
245         interrupts = octeon_get_pci_interrupts();
246 
247         dev_num = dev->devfn >> 3;
248         if (dev_num < strlen(interrupts))
249                 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
250                         OCTEON_IRQ_PCI_INT0;
251         else
252                 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
253         return irq_num;
254 }
255 
256 
257 /*
258  * Read a value from configuration space
259  */
260 static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
261                               int reg, int size, u32 *val)
262 {
263         union octeon_pci_address pci_addr;
264 
265         pci_addr.u64 = 0;
266         pci_addr.s.upper = 2;
267         pci_addr.s.io = 1;
268         pci_addr.s.did = 3;
269         pci_addr.s.subdid = 1;
270         pci_addr.s.endian_swap = 1;
271         pci_addr.s.bus = bus->number;
272         pci_addr.s.dev = devfn >> 3;
273         pci_addr.s.func = devfn & 0x7;
274         pci_addr.s.reg = reg;
275 
276         switch (size) {
277         case 4:
278                 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
279                 return PCIBIOS_SUCCESSFUL;
280         case 2:
281                 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
282                 return PCIBIOS_SUCCESSFUL;
283         case 1:
284                 *val = cvmx_read64_uint8(pci_addr.u64);
285                 return PCIBIOS_SUCCESSFUL;
286         }
287         return PCIBIOS_FUNC_NOT_SUPPORTED;
288 }
289 
290 
291 /*
292  * Write a value to PCI configuration space
293  */
294 static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
295                                int reg, int size, u32 val)
296 {
297         union octeon_pci_address pci_addr;
298 
299         pci_addr.u64 = 0;
300         pci_addr.s.upper = 2;
301         pci_addr.s.io = 1;
302         pci_addr.s.did = 3;
303         pci_addr.s.subdid = 1;
304         pci_addr.s.endian_swap = 1;
305         pci_addr.s.bus = bus->number;
306         pci_addr.s.dev = devfn >> 3;
307         pci_addr.s.func = devfn & 0x7;
308         pci_addr.s.reg = reg;
309 
310         switch (size) {
311         case 4:
312                 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
313                 return PCIBIOS_SUCCESSFUL;
314         case 2:
315                 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
316                 return PCIBIOS_SUCCESSFUL;
317         case 1:
318                 cvmx_write64_uint8(pci_addr.u64, val);
319                 return PCIBIOS_SUCCESSFUL;
320         }
321         return PCIBIOS_FUNC_NOT_SUPPORTED;
322 }
323 
324 
325 static struct pci_ops octeon_pci_ops = {
326         .read   = octeon_read_config,
327         .write  = octeon_write_config,
328 };
329 
330 static struct resource octeon_pci_mem_resource = {
331         .start = 0,
332         .end = 0,
333         .name = "Octeon PCI MEM",
334         .flags = IORESOURCE_MEM,
335 };
336 
337 /*
338  * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
339  * bridge
340  */
341 static struct resource octeon_pci_io_resource = {
342         .start = 0x4000,
343         .end = OCTEON_PCI_IOSPACE_SIZE - 1,
344         .name = "Octeon PCI IO",
345         .flags = IORESOURCE_IO,
346 };
347 
348 static struct pci_controller octeon_pci_controller = {
349         .pci_ops = &octeon_pci_ops,
350         .mem_resource = &octeon_pci_mem_resource,
351         .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
352         .io_resource = &octeon_pci_io_resource,
353         .io_offset = 0,
354         .io_map_base = OCTEON_PCI_IOSPACE_BASE,
355 };
356 
357 
358 /*
359  * Low level initialize the Octeon PCI controller
360  */
361 static void octeon_pci_initialize(void)
362 {
363         union cvmx_pci_cfg01 cfg01;
364         union cvmx_npi_ctl_status ctl_status;
365         union cvmx_pci_ctl_status_2 ctl_status_2;
366         union cvmx_pci_cfg19 cfg19;
367         union cvmx_pci_cfg16 cfg16;
368         union cvmx_pci_cfg22 cfg22;
369         union cvmx_pci_cfg56 cfg56;
370 
371         /* Reset the PCI Bus */
372         cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
373         cvmx_read_csr(CVMX_CIU_SOFT_PRST);
374 
375         udelay(2000);           /* Hold PCI reset for 2 ms */
376 
377         ctl_status.u64 = 0;     /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
378         ctl_status.s.max_word = 1;
379         ctl_status.s.timer = 1;
380         cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
381 
382         /* Deassert PCI reset and advertize PCX Host Mode Device Capability
383            (64b) */
384         cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
385         cvmx_read_csr(CVMX_CIU_SOFT_PRST);
386 
387         udelay(2000);           /* Wait 2 ms after deasserting PCI reset */
388 
389         ctl_status_2.u32 = 0;
390         ctl_status_2.s.tsr_hwm = 1;     /* Initializes to 0.  Must be set
391                                            before any PCI reads. */
392         ctl_status_2.s.bar2pres = 1;    /* Enable BAR2 */
393         ctl_status_2.s.bar2_enb = 1;
394         ctl_status_2.s.bar2_cax = 1;    /* Don't use L2 */
395         ctl_status_2.s.bar2_esx = 1;
396         ctl_status_2.s.pmo_amod = 1;    /* Round robin priority */
397         if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
398                 /* BAR1 hole */
399                 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
400                 ctl_status_2.s.bb1_siz = 1;  /* BAR1 is 2GB */
401                 ctl_status_2.s.bb_ca = 1;    /* Don't use L2 with big bars */
402                 ctl_status_2.s.bb_es = 1;    /* Big bar in byte swap mode */
403                 ctl_status_2.s.bb1 = 1;      /* BAR1 is big */
404                 ctl_status_2.s.bb0 = 1;      /* BAR0 is big */
405         }
406 
407         octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
408         udelay(2000);           /* Wait 2 ms before doing PCI reads */
409 
410         ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
411         pr_notice("PCI Status: %s %s-bit\n",
412                   ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
413                   ctl_status_2.s.ap_64ad ? "64" : "32");
414 
415         if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
416                 union cvmx_pci_cnt_reg cnt_reg_start;
417                 union cvmx_pci_cnt_reg cnt_reg_end;
418                 unsigned long cycles, pci_clock;
419 
420                 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
421                 cycles = read_c0_cvmcount();
422                 udelay(1000);
423                 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
424                 cycles = read_c0_cvmcount() - cycles;
425                 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
426                             (cycles / (mips_hpt_frequency / 1000000));
427                 pr_notice("PCI Clock: %lu MHz\n", pci_clock);
428         }
429 
430         /*
431          * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
432          * in PCI-X mode to allow four outstanding splits. Otherwise,
433          * should not change from its reset value. Don't write PCI_CFG19
434          * in PCI mode (0x82000001 reset value), write it to 0x82000004
435          * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
436          * MRBCM -> must be one.
437          */
438         if (ctl_status_2.s.ap_pcix) {
439                 cfg19.u32 = 0;
440                 /*
441                  * Target Delayed/Split request outstanding maximum
442                  * count. [1..31] and 0=32.  NOTE: If the user
443                  * programs these bits beyond the Designed Maximum
444                  * outstanding count, then the designed maximum table
445                  * depth will be used instead.  No additional
446                  * Deferred/Split transactions will be accepted if
447                  * this outstanding maximum count is
448                  * reached. Furthermore, no additional deferred/split
449                  * transactions will be accepted if the I/O delay/ I/O
450                  * Split Request outstanding maximum is reached.
451                  */
452                 cfg19.s.tdomc = 4;
453                 /*
454                  * Master Deferred Read Request Outstanding Max Count
455                  * (PCI only).  CR4C[26:24] Max SAC cycles MAX DAC
456                  * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
457                  * 5 2 110 6 3 111 7 3 For example, if these bits are
458                  * programmed to 100, the core can support 2 DAC
459                  * cycles, 4 SAC cycles or a combination of 1 DAC and
460                  * 2 SAC cycles. NOTE: For the PCI-X maximum
461                  * outstanding split transactions, refer to
462                  * CRE0[22:20].
463                  */
464                 cfg19.s.mdrrmc = 2;
465                 /*
466                  * Master Request (Memory Read) Byte Count/Byte Enable
467                  * select. 0 = Byte Enables valid. In PCI mode, a
468                  * burst transaction cannot be performed using Memory
469                  * Read command=4?h6. 1 = DWORD Byte Count valid
470                  * (default). In PCI Mode, the memory read byte
471                  * enables are automatically generated by the
472                  * core. Note: N3 Master Request transaction sizes are
473                  * always determined through the
474                  * am_attr[<35:32>|<7:0>] field.
475                  */
476                 cfg19.s.mrbcm = 1;
477                 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
478         }
479 
480 
481         cfg01.u32 = 0;
482         cfg01.s.msae = 1;       /* Memory Space Access Enable */
483         cfg01.s.me = 1;         /* Master Enable */
484         cfg01.s.pee = 1;        /* PERR# Enable */
485         cfg01.s.see = 1;        /* System Error Enable */
486         cfg01.s.fbbe = 1;       /* Fast Back to Back Transaction Enable */
487 
488         octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
489 
490 #ifdef USE_OCTEON_INTERNAL_ARBITER
491         /*
492          * When OCTEON is a PCI host, most systems will use OCTEON's
493          * internal arbiter, so must enable it before any PCI/PCI-X
494          * traffic can occur.
495          */
496         {
497                 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
498 
499                 pci_int_arb_cfg.u64 = 0;
500                 pci_int_arb_cfg.s.en = 1;       /* Internal arbiter enable */
501                 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
502         }
503 #endif  /* USE_OCTEON_INTERNAL_ARBITER */
504 
505         /*
506          * Preferably written to 1 to set MLTD. [RDSATI,TRTAE,
507          * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
508          * 1..7.
509          */
510         cfg16.u32 = 0;
511         cfg16.s.mltd = 1;       /* Master Latency Timer Disable */
512         octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
513 
514         /*
515          * Should be written to 0x4ff00. MTTV -> must be zero.
516          * FLUSH -> must be 1. MRV -> should be 0xFF.
517          */
518         cfg22.u32 = 0;
519         /* Master Retry Value [1..255] and 0=infinite */
520         cfg22.s.mrv = 0xff;
521         /*
522          * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
523          * N3K operation.
524          */
525         cfg22.s.flush = 1;
526         octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
527 
528         /*
529          * MOST Indicates the maximum number of outstanding splits (in -1
530          * notation) when OCTEON is in PCI-X mode.  PCI-X performance is
531          * affected by the MOST selection.  Should generally be written
532          * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
533          * depending on the desired MOST of 3, 2, 1, or 0, respectively.
534          */
535         cfg56.u32 = 0;
536         cfg56.s.pxcid = 7;      /* RO - PCI-X Capability ID */
537         cfg56.s.ncp = 0xe8;     /* RO - Next Capability Pointer */
538         cfg56.s.dpere = 1;      /* Data Parity Error Recovery Enable */
539         cfg56.s.roe = 1;        /* Relaxed Ordering Enable */
540         cfg56.s.mmbc = 1;       /* Maximum Memory Byte Count
541                                    [0=512B,1=1024B,2=2048B,3=4096B] */
542         cfg56.s.most = 3;       /* Maximum outstanding Split transactions [0=1
543                                    .. 7=32] */
544 
545         octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
546 
547         /*
548          * Affects PCI performance when OCTEON services reads to its
549          * BAR1/BAR2. Refer to Section 10.6.1.  The recommended values are
550          * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
551          * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
552          * these values need to be changed so they won't possibly prefetch off
553          * of the end of memory if PCI is DMAing a buffer at the end of
554          * memory. Note that these values differ from their reset values.
555          */
556         octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
557         octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
558         octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
559 }
560 
561 
562 /*
563  * Initialize the Octeon PCI controller
564  */
565 static int __init octeon_pci_setup(void)
566 {
567         union cvmx_npi_mem_access_subidx mem_access;
568         int index;
569 
570         /* Only these chips have PCI */
571         if (octeon_has_feature(OCTEON_FEATURE_PCIE))
572                 return 0;
573 
574         /* Point pcibios_map_irq() to the PCI version of it */
575         octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
576 
577         /* Only use the big bars on chips that support it */
578         if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
579             OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
580             OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
581                 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
582         else
583                 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
584 
585         if (!octeon_is_pci_host()) {
586                 pr_notice("Not in host mode, PCI Controller not initialized\n");
587                 return 0;
588         }
589 
590         /* PCI I/O and PCI MEM values */
591         set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
592         ioport_resource.start = 0;
593         ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
594 
595         pr_notice("%s Octeon big bar support\n",
596                   (octeon_dma_bar_type ==
597                   OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
598 
599         octeon_pci_initialize();
600 
601         mem_access.u64 = 0;
602         mem_access.s.esr = 1;   /* Endian-Swap on read. */
603         mem_access.s.esw = 1;   /* Endian-Swap on write. */
604         mem_access.s.nsr = 0;   /* No-Snoop on read. */
605         mem_access.s.nsw = 0;   /* No-Snoop on write. */
606         mem_access.s.ror = 0;   /* Relax Read on read. */
607         mem_access.s.row = 0;   /* Relax Order on write. */
608         mem_access.s.ba = 0;    /* PCI Address bits [63:36]. */
609         cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
610 
611         /*
612          * Remap the Octeon BAR 2 above all 32 bit devices
613          * (0x8000000000ul).  This is done here so it is remapped
614          * before the readl()'s below. We don't want BAR2 overlapping
615          * with BAR0/BAR1 during these reads.
616          */
617         octeon_npi_write32(CVMX_NPI_PCI_CFG08,
618                            (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
619         octeon_npi_write32(CVMX_NPI_PCI_CFG09,
620                            (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
621 
622         if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
623                 /* Remap the Octeon BAR 0 to 0-2GB */
624                 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
625                 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
626 
627                 /*
628                  * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
629                  * BAR 1 hole).
630                  */
631                 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
632                 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
633 
634                 /* BAR1 movable mappings set for identity mapping */
635                 octeon_bar1_pci_phys = 0x80000000ull;
636                 for (index = 0; index < 32; index++) {
637                         union cvmx_pci_bar1_indexx bar1_index;
638 
639                         bar1_index.u32 = 0;
640                         /* Address bits[35:22] sent to L2C */
641                         bar1_index.s.addr_idx =
642                                 (octeon_bar1_pci_phys >> 22) + index;
643                         /* Don't put PCI accesses in L2. */
644                         bar1_index.s.ca = 1;
645                         /* Endian Swap Mode */
646                         bar1_index.s.end_swp = 1;
647                         /* Set '1' when the selected address range is valid. */
648                         bar1_index.s.addr_v = 1;
649                         octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
650                                            bar1_index.u32);
651                 }
652 
653                 /* Devices go after BAR1 */
654                 octeon_pci_mem_resource.start =
655                         OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
656                         (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
657                 octeon_pci_mem_resource.end =
658                         octeon_pci_mem_resource.start + (1ul << 30);
659         } else {
660                 /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
661                 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
662                 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
663 
664                 /* Remap the Octeon BAR 1 to map 0-128MB */
665                 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
666                 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
667 
668                 /* BAR1 movable regions contiguous to cover the swiotlb */
669                 octeon_bar1_pci_phys =
670                         virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
671 
672                 for (index = 0; index < 32; index++) {
673                         union cvmx_pci_bar1_indexx bar1_index;
674 
675                         bar1_index.u32 = 0;
676                         /* Address bits[35:22] sent to L2C */
677                         bar1_index.s.addr_idx =
678                                 (octeon_bar1_pci_phys >> 22) + index;
679                         /* Don't put PCI accesses in L2. */
680                         bar1_index.s.ca = 1;
681                         /* Endian Swap Mode */
682                         bar1_index.s.end_swp = 1;
683                         /* Set '1' when the selected address range is valid. */
684                         bar1_index.s.addr_v = 1;
685                         octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
686                                            bar1_index.u32);
687                 }
688 
689                 /* Devices go after BAR0 */
690                 octeon_pci_mem_resource.start =
691                         OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
692                         (4ul << 10);
693                 octeon_pci_mem_resource.end =
694                         octeon_pci_mem_resource.start + (1ul << 30);
695         }
696 
697         register_pci_controller(&octeon_pci_controller);
698 
699         /*
700          * Clear any errors that might be pending from before the bus
701          * was setup properly.
702          */
703         cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
704 
705         if (IS_ERR(platform_device_register_simple("octeon_pci_edac",
706                                                    -1, NULL, 0)))
707                 pr_err("Registration of co_pci_edac failed!\n");
708 
709         octeon_pci_dma_init();
710 
711         return 0;
712 }
713 
714 arch_initcall(octeon_pci_setup);
715 

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