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TOMOYO Linux Cross Reference
Linux/arch/powerpc/include/asm/reg.h

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  1 /*
  2  * Contains the definition of registers common to all PowerPC variants.
  3  * If a register definition has been changed in a different PowerPC
  4  * variant, we will case it in #ifndef XXX ... #endif, and have the
  5  * number used in the Programming Environments Manual For 32-Bit
  6  * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
  7  */
  8 
  9 #ifndef _ASM_POWERPC_REG_H
 10 #define _ASM_POWERPC_REG_H
 11 #ifdef __KERNEL__
 12 
 13 #include <linux/stringify.h>
 14 #include <asm/cputable.h>
 15 
 16 /* Pickup Book E specific registers. */
 17 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 18 #include <asm/reg_booke.h>
 19 #endif /* CONFIG_BOOKE || CONFIG_40x */
 20 
 21 #ifdef CONFIG_FSL_EMB_PERFMON
 22 #include <asm/reg_fsl_emb.h>
 23 #endif
 24 
 25 #ifdef CONFIG_8xx
 26 #include <asm/reg_8xx.h>
 27 #endif /* CONFIG_8xx */
 28 
 29 #define MSR_SF_LG       63              /* Enable 64 bit mode */
 30 #define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
 31 #define MSR_HV_LG       60              /* Hypervisor state */
 32 #define MSR_TS_T_LG     34              /* Trans Mem state: Transactional */
 33 #define MSR_TS_S_LG     33              /* Trans Mem state: Suspended */
 34 #define MSR_TS_LG       33              /* Trans Mem state (2 bits) */
 35 #define MSR_TM_LG       32              /* Trans Mem Available */
 36 #define MSR_VEC_LG      25              /* Enable AltiVec */
 37 #define MSR_VSX_LG      23              /* Enable VSX */
 38 #define MSR_POW_LG      18              /* Enable Power Management */
 39 #define MSR_WE_LG       18              /* Wait State Enable */
 40 #define MSR_TGPR_LG     17              /* TLB Update registers in use */
 41 #define MSR_CE_LG       17              /* Critical Interrupt Enable */
 42 #define MSR_ILE_LG      16              /* Interrupt Little Endian */
 43 #define MSR_EE_LG       15              /* External Interrupt Enable */
 44 #define MSR_PR_LG       14              /* Problem State / Privilege Level */
 45 #define MSR_FP_LG       13              /* Floating Point enable */
 46 #define MSR_ME_LG       12              /* Machine Check Enable */
 47 #define MSR_FE0_LG      11              /* Floating Exception mode 0 */
 48 #define MSR_SE_LG       10              /* Single Step */
 49 #define MSR_BE_LG       9               /* Branch Trace */
 50 #define MSR_DE_LG       9               /* Debug Exception Enable */
 51 #define MSR_FE1_LG      8               /* Floating Exception mode 1 */
 52 #define MSR_IP_LG       6               /* Exception prefix 0x000/0xFFF */
 53 #define MSR_IR_LG       5               /* Instruction Relocate */
 54 #define MSR_DR_LG       4               /* Data Relocate */
 55 #define MSR_PE_LG       3               /* Protection Enable */
 56 #define MSR_PX_LG       2               /* Protection Exclusive Mode */
 57 #define MSR_PMM_LG      2               /* Performance monitor */
 58 #define MSR_RI_LG       1               /* Recoverable Exception */
 59 #define MSR_LE_LG       0               /* Little Endian */
 60 
 61 #ifdef __ASSEMBLY__
 62 #define __MASK(X)       (1<<(X))
 63 #else
 64 #define __MASK(X)       (1UL<<(X))
 65 #endif
 66 
 67 #ifdef CONFIG_PPC64
 68 #define MSR_SF          __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
 69 #define MSR_ISF         __MASK(MSR_ISF_LG)      /* Interrupt 64b mode valid on 630 */
 70 #define MSR_HV          __MASK(MSR_HV_LG)       /* Hypervisor state */
 71 #else
 72 /* so tests for these bits fail on 32-bit */
 73 #define MSR_SF          0
 74 #define MSR_ISF         0
 75 #define MSR_HV          0
 76 #endif
 77 
 78 #define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
 79 #define MSR_VSX         __MASK(MSR_VSX_LG)      /* Enable VSX */
 80 #define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
 81 #define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
 82 #define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
 83 #define MSR_CE          __MASK(MSR_CE_LG)       /* Critical Interrupt Enable */
 84 #define MSR_ILE         __MASK(MSR_ILE_LG)      /* Interrupt Little Endian */
 85 #define MSR_EE          __MASK(MSR_EE_LG)       /* External Interrupt Enable */
 86 #define MSR_PR          __MASK(MSR_PR_LG)       /* Problem State / Privilege Level */
 87 #define MSR_FP          __MASK(MSR_FP_LG)       /* Floating Point enable */
 88 #define MSR_ME          __MASK(MSR_ME_LG)       /* Machine Check Enable */
 89 #define MSR_FE0         __MASK(MSR_FE0_LG)      /* Floating Exception mode 0 */
 90 #define MSR_SE          __MASK(MSR_SE_LG)       /* Single Step */
 91 #define MSR_BE          __MASK(MSR_BE_LG)       /* Branch Trace */
 92 #define MSR_DE          __MASK(MSR_DE_LG)       /* Debug Exception Enable */
 93 #define MSR_FE1         __MASK(MSR_FE1_LG)      /* Floating Exception mode 1 */
 94 #define MSR_IP          __MASK(MSR_IP_LG)       /* Exception prefix 0x000/0xFFF */
 95 #define MSR_IR          __MASK(MSR_IR_LG)       /* Instruction Relocate */
 96 #define MSR_DR          __MASK(MSR_DR_LG)       /* Data Relocate */
 97 #define MSR_PE          __MASK(MSR_PE_LG)       /* Protection Enable */
 98 #define MSR_PX          __MASK(MSR_PX_LG)       /* Protection Exclusive Mode */
 99 #ifndef MSR_PMM
100 #define MSR_PMM         __MASK(MSR_PMM_LG)      /* Performance monitor */
101 #endif
102 #define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
103 #define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
104 
105 #define MSR_TM          __MASK(MSR_TM_LG)       /* Transactional Mem Available */
106 #define MSR_TS_N        0                       /*  Non-transactional */
107 #define MSR_TS_S        __MASK(MSR_TS_S_LG)     /*  Transaction Suspended */
108 #define MSR_TS_T        __MASK(MSR_TS_T_LG)     /*  Transaction Transactional */
109 #define MSR_TS_MASK     (MSR_TS_T | MSR_TS_S)   /* Transaction State bits */
110 #define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
111 #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
112 #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
113 #define MSR_TM_SUSPENDED(x)     (((x) & MSR_TS_MASK) == MSR_TS_S)
114 
115 #if defined(CONFIG_PPC_BOOK3S_64)
116 #define MSR_64BIT       MSR_SF
117 
118 /* Server variant */
119 #define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
120 #define MSR_KERNEL      MSR_ | MSR_64BIT
121 #define MSR_USER32      MSR_ | MSR_PR | MSR_EE
122 #define MSR_USER64      MSR_USER32 | MSR_64BIT
123 #elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
124 /* Default MSR for kernel mode. */
125 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
126 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
127 #endif
128 
129 #ifndef MSR_64BIT
130 #define MSR_64BIT       0
131 #endif
132 
133 /* Floating Point Status and Control Register (FPSCR) Fields */
134 #define FPSCR_FX        0x80000000      /* FPU exception summary */
135 #define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
136 #define FPSCR_VX        0x20000000      /* Invalid operation summary */
137 #define FPSCR_OX        0x10000000      /* Overflow exception summary */
138 #define FPSCR_UX        0x08000000      /* Underflow exception summary */
139 #define FPSCR_ZX        0x04000000      /* Zero-divide exception summary */
140 #define FPSCR_XX        0x02000000      /* Inexact exception summary */
141 #define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
142 #define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
143 #define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
144 #define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
145 #define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
146 #define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
147 #define FPSCR_FR        0x00040000      /* Fraction rounded */
148 #define FPSCR_FI        0x00020000      /* Fraction inexact */
149 #define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
150 #define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
151 #define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
152 #define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
153 #define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
154 #define FPSCR_VE        0x00000080      /* Invalid op exception enable */
155 #define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
156 #define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
157 #define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
158 #define FPSCR_XE        0x00000008      /* FP inexact exception enable */
159 #define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
160 #define FPSCR_RN        0x00000003      /* FPU rounding control */
161 
162 /* Bit definitions for SPEFSCR. */
163 #define SPEFSCR_SOVH    0x80000000      /* Summary integer overflow high */
164 #define SPEFSCR_OVH     0x40000000      /* Integer overflow high */
165 #define SPEFSCR_FGH     0x20000000      /* Embedded FP guard bit high */
166 #define SPEFSCR_FXH     0x10000000      /* Embedded FP sticky bit high */
167 #define SPEFSCR_FINVH   0x08000000      /* Embedded FP invalid operation high */
168 #define SPEFSCR_FDBZH   0x04000000      /* Embedded FP div by zero high */
169 #define SPEFSCR_FUNFH   0x02000000      /* Embedded FP underflow high */
170 #define SPEFSCR_FOVFH   0x01000000      /* Embedded FP overflow high */
171 #define SPEFSCR_FINXS   0x00200000      /* Embedded FP inexact sticky */
172 #define SPEFSCR_FINVS   0x00100000      /* Embedded FP invalid op. sticky */
173 #define SPEFSCR_FDBZS   0x00080000      /* Embedded FP div by zero sticky */
174 #define SPEFSCR_FUNFS   0x00040000      /* Embedded FP underflow sticky */
175 #define SPEFSCR_FOVFS   0x00020000      /* Embedded FP overflow sticky */
176 #define SPEFSCR_MODE    0x00010000      /* Embedded FP mode */
177 #define SPEFSCR_SOV     0x00008000      /* Integer summary overflow */
178 #define SPEFSCR_OV      0x00004000      /* Integer overflow */
179 #define SPEFSCR_FG      0x00002000      /* Embedded FP guard bit */
180 #define SPEFSCR_FX      0x00001000      /* Embedded FP sticky bit */
181 #define SPEFSCR_FINV    0x00000800      /* Embedded FP invalid operation */
182 #define SPEFSCR_FDBZ    0x00000400      /* Embedded FP div by zero */
183 #define SPEFSCR_FUNF    0x00000200      /* Embedded FP underflow */
184 #define SPEFSCR_FOVF    0x00000100      /* Embedded FP overflow */
185 #define SPEFSCR_FINXE   0x00000040      /* Embedded FP inexact enable */
186 #define SPEFSCR_FINVE   0x00000020      /* Embedded FP invalid op. enable */
187 #define SPEFSCR_FDBZE   0x00000010      /* Embedded FP div by zero enable */
188 #define SPEFSCR_FUNFE   0x00000008      /* Embedded FP underflow enable */
189 #define SPEFSCR_FOVFE   0x00000004      /* Embedded FP overflow enable */
190 #define SPEFSCR_FRMC    0x00000003      /* Embedded FP rounding mode control */
191 
192 /* Special Purpose Registers (SPRNs)*/
193 
194 #ifdef CONFIG_40x
195 #define SPRN_PID        0x3B1   /* Process ID */
196 #else
197 #define SPRN_PID        0x030   /* Process ID */
198 #ifdef CONFIG_BOOKE
199 #define SPRN_PID0       SPRN_PID/* Process ID Register 0 */
200 #endif
201 #endif
202 
203 #define SPRN_CTR        0x009   /* Count Register */
204 #define SPRN_DSCR       0x11
205 #define SPRN_CFAR       0x1c    /* Come From Address Register */
206 #define SPRN_AMR        0x1d    /* Authority Mask Register */
207 #define SPRN_UAMOR      0x9d    /* User Authority Mask Override Register */
208 #define SPRN_AMOR       0x15d   /* Authority Mask Override Register */
209 #define SPRN_ACOP       0x1F    /* Available Coprocessor Register */
210 #define SPRN_TFIAR      0x81    /* Transaction Failure Inst Addr   */
211 #define SPRN_TEXASR     0x82    /* Transaction EXception & Summary */
212 #define   TEXASR_FS     __MASK(63-36)   /* Transaction Failure Summary */
213 #define SPRN_TEXASRU    0x83    /* ''      ''      ''    Upper 32  */
214 #define SPRN_TFHAR      0x80    /* Transaction Failure Handler Addr */
215 #define SPRN_CTRLF      0x088
216 #define SPRN_CTRLT      0x098
217 #define   CTRL_CT       0xc0000000      /* current thread */
218 #define   CTRL_CT0      0x80000000      /* thread 0 */
219 #define   CTRL_CT1      0x40000000      /* thread 1 */
220 #define   CTRL_TE       0x00c00000      /* thread enable */
221 #define   CTRL_RUNLATCH 0x1
222 #define SPRN_DAWR       0xB4
223 #define SPRN_DAWRX      0xBC
224 #define   DAWRX_USER    (1UL << 0)
225 #define   DAWRX_KERNEL  (1UL << 1)
226 #define   DAWRX_HYP     (1UL << 2)
227 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
228 #define SPRN_DABR2      0x13D   /* e300 */
229 #define SPRN_DABRX      0x3F7   /* Data Address Breakpoint Register Extension */
230 #define   DABRX_USER    (1UL << 0)
231 #define   DABRX_KERNEL  (1UL << 1)
232 #define   DABRX_HYP     (1UL << 2)
233 #define   DABRX_BTI     (1UL << 3)
234 #define   DABRX_ALL     (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
235 #define SPRN_DAR        0x013   /* Data Address Register */
236 #define SPRN_DBCR       0x136   /* e300 Data Breakpoint Control Reg */
237 #define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
238 #define   DSISR_NOHPTE          0x40000000      /* no translation found */
239 #define   DSISR_PROTFAULT       0x08000000      /* protection fault */
240 #define   DSISR_ISSTORE         0x02000000      /* access was a store */
241 #define   DSISR_DABRMATCH       0x00400000      /* hit data breakpoint */
242 #define   DSISR_NOSEGMENT       0x00200000      /* STAB/SLB miss */
243 #define   DSISR_KEYFAULT        0x00200000      /* Key fault */
244 #define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
245 #define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
246 #define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
247 #define SPRN_TBWU       0x11D   /* Time Base Upper Register (super, R/W) */
248 #define SPRN_SPURR      0x134   /* Scaled PURR */
249 #define SPRN_HSPRG0     0x130   /* Hypervisor Scratch 0 */
250 #define SPRN_HSPRG1     0x131   /* Hypervisor Scratch 1 */
251 #define SPRN_HDSISR     0x132
252 #define SPRN_HDAR       0x133
253 #define SPRN_HDEC       0x136   /* Hypervisor Decrementer */
254 #define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
255 #define SPRN_RMOR       0x138   /* Real mode offset register */
256 #define SPRN_HRMOR      0x139   /* Real mode offset register */
257 #define SPRN_HSRR0      0x13A   /* Hypervisor Save/Restore 0 */
258 #define SPRN_HSRR1      0x13B   /* Hypervisor Save/Restore 1 */
259 /* HFSCR and FSCR bit numbers are the same */
260 #define FSCR_TAR_LG     8       /* Enable Target Address Register */
261 #define FSCR_EBB_LG     7       /* Enable Event Based Branching */
262 #define FSCR_TM_LG      5       /* Enable Transactional Memory */
263 #define FSCR_PM_LG      4       /* Enable prob/priv access to PMU SPRs */
264 #define FSCR_BHRB_LG    3       /* Enable Branch History Rolling Buffer*/
265 #define FSCR_DSCR_LG    2       /* Enable Data Stream Control Register */
266 #define FSCR_VECVSX_LG  1       /* Enable VMX/VSX  */
267 #define FSCR_FP_LG      0       /* Enable Floating Point */
268 #define SPRN_FSCR       0x099   /* Facility Status & Control Register */
269 #define   FSCR_TAR      __MASK(FSCR_TAR_LG)
270 #define   FSCR_EBB      __MASK(FSCR_EBB_LG)
271 #define   FSCR_DSCR     __MASK(FSCR_DSCR_LG)
272 #define SPRN_HFSCR      0xbe    /* HV=1 Facility Status & Control Register */
273 #define   HFSCR_TAR     __MASK(FSCR_TAR_LG)
274 #define   HFSCR_EBB     __MASK(FSCR_EBB_LG)
275 #define   HFSCR_TM      __MASK(FSCR_TM_LG)
276 #define   HFSCR_PM      __MASK(FSCR_PM_LG)
277 #define   HFSCR_BHRB    __MASK(FSCR_BHRB_LG)
278 #define   HFSCR_DSCR    __MASK(FSCR_DSCR_LG)
279 #define   HFSCR_VECVSX  __MASK(FSCR_VECVSX_LG)
280 #define   HFSCR_FP      __MASK(FSCR_FP_LG)
281 #define SPRN_TAR        0x32f   /* Target Address Register */
282 #define SPRN_LPCR       0x13E   /* LPAR Control Register */
283 #define   LPCR_VPM0     (1ul << (63-0))
284 #define   LPCR_VPM1     (1ul << (63-1))
285 #define   LPCR_ISL      (1ul << (63-2))
286 #define   LPCR_VC_SH    (63-2)
287 #define   LPCR_DPFD_SH  (63-11)
288 #define   LPCR_VRMASD   (0x1ful << (63-16))
289 #define   LPCR_VRMA_L   (1ul << (63-12))
290 #define   LPCR_VRMA_LP0 (1ul << (63-15))
291 #define   LPCR_VRMA_LP1 (1ul << (63-16))
292 #define   LPCR_VRMASD_SH (63-16)
293 #define   LPCR_RMLS    0x1C000000      /* impl dependent rmo limit sel */
294 #define   LPCR_RMLS_SH  (63-37)
295 #define   LPCR_ILE     0x02000000      /* !HV irqs set MSR:LE */
296 #define   LPCR_AIL_0    0x00000000      /* MMU off exception offset 0x0 */
297 #define   LPCR_AIL_3    0x01800000      /* MMU on exception offset 0xc00...4xxx */
298 #define   LPCR_PECE     0x00007000      /* powersave exit cause enable */
299 #define     LPCR_PECE0  0x00004000      /* ext. exceptions can cause exit */
300 #define     LPCR_PECE1  0x00002000      /* decrementer can cause exit */
301 #define     LPCR_PECE2  0x00001000      /* machine check etc can cause exit */
302 #define   LPCR_MER      0x00000800      /* Mediated External Exception */
303 #define   LPCR_MER_SH   11
304 #define   LPCR_LPES    0x0000000c
305 #define   LPCR_LPES0   0x00000008      /* LPAR Env selector 0 */
306 #define   LPCR_LPES1   0x00000004      /* LPAR Env selector 1 */
307 #define   LPCR_LPES_SH  2
308 #define   LPCR_RMI     0x00000002      /* real mode is cache inhibit */
309 #define   LPCR_HDICE   0x00000001      /* Hyp Decr enable (HV,PR,EE) */
310 #ifndef SPRN_LPID
311 #define SPRN_LPID       0x13F   /* Logical Partition Identifier */
312 #endif
313 #define   LPID_RSVD     0x3ff           /* Reserved LPID for partn switching */
314 #define SPRN_HMER       0x150   /* Hardware m? error recovery */
315 #define SPRN_HMEER      0x151   /* Hardware m? enable error recovery */
316 #define SPRN_HEIR       0x153   /* Hypervisor Emulated Instruction Register */
317 #define SPRN_TLBINDEXR  0x154   /* P7 TLB control register */
318 #define SPRN_TLBVPNR    0x155   /* P7 TLB control register */
319 #define SPRN_TLBRPNR    0x156   /* P7 TLB control register */
320 #define SPRN_TLBLPIDR   0x157   /* P7 TLB control register */
321 #define SPRN_DBAT0L     0x219   /* Data BAT 0 Lower Register */
322 #define SPRN_DBAT0U     0x218   /* Data BAT 0 Upper Register */
323 #define SPRN_DBAT1L     0x21B   /* Data BAT 1 Lower Register */
324 #define SPRN_DBAT1U     0x21A   /* Data BAT 1 Upper Register */
325 #define SPRN_DBAT2L     0x21D   /* Data BAT 2 Lower Register */
326 #define SPRN_DBAT2U     0x21C   /* Data BAT 2 Upper Register */
327 #define SPRN_DBAT3L     0x21F   /* Data BAT 3 Lower Register */
328 #define SPRN_DBAT3U     0x21E   /* Data BAT 3 Upper Register */
329 #define SPRN_DBAT4L     0x239   /* Data BAT 4 Lower Register */
330 #define SPRN_DBAT4U     0x238   /* Data BAT 4 Upper Register */
331 #define SPRN_DBAT5L     0x23B   /* Data BAT 5 Lower Register */
332 #define SPRN_DBAT5U     0x23A   /* Data BAT 5 Upper Register */
333 #define SPRN_DBAT6L     0x23D   /* Data BAT 6 Lower Register */
334 #define SPRN_DBAT6U     0x23C   /* Data BAT 6 Upper Register */
335 #define SPRN_DBAT7L     0x23F   /* Data BAT 7 Lower Register */
336 #define SPRN_DBAT7U     0x23E   /* Data BAT 7 Upper Register */
337 #define SPRN_PPR        0x380   /* SMT Thread status Register */
338 
339 #define SPRN_DEC        0x016           /* Decrement Register */
340 #define SPRN_DER        0x095           /* Debug Enable Regsiter */
341 #define DER_RSTE        0x40000000      /* Reset Interrupt */
342 #define DER_CHSTPE      0x20000000      /* Check Stop */
343 #define DER_MCIE        0x10000000      /* Machine Check Interrupt */
344 #define DER_EXTIE       0x02000000      /* External Interrupt */
345 #define DER_ALIE        0x01000000      /* Alignment Interrupt */
346 #define DER_PRIE        0x00800000      /* Program Interrupt */
347 #define DER_FPUVIE      0x00400000      /* FP Unavailable Interrupt */
348 #define DER_DECIE       0x00200000      /* Decrementer Interrupt */
349 #define DER_SYSIE       0x00040000      /* System Call Interrupt */
350 #define DER_TRE         0x00020000      /* Trace Interrupt */
351 #define DER_SEIE        0x00004000      /* FP SW Emulation Interrupt */
352 #define DER_ITLBMSE     0x00002000      /* Imp. Spec. Instruction TLB Miss */
353 #define DER_ITLBERE     0x00001000      /* Imp. Spec. Instruction TLB Error */
354 #define DER_DTLBMSE     0x00000800      /* Imp. Spec. Data TLB Miss */
355 #define DER_DTLBERE     0x00000400      /* Imp. Spec. Data TLB Error */
356 #define DER_LBRKE       0x00000008      /* Load/Store Breakpoint Interrupt */
357 #define DER_IBRKE       0x00000004      /* Instruction Breakpoint Interrupt */
358 #define DER_EBRKE       0x00000002      /* External Breakpoint Interrupt */
359 #define DER_DPIE        0x00000001      /* Dev. Port Nonmaskable Request */
360 #define SPRN_DMISS      0x3D0           /* Data TLB Miss Register */
361 #define SPRN_EAR        0x11A           /* External Address Register */
362 #define SPRN_HASH1      0x3D2           /* Primary Hash Address Register */
363 #define SPRN_HASH2      0x3D3           /* Secondary Hash Address Resgister */
364 #define SPRN_HID0       0x3F0           /* Hardware Implementation Register 0 */
365 #define HID0_HDICE_SH   (63 - 23)       /* 970 HDEC interrupt enable */
366 #define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
367 #define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
368 #define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
369 #define HID0_SBCLK      (1<<27)
370 #define HID0_EICE       (1<<26)
371 #define HID0_TBEN       (1<<26)         /* Timebase enable - 745x */
372 #define HID0_ECLK       (1<<25)
373 #define HID0_PAR        (1<<24)
374 #define HID0_STEN       (1<<24)         /* Software table search enable - 745x */
375 #define HID0_HIGH_BAT   (1<<23)         /* Enable high BATs - 7455 */
376 #define HID0_DOZE       (1<<23)
377 #define HID0_NAP        (1<<22)
378 #define HID0_SLEEP      (1<<21)
379 #define HID0_DPM        (1<<20)
380 #define HID0_BHTCLR     (1<<18)         /* Clear branch history table - 7450 */
381 #define HID0_XAEN       (1<<17)         /* Extended addressing enable - 7450 */
382 #define HID0_NHR        (1<<16)         /* Not hard reset (software bit-7450)*/
383 #define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
384 #define HID0_DCE        (1<<14)         /* Data Cache Enable */
385 #define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
386 #define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
387 #define HID0_ICFI       (1<<11)         /* Instr. Cache Flash Invalidate */
388 #define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
389 #define HID0_SPD        (1<<9)          /* Speculative disable */
390 #define HID0_DAPUEN     (1<<8)          /* Debug APU enable */
391 #define HID0_SGE        (1<<7)          /* Store Gathering Enable */
392 #define HID0_SIED       (1<<7)          /* Serial Instr. Execution [Disable] */
393 #define HID0_DCFA       (1<<6)          /* Data Cache Flush Assist */
394 #define HID0_LRSTK      (1<<4)          /* Link register stack - 745x */
395 #define HID0_BTIC       (1<<5)          /* Branch Target Instr Cache Enable */
396 #define HID0_ABE        (1<<3)          /* Address Broadcast Enable */
397 #define HID0_FOLD       (1<<3)          /* Branch Folding enable - 745x */
398 #define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
399 #define HID0_BTCD       (1<<1)          /* Branch target cache disable */
400 #define HID0_NOPDST     (1<<1)          /* No-op dst, dstt, etc. instr. */
401 #define HID0_NOPTI      (1<<0)          /* No-op dcbt and dcbst instr. */
402 
403 #define SPRN_HID1       0x3F1           /* Hardware Implementation Register 1 */
404 #ifdef CONFIG_6xx
405 #define HID1_EMCP       (1<<31)         /* 7450 Machine Check Pin Enable */
406 #define HID1_DFS        (1<<22)         /* 7447A Dynamic Frequency Scaling */
407 #define HID1_PC0        (1<<16)         /* 7450 PLL_CFG[0] */
408 #define HID1_PC1        (1<<15)         /* 7450 PLL_CFG[1] */
409 #define HID1_PC2        (1<<14)         /* 7450 PLL_CFG[2] */
410 #define HID1_PC3        (1<<13)         /* 7450 PLL_CFG[3] */
411 #define HID1_SYNCBE     (1<<11)         /* 7450 ABE for sync, eieio */
412 #define HID1_ABE        (1<<10)         /* 7450 Address Broadcast Enable */
413 #define HID1_PS         (1<<16)         /* 750FX PLL selection */
414 #endif
415 #define SPRN_HID2       0x3F8           /* Hardware Implementation Register 2 */
416 #define SPRN_HID2_GEKKO 0x398           /* Gekko HID2 Register */
417 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
418 #define SPRN_IABR2      0x3FA           /* 83xx */
419 #define SPRN_IBCR       0x135           /* 83xx Insn Breakpoint Control Reg */
420 #define SPRN_HID4       0x3F4           /* 970 HID4 */
421 #define  HID4_LPES0      (1ul << (63-0)) /* LPAR env. sel. bit 0 */
422 #define  HID4_RMLS2_SH   (63 - 2)       /* Real mode limit bottom 2 bits */
423 #define  HID4_LPID5_SH   (63 - 6)       /* partition ID bottom 4 bits */
424 #define  HID4_RMOR_SH    (63 - 22)      /* real mode offset (16 bits) */
425 #define  HID4_LPES1      (1 << (63-57)) /* LPAR env. sel. bit 1 */
426 #define  HID4_RMLS0_SH   (63 - 58)      /* Real mode limit top bit */
427 #define  HID4_LPID1_SH   0              /* partition ID top 2 bits */
428 #define SPRN_HID4_GEKKO 0x3F3           /* Gekko HID4 */
429 #define SPRN_HID5       0x3F6           /* 970 HID5 */
430 #define SPRN_HID6       0x3F9   /* BE HID 6 */
431 #define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
432 #define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
433 #define SPRN_TSC_CELL   0x399   /* Thread switch control on Cell */
434 #define   TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
435 #define   TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
436 #define   TSC_CELL_EE_ENABLE    0x100000 /* External Interrupt */
437 #define   TSC_CELL_EE_BOOST     0x080000 /* External Interrupt Boost */
438 #define SPRN_TSC        0x3FD   /* Thread switch control on others */
439 #define SPRN_TST        0x3FC   /* Thread switch timeout on others */
440 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
441 #define SPRN_IAC1       0x3F4           /* Instruction Address Compare 1 */
442 #define SPRN_IAC2       0x3F5           /* Instruction Address Compare 2 */
443 #endif
444 #define SPRN_IBAT0L     0x211           /* Instruction BAT 0 Lower Register */
445 #define SPRN_IBAT0U     0x210           /* Instruction BAT 0 Upper Register */
446 #define SPRN_IBAT1L     0x213           /* Instruction BAT 1 Lower Register */
447 #define SPRN_IBAT1U     0x212           /* Instruction BAT 1 Upper Register */
448 #define SPRN_IBAT2L     0x215           /* Instruction BAT 2 Lower Register */
449 #define SPRN_IBAT2U     0x214           /* Instruction BAT 2 Upper Register */
450 #define SPRN_IBAT3L     0x217           /* Instruction BAT 3 Lower Register */
451 #define SPRN_IBAT3U     0x216           /* Instruction BAT 3 Upper Register */
452 #define SPRN_IBAT4L     0x231           /* Instruction BAT 4 Lower Register */
453 #define SPRN_IBAT4U     0x230           /* Instruction BAT 4 Upper Register */
454 #define SPRN_IBAT5L     0x233           /* Instruction BAT 5 Lower Register */
455 #define SPRN_IBAT5U     0x232           /* Instruction BAT 5 Upper Register */
456 #define SPRN_IBAT6L     0x235           /* Instruction BAT 6 Lower Register */
457 #define SPRN_IBAT6U     0x234           /* Instruction BAT 6 Upper Register */
458 #define SPRN_IBAT7L     0x237           /* Instruction BAT 7 Lower Register */
459 #define SPRN_IBAT7U     0x236           /* Instruction BAT 7 Upper Register */
460 #define SPRN_ICMP       0x3D5           /* Instruction TLB Compare Register */
461 #define SPRN_ICTC       0x3FB   /* Instruction Cache Throttling Control Reg */
462 #define SPRN_ICTRL      0x3F3   /* 1011 7450 icache and interrupt ctrl */
463 #define ICTRL_EICE      0x08000000      /* enable icache parity errs */
464 #define ICTRL_EDC       0x04000000      /* enable dcache parity errs */
465 #define ICTRL_EICP      0x00000100      /* enable icache par. check */
466 #define SPRN_IMISS      0x3D4           /* Instruction TLB Miss Register */
467 #define SPRN_IMMR       0x27E           /* Internal Memory Map Register */
468 #define SPRN_L2CR       0x3F9           /* Level 2 Cache Control Regsiter */
469 #define SPRN_L2CR2      0x3f8
470 #define L2CR_L2E                0x80000000      /* L2 enable */
471 #define L2CR_L2PE               0x40000000      /* L2 parity enable */
472 #define L2CR_L2SIZ_MASK         0x30000000      /* L2 size mask */
473 #define L2CR_L2SIZ_256KB        0x10000000      /* L2 size 256KB */
474 #define L2CR_L2SIZ_512KB        0x20000000      /* L2 size 512KB */
475 #define L2CR_L2SIZ_1MB          0x30000000      /* L2 size 1MB */
476 #define L2CR_L2CLK_MASK         0x0e000000      /* L2 clock mask */
477 #define L2CR_L2CLK_DISABLED     0x00000000      /* L2 clock disabled */
478 #define L2CR_L2CLK_DIV1         0x02000000      /* L2 clock / 1 */
479 #define L2CR_L2CLK_DIV1_5       0x04000000      /* L2 clock / 1.5 */
480 #define L2CR_L2CLK_DIV2         0x08000000      /* L2 clock / 2 */
481 #define L2CR_L2CLK_DIV2_5       0x0a000000      /* L2 clock / 2.5 */
482 #define L2CR_L2CLK_DIV3         0x0c000000      /* L2 clock / 3 */
483 #define L2CR_L2RAM_MASK         0x01800000      /* L2 RAM type mask */
484 #define L2CR_L2RAM_FLOW         0x00000000      /* L2 RAM flow through */
485 #define L2CR_L2RAM_PIPE         0x01000000      /* L2 RAM pipelined */
486 #define L2CR_L2RAM_PIPE_LW      0x01800000      /* L2 RAM pipelined latewr */
487 #define L2CR_L2DO               0x00400000      /* L2 data only */
488 #define L2CR_L2I                0x00200000      /* L2 global invalidate */
489 #define L2CR_L2CTL              0x00100000      /* L2 RAM control */
490 #define L2CR_L2WT               0x00080000      /* L2 write-through */
491 #define L2CR_L2TS               0x00040000      /* L2 test support */
492 #define L2CR_L2OH_MASK          0x00030000      /* L2 output hold mask */
493 #define L2CR_L2OH_0_5           0x00000000      /* L2 output hold 0.5 ns */
494 #define L2CR_L2OH_1_0           0x00010000      /* L2 output hold 1.0 ns */
495 #define L2CR_L2SL               0x00008000      /* L2 DLL slow */
496 #define L2CR_L2DF               0x00004000      /* L2 differential clock */
497 #define L2CR_L2BYP              0x00002000      /* L2 DLL bypass */
498 #define L2CR_L2IP               0x00000001      /* L2 GI in progress */
499 #define L2CR_L2IO_745x          0x00100000      /* L2 instr. only (745x) */
500 #define L2CR_L2DO_745x          0x00010000      /* L2 data only (745x) */
501 #define L2CR_L2REP_745x         0x00001000      /* L2 repl. algorithm (745x) */
502 #define L2CR_L2HWF_745x         0x00000800      /* L2 hardware flush (745x) */
503 #define SPRN_L3CR               0x3FA   /* Level 3 Cache Control Regsiter */
504 #define L3CR_L3E                0x80000000      /* L3 enable */
505 #define L3CR_L3PE               0x40000000      /* L3 data parity enable */
506 #define L3CR_L3APE              0x20000000      /* L3 addr parity enable */
507 #define L3CR_L3SIZ              0x10000000      /* L3 size */
508 #define L3CR_L3CLKEN            0x08000000      /* L3 clock enable */
509 #define L3CR_L3RES              0x04000000      /* L3 special reserved bit */
510 #define L3CR_L3CLKDIV           0x03800000      /* L3 clock divisor */
511 #define L3CR_L3IO               0x00400000      /* L3 instruction only */
512 #define L3CR_L3SPO              0x00040000      /* L3 sample point override */
513 #define L3CR_L3CKSP             0x00030000      /* L3 clock sample point */
514 #define L3CR_L3PSP              0x0000e000      /* L3 P-clock sample point */
515 #define L3CR_L3REP              0x00001000      /* L3 replacement algorithm */
516 #define L3CR_L3HWF              0x00000800      /* L3 hardware flush */
517 #define L3CR_L3I                0x00000400      /* L3 global invalidate */
518 #define L3CR_L3RT               0x00000300      /* L3 SRAM type */
519 #define L3CR_L3NIRCA            0x00000080      /* L3 non-integer ratio clock adj. */
520 #define L3CR_L3DO               0x00000040      /* L3 data only mode */
521 #define L3CR_PMEN               0x00000004      /* L3 private memory enable */
522 #define L3CR_PMSIZ              0x00000001      /* L3 private memory size */
523 
524 #define SPRN_MSSCR0     0x3f6   /* Memory Subsystem Control Register 0 */
525 #define SPRN_MSSSR0     0x3f7   /* Memory Subsystem Status Register 1 */
526 #define SPRN_LDSTCR     0x3f8   /* Load/Store control register */
527 #define SPRN_LDSTDB     0x3f4   /* */
528 #define SPRN_LR         0x008   /* Link Register */
529 #ifndef SPRN_PIR
530 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
531 #endif
532 #define SPRN_TIR        0x1BE   /* Thread Identification Register */
533 #define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
534 #define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load) */
535 #define SPRN_PURR       0x135   /* Processor Utilization of Resources Reg */
536 #define SPRN_PVR        0x11F   /* Processor Version Register */
537 #define SPRN_RPA        0x3D6   /* Required Physical Address Register */
538 #define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
539 #define SPRN_SDR1       0x019   /* MMU Hash Base Register */
540 #define SPRN_ASR        0x118   /* Address Space Register */
541 #define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
542 #define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
543 #define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
544 #define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
545 #define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
546 #define SPRN_USPRG3     0x103   /* SPRG3 userspace read */
547 #define SPRN_SPRG4      0x114   /* Special Purpose Register General 4 */
548 #define SPRN_SPRG5      0x115   /* Special Purpose Register General 5 */
549 #define SPRN_SPRG6      0x116   /* Special Purpose Register General 6 */
550 #define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 */
551 #define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
552 #define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
553 #define   SRR1_ISI_NOPT         0x40000000 /* ISI: Not found in hash */
554 #define   SRR1_ISI_N_OR_G       0x10000000 /* ISI: Access is no-exec or G */
555 #define   SRR1_ISI_PROT         0x08000000 /* ISI: Other protection fault */
556 #define   SRR1_WAKEMASK         0x00380000 /* reason for wakeup */
557 #define   SRR1_WAKESYSERR       0x00300000 /* System error */
558 #define   SRR1_WAKEEE           0x00200000 /* External interrupt */
559 #define   SRR1_WAKEMT           0x00280000 /* mtctrl */
560 #define   SRR1_WAKEHMI          0x00280000 /* Hypervisor maintenance */
561 #define   SRR1_WAKEDEC          0x00180000 /* Decrementer interrupt */
562 #define   SRR1_WAKETHERM        0x00100000 /* Thermal management interrupt */
563 #define   SRR1_WAKERESET        0x00100000 /* System reset */
564 #define   SRR1_WAKESTATE        0x00030000 /* Powersave exit mask [46:47] */
565 #define   SRR1_WS_DEEPEST       0x00030000 /* Some resources not maintained,
566                                           * may not be recoverable */
567 #define   SRR1_WS_DEEPER        0x00020000 /* Some resources not maintained */
568 #define   SRR1_WS_DEEP          0x00010000 /* All resources maintained */
569 #define   SRR1_PROGFPE          0x00100000 /* Floating Point Enabled */
570 #define   SRR1_PROGILL          0x00080000 /* Illegal instruction */
571 #define   SRR1_PROGPRIV         0x00040000 /* Privileged instruction */
572 #define   SRR1_PROGTRAP         0x00020000 /* Trap */
573 #define   SRR1_PROGADDR         0x00010000 /* SRR0 contains subsequent addr */
574 
575 #define SPRN_HSRR0      0x13A   /* Save/Restore Register 0 */
576 #define SPRN_HSRR1      0x13B   /* Save/Restore Register 1 */
577 #define   HSRR1_DENORM          0x00100000 /* Denorm exception */
578 
579 #define SPRN_TBCTL      0x35f   /* PA6T Timebase control register */
580 #define   TBCTL_FREEZE          0x0000000000000000ull /* Freeze all tbs */
581 #define   TBCTL_RESTART         0x0000000100000000ull /* Restart all tbs */
582 #define   TBCTL_UPDATE_UPPER    0x0000000200000000ull /* Set upper 32 bits */
583 #define   TBCTL_UPDATE_LOWER    0x0000000300000000ull /* Set lower 32 bits */
584 
585 #ifndef SPRN_SVR
586 #define SPRN_SVR        0x11E   /* System Version Register */
587 #endif
588 #define SPRN_THRM1      0x3FC           /* Thermal Management Register 1 */
589 /* these bits were defined in inverted endian sense originally, ugh, confusing */
590 #define THRM1_TIN       (1 << 31)
591 #define THRM1_TIV       (1 << 30)
592 #define THRM1_THRES(x)  ((x&0x7f)<<23)
593 #define THRM3_SITV(x)   ((x&0x3fff)<<1)
594 #define THRM1_TID       (1<<2)
595 #define THRM1_TIE       (1<<1)
596 #define THRM1_V         (1<<0)
597 #define SPRN_THRM2      0x3FD           /* Thermal Management Register 2 */
598 #define SPRN_THRM3      0x3FE           /* Thermal Management Register 3 */
599 #define THRM3_E         (1<<0)
600 #define SPRN_TLBMISS    0x3D4           /* 980 7450 TLB Miss Register */
601 #define SPRN_UMMCR0     0x3A8   /* User Monitor Mode Control Register 0 */
602 #define SPRN_UMMCR1     0x3AC   /* User Monitor Mode Control Register 0 */
603 #define SPRN_UPMC1      0x3A9   /* User Performance Counter Register 1 */
604 #define SPRN_UPMC2      0x3AA   /* User Performance Counter Register 2 */
605 #define SPRN_UPMC3      0x3AD   /* User Performance Counter Register 3 */
606 #define SPRN_UPMC4      0x3AE   /* User Performance Counter Register 4 */
607 #define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
608 #define SPRN_VRSAVE     0x100   /* Vector Register Save Register */
609 #define SPRN_XER        0x001   /* Fixed Point Exception Register */
610 
611 #define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
612 #define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
613 #define SPRN_PMC1_GEKKO  0x3B9 /* Gekko Performance Monitor Control 1 */
614 #define SPRN_PMC2_GEKKO  0x3BA /* Gekko Performance Monitor Control 2 */
615 #define SPRN_PMC3_GEKKO  0x3BD /* Gekko Performance Monitor Control 3 */
616 #define SPRN_PMC4_GEKKO  0x3BE /* Gekko Performance Monitor Control 4 */
617 #define SPRN_WPAR_GEKKO  0x399 /* Gekko Write Pipe Address Register */
618 
619 #define SPRN_SCOMC      0x114   /* SCOM Access Control */
620 #define SPRN_SCOMD      0x115   /* SCOM Access DATA */
621 
622 /* Performance monitor SPRs */
623 #ifdef CONFIG_PPC64
624 #define SPRN_MMCR0      795
625 #define   MMCR0_FC      0x80000000UL /* freeze counters */
626 #define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
627 #define   MMCR0_KERNEL_DISABLE MMCR0_FCS
628 #define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
629 #define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
630 #define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
631 #define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
632 #define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
633 #define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
634 #define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
635 #define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
636 #define   MMCR0_PMCjCE  0x00004000UL /* PMCj count enable*/
637 #define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
638 #define   MMCR0_PMAO    0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
639 #define   MMCR0_SHRFC   0x00000040UL /* SHRre freeze conditions between threads */
640 #define   MMCR0_FC56    0x00000010UL /* freeze counters 5 and 6 */
641 #define   MMCR0_FCTI    0x00000008UL /* freeze counters in tags inactive mode */
642 #define   MMCR0_FCTA    0x00000004UL /* freeze counters in tags active mode */
643 #define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
644 #define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
645 #define SPRN_MMCR1      798
646 #define SPRN_MMCR2      785
647 #define SPRN_MMCRA      0x312
648 #define   MMCRA_SDSYNC  0x80000000UL /* SDAR synced with SIAR */
649 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
650 #define   MMCRA_SDAR_ERAT_MISS   0x20000000UL
651 #define   MMCRA_SIHV    0x10000000UL /* state of MSR HV when SIAR set */
652 #define   MMCRA_SIPR    0x08000000UL /* state of MSR PR when SIAR set */
653 #define   MMCRA_SLOT    0x07000000UL /* SLOT bits (37-39) */
654 #define   MMCRA_SLOT_SHIFT      24
655 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
656 #define   POWER6_MMCRA_SDSYNC 0x0000080000000000ULL     /* SDAR/SIAR synced */
657 #define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
658 #define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
659 #define   POWER6_MMCRA_THRM     0x00000020UL
660 #define   POWER6_MMCRA_OTHER    0x0000000EUL
661 
662 #define   POWER7P_MMCRA_SIAR_VALID 0x10000000   /* P7+ SIAR contents valid */
663 #define   POWER7P_MMCRA_SDAR_VALID 0x08000000   /* P7+ SDAR contents valid */
664 
665 #define SPRN_MMCRH      316     /* Hypervisor monitor mode control register */
666 #define SPRN_MMCRS      894     /* Supervisor monitor mode control register */
667 #define SPRN_MMCRC      851     /* Core monitor mode control register */
668 #define SPRN_EBBHR      804     /* Event based branch handler register */
669 #define SPRN_EBBRR      805     /* Event based branch return register */
670 #define SPRN_BESCR      806     /* Branch event status and control register */
671 
672 #define SPRN_PMC1       787
673 #define SPRN_PMC2       788
674 #define SPRN_PMC3       789
675 #define SPRN_PMC4       790
676 #define SPRN_PMC5       791
677 #define SPRN_PMC6       792
678 #define SPRN_PMC7       793
679 #define SPRN_PMC8       794
680 #define SPRN_SIER       784
681 #define   SIER_SIPR             0x2000000       /* Sampled MSR_PR */
682 #define   SIER_SIHV             0x1000000       /* Sampled MSR_HV */
683 #define   SIER_SIAR_VALID       0x0400000       /* SIAR contents valid */
684 #define   SIER_SDAR_VALID       0x0200000       /* SDAR contents valid */
685 #define SPRN_SIAR       796
686 #define SPRN_SDAR       797
687 
688 #define SPRN_PA6T_MMCR0 795
689 #define   PA6T_MMCR0_EN0        0x0000000000000001UL
690 #define   PA6T_MMCR0_EN1        0x0000000000000002UL
691 #define   PA6T_MMCR0_EN2        0x0000000000000004UL
692 #define   PA6T_MMCR0_EN3        0x0000000000000008UL
693 #define   PA6T_MMCR0_EN4        0x0000000000000010UL
694 #define   PA6T_MMCR0_EN5        0x0000000000000020UL
695 #define   PA6T_MMCR0_SUPEN      0x0000000000000040UL
696 #define   PA6T_MMCR0_PREN       0x0000000000000080UL
697 #define   PA6T_MMCR0_HYPEN      0x0000000000000100UL
698 #define   PA6T_MMCR0_FCM0       0x0000000000000200UL
699 #define   PA6T_MMCR0_FCM1       0x0000000000000400UL
700 #define   PA6T_MMCR0_INTGEN     0x0000000000000800UL
701 #define   PA6T_MMCR0_INTEN0     0x0000000000001000UL
702 #define   PA6T_MMCR0_INTEN1     0x0000000000002000UL
703 #define   PA6T_MMCR0_INTEN2     0x0000000000004000UL
704 #define   PA6T_MMCR0_INTEN3     0x0000000000008000UL
705 #define   PA6T_MMCR0_INTEN4     0x0000000000010000UL
706 #define   PA6T_MMCR0_INTEN5     0x0000000000020000UL
707 #define   PA6T_MMCR0_DISCNT     0x0000000000040000UL
708 #define   PA6T_MMCR0_UOP        0x0000000000080000UL
709 #define   PA6T_MMCR0_TRG        0x0000000000100000UL
710 #define   PA6T_MMCR0_TRGEN      0x0000000000200000UL
711 #define   PA6T_MMCR0_TRGREG     0x0000000001600000UL
712 #define   PA6T_MMCR0_SIARLOG    0x0000000002000000UL
713 #define   PA6T_MMCR0_SDARLOG    0x0000000004000000UL
714 #define   PA6T_MMCR0_PROEN      0x0000000008000000UL
715 #define   PA6T_MMCR0_PROLOG     0x0000000010000000UL
716 #define   PA6T_MMCR0_DAMEN2     0x0000000020000000UL
717 #define   PA6T_MMCR0_DAMEN3     0x0000000040000000UL
718 #define   PA6T_MMCR0_DAMEN4     0x0000000080000000UL
719 #define   PA6T_MMCR0_DAMEN5     0x0000000100000000UL
720 #define   PA6T_MMCR0_DAMSEL2    0x0000000200000000UL
721 #define   PA6T_MMCR0_DAMSEL3    0x0000000400000000UL
722 #define   PA6T_MMCR0_DAMSEL4    0x0000000800000000UL
723 #define   PA6T_MMCR0_DAMSEL5    0x0000001000000000UL
724 #define   PA6T_MMCR0_HANDDIS    0x0000002000000000UL
725 #define   PA6T_MMCR0_PCTEN      0x0000004000000000UL
726 #define   PA6T_MMCR0_SOCEN      0x0000008000000000UL
727 #define   PA6T_MMCR0_SOCMOD     0x0000010000000000UL
728 
729 #define SPRN_PA6T_MMCR1 798
730 #define   PA6T_MMCR1_ES2        0x00000000000000ffUL
731 #define   PA6T_MMCR1_ES3        0x000000000000ff00UL
732 #define   PA6T_MMCR1_ES4        0x0000000000ff0000UL
733 #define   PA6T_MMCR1_ES5        0x00000000ff000000UL
734 
735 #define SPRN_PA6T_UPMC0 771     /* User PerfMon Counter 0 */
736 #define SPRN_PA6T_UPMC1 772     /* ... */
737 #define SPRN_PA6T_UPMC2 773
738 #define SPRN_PA6T_UPMC3 774
739 #define SPRN_PA6T_UPMC4 775
740 #define SPRN_PA6T_UPMC5 776
741 #define SPRN_PA6T_UMMCR0 779    /* User Monitor Mode Control Register 0 */
742 #define SPRN_PA6T_SIAR  780     /* Sampled Instruction Address */
743 #define SPRN_PA6T_UMMCR1 782    /* User Monitor Mode Control Register 1 */
744 #define SPRN_PA6T_SIER  785     /* Sampled Instruction Event Register */
745 #define SPRN_PA6T_PMC0  787
746 #define SPRN_PA6T_PMC1  788
747 #define SPRN_PA6T_PMC2  789
748 #define SPRN_PA6T_PMC3  790
749 #define SPRN_PA6T_PMC4  791
750 #define SPRN_PA6T_PMC5  792
751 #define SPRN_PA6T_TSR0  793     /* Timestamp Register 0 */
752 #define SPRN_PA6T_TSR1  794     /* Timestamp Register 1 */
753 #define SPRN_PA6T_TSR2  799     /* Timestamp Register 2 */
754 #define SPRN_PA6T_TSR3  784     /* Timestamp Register 3 */
755 
756 #define SPRN_PA6T_IER   981     /* Icache Error Register */
757 #define SPRN_PA6T_DER   982     /* Dcache Error Register */
758 #define SPRN_PA6T_BER   862     /* BIU Error Address Register */
759 #define SPRN_PA6T_MER   849     /* MMU Error Register */
760 
761 #define SPRN_PA6T_IMA0  880     /* Instruction Match Array 0 */
762 #define SPRN_PA6T_IMA1  881     /* ... */
763 #define SPRN_PA6T_IMA2  882
764 #define SPRN_PA6T_IMA3  883
765 #define SPRN_PA6T_IMA4  884
766 #define SPRN_PA6T_IMA5  885
767 #define SPRN_PA6T_IMA6  886
768 #define SPRN_PA6T_IMA7  887
769 #define SPRN_PA6T_IMA8  888
770 #define SPRN_PA6T_IMA9  889
771 #define SPRN_PA6T_BTCR  978     /* Breakpoint and Tagging Control Register */
772 #define SPRN_PA6T_IMAAT 979     /* Instruction Match Array Action Table */
773 #define SPRN_PA6T_PCCR  1019    /* Power Counter Control Register */
774 #define SPRN_BKMK       1020    /* Cell Bookmark Register */
775 #define SPRN_PA6T_RPCCR 1021    /* Retire PC Trace Control Register */
776 
777 
778 #else /* 32-bit */
779 #define SPRN_MMCR0      952     /* Monitor Mode Control Register 0 */
780 #define   MMCR0_FC      0x80000000UL /* freeze counters */
781 #define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
782 #define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
783 #define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
784 #define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
785 #define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
786 #define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
787 #define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
788 #define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
789 #define   MMCR0_PMCnCE  0x00004000UL /* count enable for all but PMC 1*/
790 #define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
791 #define   MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
792 #define   MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
793 
794 #define SPRN_MMCR1      956
795 #define   MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
796 #define   MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
797 #define   MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
798 #define   MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
799 #define SPRN_MMCR2      944
800 #define SPRN_PMC1       953     /* Performance Counter Register 1 */
801 #define SPRN_PMC2       954     /* Performance Counter Register 2 */
802 #define SPRN_PMC3       957     /* Performance Counter Register 3 */
803 #define SPRN_PMC4       958     /* Performance Counter Register 4 */
804 #define SPRN_PMC5       945     /* Performance Counter Register 5 */
805 #define SPRN_PMC6       946     /* Performance Counter Register 6 */
806 
807 #define SPRN_SIAR       955     /* Sampled Instruction Address Register */
808 
809 /* Bit definitions for MMCR0 and PMC1 / PMC2. */
810 #define MMCR0_PMC1_CYCLES       (1 << 7)
811 #define MMCR0_PMC1_ICACHEMISS   (5 << 7)
812 #define MMCR0_PMC1_DTLB         (6 << 7)
813 #define MMCR0_PMC2_DCACHEMISS   0x6
814 #define MMCR0_PMC2_CYCLES       0x1
815 #define MMCR0_PMC2_ITLB         0x7
816 #define MMCR0_PMC2_LOADMISSTIME 0x5
817 #endif
818 
819 /*
820  * SPRG usage:
821  *
822  * All 64-bit:
823  *      - SPRG1 stores PACA pointer except 64-bit server in
824  *        HV mode in which case it is HSPRG0
825  *
826  * 64-bit server:
827  *      - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
828  *      - SPRG2 scratch for exception vectors
829  *      - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
830  *      - HSPRG0 stores PACA in HV mode
831  *      - HSPRG1 scratch for "HV" exceptions
832  *
833  * 64-bit embedded
834  *      - SPRG0 generic exception scratch
835  *      - SPRG2 TLB exception stack
836  *      - SPRG3 critical exception scratch and
837  *        CPU and NUMA node for VDSO getcpu (user visible)
838  *      - SPRG4 unused (user visible)
839  *      - SPRG6 TLB miss scratch (user visible, sorry !)
840  *      - SPRG7 critical exception scratch
841  *      - SPRG8 machine check exception scratch
842  *      - SPRG9 debug exception scratch
843  *
844  * All 32-bit:
845  *      - SPRG3 current thread_info pointer
846  *        (virtual on BookE, physical on others)
847  *
848  * 32-bit classic:
849  *      - SPRG0 scratch for exception vectors
850  *      - SPRG1 scratch for exception vectors
851  *      - SPRG2 indicator that we are in RTAS
852  *      - SPRG4 (603 only) pseudo TLB LRU data
853  *
854  * 32-bit 40x:
855  *      - SPRG0 scratch for exception vectors
856  *      - SPRG1 scratch for exception vectors
857  *      - SPRG2 scratch for exception vectors
858  *      - SPRG4 scratch for exception vectors (not 403)
859  *      - SPRG5 scratch for exception vectors (not 403)
860  *      - SPRG6 scratch for exception vectors (not 403)
861  *      - SPRG7 scratch for exception vectors (not 403)
862  *
863  * 32-bit 440 and FSL BookE:
864  *      - SPRG0 scratch for exception vectors
865  *      - SPRG1 scratch for exception vectors (*)
866  *      - SPRG2 scratch for crit interrupts handler
867  *      - SPRG4 scratch for exception vectors
868  *      - SPRG5 scratch for exception vectors
869  *      - SPRG6 scratch for machine check handler
870  *      - SPRG7 scratch for exception vectors
871  *      - SPRG9 scratch for debug vectors (e500 only)
872  *
873  *      Additionally, BookE separates "read" and "write"
874  *      of those registers. That allows to use the userspace
875  *      readable variant for reads, which can avoid a fault
876  *      with KVM type virtualization.
877  *
878  *      (*) Under KVM, the host SPRG1 is used to point to
879  *      the current VCPU data structure
880  *
881  * 32-bit 8xx:
882  *      - SPRG0 scratch for exception vectors
883  *      - SPRG1 scratch for exception vectors
884  *      - SPRG2 apparently unused but initialized
885  *
886  */
887 #ifdef CONFIG_PPC64
888 #define SPRN_SPRG_PACA          SPRN_SPRG1
889 #else
890 #define SPRN_SPRG_THREAD        SPRN_SPRG3
891 #endif
892 
893 #ifdef CONFIG_PPC_BOOK3S_64
894 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG2
895 #define SPRN_SPRG_HPACA         SPRN_HSPRG0
896 #define SPRN_SPRG_HSCRATCH0     SPRN_HSPRG1
897 
898 #define GET_PACA(rX)                                    \
899         BEGIN_FTR_SECTION_NESTED(66);                   \
900         mfspr   rX,SPRN_SPRG_PACA;                      \
901         FTR_SECTION_ELSE_NESTED(66);                    \
902         mfspr   rX,SPRN_SPRG_HPACA;                     \
903         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
904 
905 #define SET_PACA(rX)                                    \
906         BEGIN_FTR_SECTION_NESTED(66);                   \
907         mtspr   SPRN_SPRG_PACA,rX;                      \
908         FTR_SECTION_ELSE_NESTED(66);                    \
909         mtspr   SPRN_SPRG_HPACA,rX;                     \
910         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
911 
912 #define GET_SCRATCH0(rX)                                \
913         BEGIN_FTR_SECTION_NESTED(66);                   \
914         mfspr   rX,SPRN_SPRG_SCRATCH0;                  \
915         FTR_SECTION_ELSE_NESTED(66);                    \
916         mfspr   rX,SPRN_SPRG_HSCRATCH0;                 \
917         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
918 
919 #define SET_SCRATCH0(rX)                                \
920         BEGIN_FTR_SECTION_NESTED(66);                   \
921         mtspr   SPRN_SPRG_SCRATCH0,rX;                  \
922         FTR_SECTION_ELSE_NESTED(66);                    \
923         mtspr   SPRN_SPRG_HSCRATCH0,rX;                 \
924         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
925 
926 #else /* CONFIG_PPC_BOOK3S_64 */
927 #define GET_SCRATCH0(rX)        mfspr   rX,SPRN_SPRG_SCRATCH0
928 #define SET_SCRATCH0(rX)        mtspr   SPRN_SPRG_SCRATCH0,rX
929 
930 #endif
931 
932 #ifdef CONFIG_PPC_BOOK3E_64
933 #define SPRN_SPRG_MC_SCRATCH    SPRN_SPRG8
934 #define SPRN_SPRG_CRIT_SCRATCH  SPRN_SPRG3
935 #define SPRN_SPRG_DBG_SCRATCH   SPRN_SPRG9
936 #define SPRN_SPRG_TLB_EXFRAME   SPRN_SPRG2
937 #define SPRN_SPRG_TLB_SCRATCH   SPRN_SPRG6
938 #define SPRN_SPRG_GEN_SCRATCH   SPRN_SPRG0
939 #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
940 
941 #define SET_PACA(rX)    mtspr   SPRN_SPRG_PACA,rX
942 #define GET_PACA(rX)    mfspr   rX,SPRN_SPRG_PACA
943 
944 #endif
945 
946 #ifdef CONFIG_PPC_BOOK3S_32
947 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
948 #define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
949 #define SPRN_SPRG_RTAS          SPRN_SPRG2
950 #define SPRN_SPRG_603_LRU       SPRN_SPRG4
951 #endif
952 
953 #ifdef CONFIG_40x
954 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
955 #define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
956 #define SPRN_SPRG_SCRATCH2      SPRN_SPRG2
957 #define SPRN_SPRG_SCRATCH3      SPRN_SPRG4
958 #define SPRN_SPRG_SCRATCH4      SPRN_SPRG5
959 #define SPRN_SPRG_SCRATCH5      SPRN_SPRG6
960 #define SPRN_SPRG_SCRATCH6      SPRN_SPRG7
961 #endif
962 
963 #ifdef CONFIG_BOOKE
964 #define SPRN_SPRG_RSCRATCH0     SPRN_SPRG0
965 #define SPRN_SPRG_WSCRATCH0     SPRN_SPRG0
966 #define SPRN_SPRG_RSCRATCH1     SPRN_SPRG1
967 #define SPRN_SPRG_WSCRATCH1     SPRN_SPRG1
968 #define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
969 #define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
970 #define SPRN_SPRG_RSCRATCH2     SPRN_SPRG4R
971 #define SPRN_SPRG_WSCRATCH2     SPRN_SPRG4W
972 #define SPRN_SPRG_RSCRATCH3     SPRN_SPRG5R
973 #define SPRN_SPRG_WSCRATCH3     SPRN_SPRG5W
974 #define SPRN_SPRG_RSCRATCH_MC   SPRN_SPRG1
975 #define SPRN_SPRG_WSCRATCH_MC   SPRN_SPRG1
976 #define SPRN_SPRG_RSCRATCH4     SPRN_SPRG7R
977 #define SPRN_SPRG_WSCRATCH4     SPRN_SPRG7W
978 #ifdef CONFIG_E200
979 #define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG6R
980 #define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG6W
981 #else
982 #define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG9
983 #define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG9
984 #endif
985 #endif
986 
987 #ifdef CONFIG_8xx
988 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
989 #define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
990 #endif
991 
992 
993 
994 /*
995  * An mtfsf instruction with the L bit set. On CPUs that support this a
996  * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
997  *
998  * Until binutils gets the new form of mtfsf, hardwire the instruction.
999  */
1000 #ifdef CONFIG_PPC64
1001 #define MTFSF_L(REG) \
1002         .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1003 #else
1004 #define MTFSF_L(REG)    mtfsf   0xff, (REG)
1005 #endif
1006 
1007 /* Processor Version Register (PVR) field extraction */
1008 
1009 #define PVR_VER(pvr)    (((pvr) >>  16) & 0xFFFF)       /* Version field */
1010 #define PVR_REV(pvr)    (((pvr) >>   0) & 0xFFFF)       /* Revison field */
1011 
1012 #define pvr_version_is(pvr)     (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1013 
1014 /*
1015  * IBM has further subdivided the standard PowerPC 16-bit version and
1016  * revision subfields of the PVR for the PowerPC 403s into the following:
1017  */
1018 
1019 #define PVR_FAM(pvr)    (((pvr) >> 20) & 0xFFF) /* Family field */
1020 #define PVR_MEM(pvr)    (((pvr) >> 16) & 0xF)   /* Member field */
1021 #define PVR_CORE(pvr)   (((pvr) >> 12) & 0xF)   /* Core field */
1022 #define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
1023 #define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
1024 #define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
1025 
1026 /* Processor Version Numbers */
1027 
1028 #define PVR_403GA       0x00200000
1029 #define PVR_403GB       0x00200100
1030 #define PVR_403GC       0x00200200
1031 #define PVR_403GCX      0x00201400
1032 #define PVR_405GP       0x40110000
1033 #define PVR_476         0x11a52000
1034 #define PVR_476FPE      0x7ff50000
1035 #define PVR_STB03XXX    0x40310000
1036 #define PVR_NP405H      0x41410000
1037 #define PVR_NP405L      0x41610000
1038 #define PVR_601         0x00010000
1039 #define PVR_602         0x00050000
1040 #define PVR_603         0x00030000
1041 #define PVR_603e        0x00060000
1042 #define PVR_603ev       0x00070000
1043 #define PVR_603r        0x00071000
1044 #define PVR_604         0x00040000
1045 #define PVR_604e        0x00090000
1046 #define PVR_604r        0x000A0000
1047 #define PVR_620         0x00140000
1048 #define PVR_740         0x00080000
1049 #define PVR_750         PVR_740
1050 #define PVR_740P        0x10080000
1051 #define PVR_750P        PVR_740P
1052 #define PVR_7400        0x000C0000
1053 #define PVR_7410        0x800C0000
1054 #define PVR_7450        0x80000000
1055 #define PVR_8540        0x80200000
1056 #define PVR_8560        0x80200000
1057 #define PVR_VER_E500V1  0x8020
1058 #define PVR_VER_E500V2  0x8021
1059 /*
1060  * For the 8xx processors, all of them report the same PVR family for
1061  * the PowerPC core. The various versions of these processors must be
1062  * differentiated by the version number in the Communication Processor
1063  * Module (CPM).
1064  */
1065 #define PVR_821         0x00500000
1066 #define PVR_823         PVR_821
1067 #define PVR_850         PVR_821
1068 #define PVR_860         PVR_821
1069 #define PVR_8240        0x00810100
1070 #define PVR_8245        0x80811014
1071 #define PVR_8260        PVR_8240
1072 
1073 /* 476 Simulator seems to currently have the PVR of the 602... */
1074 #define PVR_476_ISS     0x00052000
1075 
1076 /* 64-bit processors */
1077 #define PVR_NORTHSTAR   0x0033
1078 #define PVR_PULSAR      0x0034
1079 #define PVR_POWER4      0x0035
1080 #define PVR_ICESTAR     0x0036
1081 #define PVR_SSTAR       0x0037
1082 #define PVR_POWER4p     0x0038
1083 #define PVR_970         0x0039
1084 #define PVR_POWER5      0x003A
1085 #define PVR_POWER5p     0x003B
1086 #define PVR_970FX       0x003C
1087 #define PVR_POWER6      0x003E
1088 #define PVR_POWER7      0x003F
1089 #define PVR_630         0x0040
1090 #define PVR_630p        0x0041
1091 #define PVR_970MP       0x0044
1092 #define PVR_970GX       0x0045
1093 #define PVR_POWER7p     0x004A
1094 #define PVR_POWER8      0x004B
1095 #define PVR_BE          0x0070
1096 #define PVR_PA6T        0x0090
1097 
1098 /* Macros for setting and retrieving special purpose registers */
1099 #ifndef __ASSEMBLY__
1100 #define mfmsr()         ({unsigned long rval; \
1101                         asm volatile("mfmsr %0" : "=r" (rval) : \
1102                                                 : "memory"); rval;})
1103 #ifdef CONFIG_PPC_BOOK3S_64
1104 #define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
1105                                      : : "r" (v) : "memory")
1106 #define mtmsrd(v)       __mtmsrd((v), 0)
1107 #define mtmsr(v)        mtmsrd(v)
1108 #else
1109 #define mtmsr(v)        asm volatile("mtmsr %0" : \
1110                                      : "r" ((unsigned long)(v)) \
1111                                      : "memory")
1112 #endif
1113 
1114 #define mfspr(rn)       ({unsigned long rval; \
1115                         asm volatile("mfspr %0," __stringify(rn) \
1116                                 : "=r" (rval)); rval;})
1117 #define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : \
1118                                      : "r" ((unsigned long)(v)) \
1119                                      : "memory")
1120 
1121 #ifdef __powerpc64__
1122 #ifdef CONFIG_PPC_CELL
1123 #define mftb()          ({unsigned long rval;                           \
1124                         asm volatile(                                   \
1125                                 "90:    mftb %0;\n"                     \
1126                                 "97:    cmpwi %0,0;\n"                  \
1127                                 "       beq- 90b;\n"                    \
1128                                 "99:\n"                                 \
1129                                 ".section __ftr_fixup,\"a\"\n"          \
1130                                 ".align 3\n"                            \
1131                                 "98:\n"                                 \
1132                                 "       .llong %1\n"                    \
1133                                 "       .llong %1\n"                    \
1134                                 "       .llong 97b-98b\n"               \
1135                                 "       .llong 99b-98b\n"               \
1136                                 "       .llong 0\n"                     \
1137                                 "       .llong 0\n"                     \
1138                                 ".previous"                             \
1139                         : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG) : "cr0"); rval;})
1140 #else
1141 #define mftb()          ({unsigned long rval;   \
1142                         asm volatile("mftb %0" : "=r" (rval)); rval;})
1143 #endif /* !CONFIG_PPC_CELL */
1144 
1145 #else /* __powerpc64__ */
1146 
1147 #define mftbl()         ({unsigned long rval;   \
1148                         asm volatile("mftbl %0" : "=r" (rval)); rval;})
1149 #define mftbu()         ({unsigned long rval;   \
1150                         asm volatile("mftbu %0" : "=r" (rval)); rval;})
1151 #endif /* !__powerpc64__ */
1152 
1153 #define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
1154 #define mttbu(v)        asm volatile("mttbu %0":: "r"(v))
1155 
1156 #ifdef CONFIG_PPC32
1157 #define mfsrin(v)       ({unsigned int rval; \
1158                         asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1159                                         rval;})
1160 #endif
1161 
1162 #define proc_trap()     asm volatile("trap")
1163 
1164 #define __get_SP()      ({unsigned long sp; \
1165                         asm volatile("mr %0,1": "=r" (sp)); sp;})
1166 
1167 extern unsigned long scom970_read(unsigned int address);
1168 extern void scom970_write(unsigned int address, unsigned long value);
1169 
1170 struct pt_regs;
1171 
1172 extern void ppc_save_regs(struct pt_regs *regs);
1173 
1174 #endif /* __ASSEMBLY__ */
1175 #endif /* __KERNEL__ */
1176 #endif /* _ASM_POWERPC_REG_H */
1177 

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