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Linux/arch/powerpc/kernel/pci-common.c

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  1 /*
  2  * Contains common pci routines for ALL ppc platform
  3  * (based on pci_32.c and pci_64.c)
  4  *
  5  * Port for PPC64 David Engebretsen, IBM Corp.
  6  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
  7  *
  8  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  9  *   Rework, based on alpha PCI code.
 10  *
 11  * Common pmac/prep/chrp pci routines. -- Cort
 12  *
 13  * This program is free software; you can redistribute it and/or
 14  * modify it under the terms of the GNU General Public License
 15  * as published by the Free Software Foundation; either version
 16  * 2 of the License, or (at your option) any later version.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/pci.h>
 21 #include <linux/string.h>
 22 #include <linux/init.h>
 23 #include <linux/delay.h>
 24 #include <linux/export.h>
 25 #include <linux/of_address.h>
 26 #include <linux/of_pci.h>
 27 #include <linux/mm.h>
 28 #include <linux/list.h>
 29 #include <linux/syscalls.h>
 30 #include <linux/irq.h>
 31 #include <linux/vmalloc.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 
 35 #include <asm/processor.h>
 36 #include <asm/io.h>
 37 #include <asm/prom.h>
 38 #include <asm/pci-bridge.h>
 39 #include <asm/byteorder.h>
 40 #include <asm/machdep.h>
 41 #include <asm/ppc-pci.h>
 42 #include <asm/eeh.h>
 43 
 44 static DEFINE_SPINLOCK(hose_spinlock);
 45 LIST_HEAD(hose_list);
 46 
 47 /* XXX kill that some day ... */
 48 static int global_phb_number;           /* Global phb counter */
 49 
 50 /* ISA Memory physical address */
 51 resource_size_t isa_mem_base;
 52 
 53 
 54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 55 
 56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
 57 {
 58         pci_dma_ops = dma_ops;
 59 }
 60 
 61 struct dma_map_ops *get_pci_dma_ops(void)
 62 {
 63         return pci_dma_ops;
 64 }
 65 EXPORT_SYMBOL(get_pci_dma_ops);
 66 
 67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
 68 {
 69         struct pci_controller *phb;
 70 
 71         phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
 72         if (phb == NULL)
 73                 return NULL;
 74         spin_lock(&hose_spinlock);
 75         phb->global_number = global_phb_number++;
 76         list_add_tail(&phb->list_node, &hose_list);
 77         spin_unlock(&hose_spinlock);
 78         phb->dn = dev;
 79         phb->is_dynamic = slab_is_available();
 80 #ifdef CONFIG_PPC64
 81         if (dev) {
 82                 int nid = of_node_to_nid(dev);
 83 
 84                 if (nid < 0 || !node_online(nid))
 85                         nid = -1;
 86 
 87                 PHB_SET_NODE(phb, nid);
 88         }
 89 #endif
 90         return phb;
 91 }
 92 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
 93 
 94 void pcibios_free_controller(struct pci_controller *phb)
 95 {
 96         spin_lock(&hose_spinlock);
 97         list_del(&phb->list_node);
 98         spin_unlock(&hose_spinlock);
 99 
100         if (phb->is_dynamic)
101                 kfree(phb);
102 }
103 EXPORT_SYMBOL_GPL(pcibios_free_controller);
104 
105 /*
106  * This function is used to call pcibios_free_controller()
107  * in a deferred manner: a callback from the PCI subsystem.
108  *
109  * _*DO NOT*_ call pcibios_free_controller() explicitly if
110  * this is used (or it may access an invalid *phb pointer).
111  *
112  * The callback occurs when all references to the root bus
113  * are dropped (e.g., child buses/devices and their users).
114  *
115  * It's called as .release_fn() of 'struct pci_host_bridge'
116  * which is associated with the 'struct pci_controller.bus'
117  * (root bus) - it expects .release_data to hold a pointer
118  * to 'struct pci_controller'.
119  *
120  * In order to use it, register .release_fn()/release_data
121  * like this:
122  *
123  * pci_set_host_bridge_release(bridge,
124  *                             pcibios_free_controller_deferred
125  *                             (void *) phb);
126  *
127  * e.g. in the pcibios_root_bridge_prepare() callback from
128  * pci_create_root_bus().
129  */
130 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
131 {
132         struct pci_controller *phb = (struct pci_controller *)
133                                          bridge->release_data;
134 
135         pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
136 
137         pcibios_free_controller(phb);
138 }
139 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
140 
141 /*
142  * The function is used to return the minimal alignment
143  * for memory or I/O windows of the associated P2P bridge.
144  * By default, 4KiB alignment for I/O windows and 1MiB for
145  * memory windows.
146  */
147 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
148                                          unsigned long type)
149 {
150         struct pci_controller *phb = pci_bus_to_host(bus);
151 
152         if (phb->controller_ops.window_alignment)
153                 return phb->controller_ops.window_alignment(bus, type);
154 
155         /*
156          * PCI core will figure out the default
157          * alignment: 4KiB for I/O and 1MiB for
158          * memory window.
159          */
160         return 1;
161 }
162 
163 void pcibios_reset_secondary_bus(struct pci_dev *dev)
164 {
165         struct pci_controller *phb = pci_bus_to_host(dev->bus);
166 
167         if (phb->controller_ops.reset_secondary_bus) {
168                 phb->controller_ops.reset_secondary_bus(dev);
169                 return;
170         }
171 
172         pci_reset_secondary_bus(dev);
173 }
174 
175 #ifdef CONFIG_PCI_IOV
176 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
177 {
178         if (ppc_md.pcibios_iov_resource_alignment)
179                 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
180 
181         return pci_iov_resource_size(pdev, resno);
182 }
183 #endif /* CONFIG_PCI_IOV */
184 
185 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
186 {
187 #ifdef CONFIG_PPC64
188         return hose->pci_io_size;
189 #else
190         return resource_size(&hose->io_resource);
191 #endif
192 }
193 
194 int pcibios_vaddr_is_ioport(void __iomem *address)
195 {
196         int ret = 0;
197         struct pci_controller *hose;
198         resource_size_t size;
199 
200         spin_lock(&hose_spinlock);
201         list_for_each_entry(hose, &hose_list, list_node) {
202                 size = pcibios_io_size(hose);
203                 if (address >= hose->io_base_virt &&
204                     address < (hose->io_base_virt + size)) {
205                         ret = 1;
206                         break;
207                 }
208         }
209         spin_unlock(&hose_spinlock);
210         return ret;
211 }
212 
213 unsigned long pci_address_to_pio(phys_addr_t address)
214 {
215         struct pci_controller *hose;
216         resource_size_t size;
217         unsigned long ret = ~0;
218 
219         spin_lock(&hose_spinlock);
220         list_for_each_entry(hose, &hose_list, list_node) {
221                 size = pcibios_io_size(hose);
222                 if (address >= hose->io_base_phys &&
223                     address < (hose->io_base_phys + size)) {
224                         unsigned long base =
225                                 (unsigned long)hose->io_base_virt - _IO_BASE;
226                         ret = base + (address - hose->io_base_phys);
227                         break;
228                 }
229         }
230         spin_unlock(&hose_spinlock);
231 
232         return ret;
233 }
234 EXPORT_SYMBOL_GPL(pci_address_to_pio);
235 
236 /*
237  * Return the domain number for this bus.
238  */
239 int pci_domain_nr(struct pci_bus *bus)
240 {
241         struct pci_controller *hose = pci_bus_to_host(bus);
242 
243         return hose->global_number;
244 }
245 EXPORT_SYMBOL(pci_domain_nr);
246 
247 /* This routine is meant to be used early during boot, when the
248  * PCI bus numbers have not yet been assigned, and you need to
249  * issue PCI config cycles to an OF device.
250  * It could also be used to "fix" RTAS config cycles if you want
251  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
252  * config cycles.
253  */
254 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
255 {
256         while(node) {
257                 struct pci_controller *hose, *tmp;
258                 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
259                         if (hose->dn == node)
260                                 return hose;
261                 node = node->parent;
262         }
263         return NULL;
264 }
265 
266 /*
267  * Reads the interrupt pin to determine if interrupt is use by card.
268  * If the interrupt is used, then gets the interrupt line from the
269  * openfirmware and sets it in the pci_dev and pci_config line.
270  */
271 static int pci_read_irq_line(struct pci_dev *pci_dev)
272 {
273         struct of_phandle_args oirq;
274         unsigned int virq;
275 
276         pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
277 
278 #ifdef DEBUG
279         memset(&oirq, 0xff, sizeof(oirq));
280 #endif
281         /* Try to get a mapping from the device-tree */
282         if (of_irq_parse_pci(pci_dev, &oirq)) {
283                 u8 line, pin;
284 
285                 /* If that fails, lets fallback to what is in the config
286                  * space and map that through the default controller. We
287                  * also set the type to level low since that's what PCI
288                  * interrupts are. If your platform does differently, then
289                  * either provide a proper interrupt tree or don't use this
290                  * function.
291                  */
292                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
293                         return -1;
294                 if (pin == 0)
295                         return -1;
296                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
297                     line == 0xff || line == 0) {
298                         return -1;
299                 }
300                 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
301                          line, pin);
302 
303                 virq = irq_create_mapping(NULL, line);
304                 if (virq != NO_IRQ)
305                         irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
306         } else {
307                 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
308                          oirq.args_count, oirq.args[0], oirq.args[1],
309                          of_node_full_name(oirq.np));
310 
311                 virq = irq_create_of_mapping(&oirq);
312         }
313         if(virq == NO_IRQ) {
314                 pr_debug(" Failed to map !\n");
315                 return -1;
316         }
317 
318         pr_debug(" Mapped to linux irq %d\n", virq);
319 
320         pci_dev->irq = virq;
321 
322         return 0;
323 }
324 
325 /*
326  * Platform support for /proc/bus/pci/X/Y mmap()s,
327  * modelled on the sparc64 implementation by Dave Miller.
328  *  -- paulus.
329  */
330 
331 /*
332  * Adjust vm_pgoff of VMA such that it is the physical page offset
333  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
334  *
335  * Basically, the user finds the base address for his device which he wishes
336  * to mmap.  They read the 32-bit value from the config space base register,
337  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
338  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
339  *
340  * Returns negative error code on failure, zero on success.
341  */
342 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
343                                                resource_size_t *offset,
344                                                enum pci_mmap_state mmap_state)
345 {
346         struct pci_controller *hose = pci_bus_to_host(dev->bus);
347         unsigned long io_offset = 0;
348         int i, res_bit;
349 
350         if (hose == NULL)
351                 return NULL;            /* should never happen */
352 
353         /* If memory, add on the PCI bridge address offset */
354         if (mmap_state == pci_mmap_mem) {
355 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
356                 *offset += hose->pci_mem_offset;
357 #endif
358                 res_bit = IORESOURCE_MEM;
359         } else {
360                 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
361                 *offset += io_offset;
362                 res_bit = IORESOURCE_IO;
363         }
364 
365         /*
366          * Check that the offset requested corresponds to one of the
367          * resources of the device.
368          */
369         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
370                 struct resource *rp = &dev->resource[i];
371                 int flags = rp->flags;
372 
373                 /* treat ROM as memory (should be already) */
374                 if (i == PCI_ROM_RESOURCE)
375                         flags |= IORESOURCE_MEM;
376 
377                 /* Active and same type? */
378                 if ((flags & res_bit) == 0)
379                         continue;
380 
381                 /* In the range of this resource? */
382                 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
383                         continue;
384 
385                 /* found it! construct the final physical address */
386                 if (mmap_state == pci_mmap_io)
387                         *offset += hose->io_base_phys - io_offset;
388                 return rp;
389         }
390 
391         return NULL;
392 }
393 
394 /*
395  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
396  * device mapping.
397  */
398 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
399                                       pgprot_t protection,
400                                       enum pci_mmap_state mmap_state,
401                                       int write_combine)
402 {
403 
404         /* Write combine is always 0 on non-memory space mappings. On
405          * memory space, if the user didn't pass 1, we check for a
406          * "prefetchable" resource. This is a bit hackish, but we use
407          * this to workaround the inability of /sysfs to provide a write
408          * combine bit
409          */
410         if (mmap_state != pci_mmap_mem)
411                 write_combine = 0;
412         else if (write_combine == 0) {
413                 if (rp->flags & IORESOURCE_PREFETCH)
414                         write_combine = 1;
415         }
416 
417         /* XXX would be nice to have a way to ask for write-through */
418         if (write_combine)
419                 return pgprot_noncached_wc(protection);
420         else
421                 return pgprot_noncached(protection);
422 }
423 
424 /*
425  * This one is used by /dev/mem and fbdev who have no clue about the
426  * PCI device, it tries to find the PCI device first and calls the
427  * above routine
428  */
429 pgprot_t pci_phys_mem_access_prot(struct file *file,
430                                   unsigned long pfn,
431                                   unsigned long size,
432                                   pgprot_t prot)
433 {
434         struct pci_dev *pdev = NULL;
435         struct resource *found = NULL;
436         resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
437         int i;
438 
439         if (page_is_ram(pfn))
440                 return prot;
441 
442         prot = pgprot_noncached(prot);
443         for_each_pci_dev(pdev) {
444                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
445                         struct resource *rp = &pdev->resource[i];
446                         int flags = rp->flags;
447 
448                         /* Active and same type? */
449                         if ((flags & IORESOURCE_MEM) == 0)
450                                 continue;
451                         /* In the range of this resource? */
452                         if (offset < (rp->start & PAGE_MASK) ||
453                             offset > rp->end)
454                                 continue;
455                         found = rp;
456                         break;
457                 }
458                 if (found)
459                         break;
460         }
461         if (found) {
462                 if (found->flags & IORESOURCE_PREFETCH)
463                         prot = pgprot_noncached_wc(prot);
464                 pci_dev_put(pdev);
465         }
466 
467         pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
468                  (unsigned long long)offset, pgprot_val(prot));
469 
470         return prot;
471 }
472 
473 
474 /*
475  * Perform the actual remap of the pages for a PCI device mapping, as
476  * appropriate for this architecture.  The region in the process to map
477  * is described by vm_start and vm_end members of VMA, the base physical
478  * address is found in vm_pgoff.
479  * The pci device structure is provided so that architectures may make mapping
480  * decisions on a per-device or per-bus basis.
481  *
482  * Returns a negative error code on failure, zero on success.
483  */
484 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
485                         enum pci_mmap_state mmap_state, int write_combine)
486 {
487         resource_size_t offset =
488                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
489         struct resource *rp;
490         int ret;
491 
492         rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
493         if (rp == NULL)
494                 return -EINVAL;
495 
496         vma->vm_pgoff = offset >> PAGE_SHIFT;
497         vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
498                                                   vma->vm_page_prot,
499                                                   mmap_state, write_combine);
500 
501         ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
502                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
503 
504         return ret;
505 }
506 
507 /* This provides legacy IO read access on a bus */
508 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
509 {
510         unsigned long offset;
511         struct pci_controller *hose = pci_bus_to_host(bus);
512         struct resource *rp = &hose->io_resource;
513         void __iomem *addr;
514 
515         /* Check if port can be supported by that bus. We only check
516          * the ranges of the PHB though, not the bus itself as the rules
517          * for forwarding legacy cycles down bridges are not our problem
518          * here. So if the host bridge supports it, we do it.
519          */
520         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
521         offset += port;
522 
523         if (!(rp->flags & IORESOURCE_IO))
524                 return -ENXIO;
525         if (offset < rp->start || (offset + size) > rp->end)
526                 return -ENXIO;
527         addr = hose->io_base_virt + port;
528 
529         switch(size) {
530         case 1:
531                 *((u8 *)val) = in_8(addr);
532                 return 1;
533         case 2:
534                 if (port & 1)
535                         return -EINVAL;
536                 *((u16 *)val) = in_le16(addr);
537                 return 2;
538         case 4:
539                 if (port & 3)
540                         return -EINVAL;
541                 *((u32 *)val) = in_le32(addr);
542                 return 4;
543         }
544         return -EINVAL;
545 }
546 
547 /* This provides legacy IO write access on a bus */
548 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
549 {
550         unsigned long offset;
551         struct pci_controller *hose = pci_bus_to_host(bus);
552         struct resource *rp = &hose->io_resource;
553         void __iomem *addr;
554 
555         /* Check if port can be supported by that bus. We only check
556          * the ranges of the PHB though, not the bus itself as the rules
557          * for forwarding legacy cycles down bridges are not our problem
558          * here. So if the host bridge supports it, we do it.
559          */
560         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
561         offset += port;
562 
563         if (!(rp->flags & IORESOURCE_IO))
564                 return -ENXIO;
565         if (offset < rp->start || (offset + size) > rp->end)
566                 return -ENXIO;
567         addr = hose->io_base_virt + port;
568 
569         /* WARNING: The generic code is idiotic. It gets passed a pointer
570          * to what can be a 1, 2 or 4 byte quantity and always reads that
571          * as a u32, which means that we have to correct the location of
572          * the data read within those 32 bits for size 1 and 2
573          */
574         switch(size) {
575         case 1:
576                 out_8(addr, val >> 24);
577                 return 1;
578         case 2:
579                 if (port & 1)
580                         return -EINVAL;
581                 out_le16(addr, val >> 16);
582                 return 2;
583         case 4:
584                 if (port & 3)
585                         return -EINVAL;
586                 out_le32(addr, val);
587                 return 4;
588         }
589         return -EINVAL;
590 }
591 
592 /* This provides legacy IO or memory mmap access on a bus */
593 int pci_mmap_legacy_page_range(struct pci_bus *bus,
594                                struct vm_area_struct *vma,
595                                enum pci_mmap_state mmap_state)
596 {
597         struct pci_controller *hose = pci_bus_to_host(bus);
598         resource_size_t offset =
599                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
600         resource_size_t size = vma->vm_end - vma->vm_start;
601         struct resource *rp;
602 
603         pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
604                  pci_domain_nr(bus), bus->number,
605                  mmap_state == pci_mmap_mem ? "MEM" : "IO",
606                  (unsigned long long)offset,
607                  (unsigned long long)(offset + size - 1));
608 
609         if (mmap_state == pci_mmap_mem) {
610                 /* Hack alert !
611                  *
612                  * Because X is lame and can fail starting if it gets an error trying
613                  * to mmap legacy_mem (instead of just moving on without legacy memory
614                  * access) we fake it here by giving it anonymous memory, effectively
615                  * behaving just like /dev/zero
616                  */
617                 if ((offset + size) > hose->isa_mem_size) {
618                         printk(KERN_DEBUG
619                                "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
620                                current->comm, current->pid, pci_domain_nr(bus), bus->number);
621                         if (vma->vm_flags & VM_SHARED)
622                                 return shmem_zero_setup(vma);
623                         return 0;
624                 }
625                 offset += hose->isa_mem_phys;
626         } else {
627                 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
628                 unsigned long roffset = offset + io_offset;
629                 rp = &hose->io_resource;
630                 if (!(rp->flags & IORESOURCE_IO))
631                         return -ENXIO;
632                 if (roffset < rp->start || (roffset + size) > rp->end)
633                         return -ENXIO;
634                 offset += hose->io_base_phys;
635         }
636         pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
637 
638         vma->vm_pgoff = offset >> PAGE_SHIFT;
639         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
640         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
641                                vma->vm_end - vma->vm_start,
642                                vma->vm_page_prot);
643 }
644 
645 void pci_resource_to_user(const struct pci_dev *dev, int bar,
646                           const struct resource *rsrc,
647                           resource_size_t *start, resource_size_t *end)
648 {
649         struct pci_controller *hose = pci_bus_to_host(dev->bus);
650         resource_size_t offset = 0;
651 
652         if (hose == NULL)
653                 return;
654 
655         if (rsrc->flags & IORESOURCE_IO)
656                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
657 
658         /* We pass a fully fixed up address to userland for MMIO instead of
659          * a BAR value because X is lame and expects to be able to use that
660          * to pass to /dev/mem !
661          *
662          * That means that we'll have potentially 64 bits values where some
663          * userland apps only expect 32 (like X itself since it thinks only
664          * Sparc has 64 bits MMIO) but if we don't do that, we break it on
665          * 32 bits CHRPs :-(
666          *
667          * Hopefully, the sysfs insterface is immune to that gunk. Once X
668          * has been fixed (and the fix spread enough), we can re-enable the
669          * 2 lines below and pass down a BAR value to userland. In that case
670          * we'll also have to re-enable the matching code in
671          * __pci_mmap_make_offset().
672          *
673          * BenH.
674          */
675 #if 0
676         else if (rsrc->flags & IORESOURCE_MEM)
677                 offset = hose->pci_mem_offset;
678 #endif
679 
680         *start = rsrc->start - offset;
681         *end = rsrc->end - offset;
682 }
683 
684 /**
685  * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
686  * @hose: newly allocated pci_controller to be setup
687  * @dev: device node of the host bridge
688  * @primary: set if primary bus (32 bits only, soon to be deprecated)
689  *
690  * This function will parse the "ranges" property of a PCI host bridge device
691  * node and setup the resource mapping of a pci controller based on its
692  * content.
693  *
694  * Life would be boring if it wasn't for a few issues that we have to deal
695  * with here:
696  *
697  *   - We can only cope with one IO space range and up to 3 Memory space
698  *     ranges. However, some machines (thanks Apple !) tend to split their
699  *     space into lots of small contiguous ranges. So we have to coalesce.
700  *
701  *   - Some busses have IO space not starting at 0, which causes trouble with
702  *     the way we do our IO resource renumbering. The code somewhat deals with
703  *     it for 64 bits but I would expect problems on 32 bits.
704  *
705  *   - Some 32 bits platforms such as 4xx can have physical space larger than
706  *     32 bits so we need to use 64 bits values for the parsing
707  */
708 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
709                                   struct device_node *dev, int primary)
710 {
711         int memno = 0;
712         struct resource *res;
713         struct of_pci_range range;
714         struct of_pci_range_parser parser;
715 
716         printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
717                dev->full_name, primary ? "(primary)" : "");
718 
719         /* Check for ranges property */
720         if (of_pci_range_parser_init(&parser, dev))
721                 return;
722 
723         /* Parse it */
724         for_each_of_pci_range(&parser, &range) {
725                 /* If we failed translation or got a zero-sized region
726                  * (some FW try to feed us with non sensical zero sized regions
727                  * such as power3 which look like some kind of attempt at exposing
728                  * the VGA memory hole)
729                  */
730                 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
731                         continue;
732 
733                 /* Act based on address space type */
734                 res = NULL;
735                 switch (range.flags & IORESOURCE_TYPE_BITS) {
736                 case IORESOURCE_IO:
737                         printk(KERN_INFO
738                                "  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
739                                range.cpu_addr, range.cpu_addr + range.size - 1,
740                                range.pci_addr);
741 
742                         /* We support only one IO range */
743                         if (hose->pci_io_size) {
744                                 printk(KERN_INFO
745                                        " \\--> Skipped (too many) !\n");
746                                 continue;
747                         }
748 #ifdef CONFIG_PPC32
749                         /* On 32 bits, limit I/O space to 16MB */
750                         if (range.size > 0x01000000)
751                                 range.size = 0x01000000;
752 
753                         /* 32 bits needs to map IOs here */
754                         hose->io_base_virt = ioremap(range.cpu_addr,
755                                                 range.size);
756 
757                         /* Expect trouble if pci_addr is not 0 */
758                         if (primary)
759                                 isa_io_base =
760                                         (unsigned long)hose->io_base_virt;
761 #endif /* CONFIG_PPC32 */
762                         /* pci_io_size and io_base_phys always represent IO
763                          * space starting at 0 so we factor in pci_addr
764                          */
765                         hose->pci_io_size = range.pci_addr + range.size;
766                         hose->io_base_phys = range.cpu_addr - range.pci_addr;
767 
768                         /* Build resource */
769                         res = &hose->io_resource;
770                         range.cpu_addr = range.pci_addr;
771                         break;
772                 case IORESOURCE_MEM:
773                         printk(KERN_INFO
774                                " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
775                                range.cpu_addr, range.cpu_addr + range.size - 1,
776                                range.pci_addr,
777                                (range.pci_space & 0x40000000) ?
778                                "Prefetch" : "");
779 
780                         /* We support only 3 memory ranges */
781                         if (memno >= 3) {
782                                 printk(KERN_INFO
783                                        " \\--> Skipped (too many) !\n");
784                                 continue;
785                         }
786                         /* Handles ISA memory hole space here */
787                         if (range.pci_addr == 0) {
788                                 if (primary || isa_mem_base == 0)
789                                         isa_mem_base = range.cpu_addr;
790                                 hose->isa_mem_phys = range.cpu_addr;
791                                 hose->isa_mem_size = range.size;
792                         }
793 
794                         /* Build resource */
795                         hose->mem_offset[memno] = range.cpu_addr -
796                                                         range.pci_addr;
797                         res = &hose->mem_resources[memno++];
798                         break;
799                 }
800                 if (res != NULL) {
801                         res->name = dev->full_name;
802                         res->flags = range.flags;
803                         res->start = range.cpu_addr;
804                         res->end = range.cpu_addr + range.size - 1;
805                         res->parent = res->child = res->sibling = NULL;
806                 }
807         }
808 }
809 
810 /* Decide whether to display the domain number in /proc */
811 int pci_proc_domain(struct pci_bus *bus)
812 {
813         struct pci_controller *hose = pci_bus_to_host(bus);
814 
815         if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
816                 return 0;
817         if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
818                 return hose->global_number != 0;
819         return 1;
820 }
821 
822 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
823 {
824         if (ppc_md.pcibios_root_bridge_prepare)
825                 return ppc_md.pcibios_root_bridge_prepare(bridge);
826 
827         return 0;
828 }
829 
830 /* This header fixup will do the resource fixup for all devices as they are
831  * probed, but not for bridge ranges
832  */
833 static void pcibios_fixup_resources(struct pci_dev *dev)
834 {
835         struct pci_controller *hose = pci_bus_to_host(dev->bus);
836         int i;
837 
838         if (!hose) {
839                 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
840                        pci_name(dev));
841                 return;
842         }
843 
844         if (dev->is_virtfn)
845                 return;
846 
847         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
848                 struct resource *res = dev->resource + i;
849                 struct pci_bus_region reg;
850                 if (!res->flags)
851                         continue;
852 
853                 /* If we're going to re-assign everything, we mark all resources
854                  * as unset (and 0-base them). In addition, we mark BARs starting
855                  * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
856                  * since in that case, we don't want to re-assign anything
857                  */
858                 pcibios_resource_to_bus(dev->bus, &reg, res);
859                 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
860                     (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
861                         /* Only print message if not re-assigning */
862                         if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
863                                 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
864                                          pci_name(dev), i, res);
865                         res->end -= res->start;
866                         res->start = 0;
867                         res->flags |= IORESOURCE_UNSET;
868                         continue;
869                 }
870 
871                 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
872         }
873 
874         /* Call machine specific resource fixup */
875         if (ppc_md.pcibios_fixup_resources)
876                 ppc_md.pcibios_fixup_resources(dev);
877 }
878 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
879 
880 /* This function tries to figure out if a bridge resource has been initialized
881  * by the firmware or not. It doesn't have to be absolutely bullet proof, but
882  * things go more smoothly when it gets it right. It should covers cases such
883  * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
884  */
885 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
886                                                  struct resource *res)
887 {
888         struct pci_controller *hose = pci_bus_to_host(bus);
889         struct pci_dev *dev = bus->self;
890         resource_size_t offset;
891         struct pci_bus_region region;
892         u16 command;
893         int i;
894 
895         /* We don't do anything if PCI_PROBE_ONLY is set */
896         if (pci_has_flag(PCI_PROBE_ONLY))
897                 return 0;
898 
899         /* Job is a bit different between memory and IO */
900         if (res->flags & IORESOURCE_MEM) {
901                 pcibios_resource_to_bus(dev->bus, &region, res);
902 
903                 /* If the BAR is non-0 then it's probably been initialized */
904                 if (region.start != 0)
905                         return 0;
906 
907                 /* The BAR is 0, let's check if memory decoding is enabled on
908                  * the bridge. If not, we consider it unassigned
909                  */
910                 pci_read_config_word(dev, PCI_COMMAND, &command);
911                 if ((command & PCI_COMMAND_MEMORY) == 0)
912                         return 1;
913 
914                 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
915                  * resources covers that starting address (0 then it's good enough for
916                  * us for memory space)
917                  */
918                 for (i = 0; i < 3; i++) {
919                         if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
920                             hose->mem_resources[i].start == hose->mem_offset[i])
921                                 return 0;
922                 }
923 
924                 /* Well, it starts at 0 and we know it will collide so we may as
925                  * well consider it as unassigned. That covers the Apple case.
926                  */
927                 return 1;
928         } else {
929                 /* If the BAR is non-0, then we consider it assigned */
930                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
931                 if (((res->start - offset) & 0xfffffffful) != 0)
932                         return 0;
933 
934                 /* Here, we are a bit different than memory as typically IO space
935                  * starting at low addresses -is- valid. What we do instead if that
936                  * we consider as unassigned anything that doesn't have IO enabled
937                  * in the PCI command register, and that's it.
938                  */
939                 pci_read_config_word(dev, PCI_COMMAND, &command);
940                 if (command & PCI_COMMAND_IO)
941                         return 0;
942 
943                 /* It's starting at 0 and IO is disabled in the bridge, consider
944                  * it unassigned
945                  */
946                 return 1;
947         }
948 }
949 
950 /* Fixup resources of a PCI<->PCI bridge */
951 static void pcibios_fixup_bridge(struct pci_bus *bus)
952 {
953         struct resource *res;
954         int i;
955 
956         struct pci_dev *dev = bus->self;
957 
958         pci_bus_for_each_resource(bus, res, i) {
959                 if (!res || !res->flags)
960                         continue;
961                 if (i >= 3 && bus->self->transparent)
962                         continue;
963 
964                 /* If we're going to reassign everything, we can
965                  * shrink the P2P resource to have size as being
966                  * of 0 in order to save space.
967                  */
968                 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
969                         res->flags |= IORESOURCE_UNSET;
970                         res->start = 0;
971                         res->end = -1;
972                         continue;
973                 }
974 
975                 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
976 
977                 /* Try to detect uninitialized P2P bridge resources,
978                  * and clear them out so they get re-assigned later
979                  */
980                 if (pcibios_uninitialized_bridge_resource(bus, res)) {
981                         res->flags = 0;
982                         pr_debug("PCI:%s            (unassigned)\n", pci_name(dev));
983                 }
984         }
985 }
986 
987 void pcibios_setup_bus_self(struct pci_bus *bus)
988 {
989         struct pci_controller *phb;
990 
991         /* Fix up the bus resources for P2P bridges */
992         if (bus->self != NULL)
993                 pcibios_fixup_bridge(bus);
994 
995         /* Platform specific bus fixups. This is currently only used
996          * by fsl_pci and I'm hoping to get rid of it at some point
997          */
998         if (ppc_md.pcibios_fixup_bus)
999                 ppc_md.pcibios_fixup_bus(bus);
1000 
1001         /* Setup bus DMA mappings */
1002         phb = pci_bus_to_host(bus);
1003         if (phb->controller_ops.dma_bus_setup)
1004                 phb->controller_ops.dma_bus_setup(bus);
1005 }
1006 
1007 static void pcibios_setup_device(struct pci_dev *dev)
1008 {
1009         struct pci_controller *phb;
1010         /* Fixup NUMA node as it may not be setup yet by the generic
1011          * code and is needed by the DMA init
1012          */
1013         set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1014 
1015         /* Hook up default DMA ops */
1016         set_dma_ops(&dev->dev, pci_dma_ops);
1017         set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1018 
1019         /* Additional platform DMA/iommu setup */
1020         phb = pci_bus_to_host(dev->bus);
1021         if (phb->controller_ops.dma_dev_setup)
1022                 phb->controller_ops.dma_dev_setup(dev);
1023 
1024         /* Read default IRQs and fixup if necessary */
1025         pci_read_irq_line(dev);
1026         if (ppc_md.pci_irq_fixup)
1027                 ppc_md.pci_irq_fixup(dev);
1028 }
1029 
1030 int pcibios_add_device(struct pci_dev *dev)
1031 {
1032         /*
1033          * We can only call pcibios_setup_device() after bus setup is complete,
1034          * since some of the platform specific DMA setup code depends on it.
1035          */
1036         if (dev->bus->is_added)
1037                 pcibios_setup_device(dev);
1038 
1039 #ifdef CONFIG_PCI_IOV
1040         if (ppc_md.pcibios_fixup_sriov)
1041                 ppc_md.pcibios_fixup_sriov(dev);
1042 #endif /* CONFIG_PCI_IOV */
1043 
1044         return 0;
1045 }
1046 
1047 void pcibios_setup_bus_devices(struct pci_bus *bus)
1048 {
1049         struct pci_dev *dev;
1050 
1051         pr_debug("PCI: Fixup bus devices %d (%s)\n",
1052                  bus->number, bus->self ? pci_name(bus->self) : "PHB");
1053 
1054         list_for_each_entry(dev, &bus->devices, bus_list) {
1055                 /* Cardbus can call us to add new devices to a bus, so ignore
1056                  * those who are already fully discovered
1057                  */
1058                 if (dev->is_added)
1059                         continue;
1060 
1061                 pcibios_setup_device(dev);
1062         }
1063 }
1064 
1065 void pcibios_set_master(struct pci_dev *dev)
1066 {
1067         /* No special bus mastering setup handling */
1068 }
1069 
1070 void pcibios_fixup_bus(struct pci_bus *bus)
1071 {
1072         /* When called from the generic PCI probe, read PCI<->PCI bridge
1073          * bases. This is -not- called when generating the PCI tree from
1074          * the OF device-tree.
1075          */
1076         pci_read_bridge_bases(bus);
1077 
1078         /* Now fixup the bus bus */
1079         pcibios_setup_bus_self(bus);
1080 
1081         /* Now fixup devices on that bus */
1082         pcibios_setup_bus_devices(bus);
1083 }
1084 EXPORT_SYMBOL(pcibios_fixup_bus);
1085 
1086 void pci_fixup_cardbus(struct pci_bus *bus)
1087 {
1088         /* Now fixup devices on that bus */
1089         pcibios_setup_bus_devices(bus);
1090 }
1091 
1092 
1093 static int skip_isa_ioresource_align(struct pci_dev *dev)
1094 {
1095         if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1096             !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1097                 return 1;
1098         return 0;
1099 }
1100 
1101 /*
1102  * We need to avoid collisions with `mirrored' VGA ports
1103  * and other strange ISA hardware, so we always want the
1104  * addresses to be allocated in the 0x000-0x0ff region
1105  * modulo 0x400.
1106  *
1107  * Why? Because some silly external IO cards only decode
1108  * the low 10 bits of the IO address. The 0x00-0xff region
1109  * is reserved for motherboard devices that decode all 16
1110  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1111  * but we want to try to avoid allocating at 0x2900-0x2bff
1112  * which might have be mirrored at 0x0100-0x03ff..
1113  */
1114 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1115                                 resource_size_t size, resource_size_t align)
1116 {
1117         struct pci_dev *dev = data;
1118         resource_size_t start = res->start;
1119 
1120         if (res->flags & IORESOURCE_IO) {
1121                 if (skip_isa_ioresource_align(dev))
1122                         return start;
1123                 if (start & 0x300)
1124                         start = (start + 0x3ff) & ~0x3ff;
1125         }
1126 
1127         return start;
1128 }
1129 EXPORT_SYMBOL(pcibios_align_resource);
1130 
1131 /*
1132  * Reparent resource children of pr that conflict with res
1133  * under res, and make res replace those children.
1134  */
1135 static int reparent_resources(struct resource *parent,
1136                                      struct resource *res)
1137 {
1138         struct resource *p, **pp;
1139         struct resource **firstpp = NULL;
1140 
1141         for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1142                 if (p->end < res->start)
1143                         continue;
1144                 if (res->end < p->start)
1145                         break;
1146                 if (p->start < res->start || p->end > res->end)
1147                         return -1;      /* not completely contained */
1148                 if (firstpp == NULL)
1149                         firstpp = pp;
1150         }
1151         if (firstpp == NULL)
1152                 return -1;      /* didn't find any conflicting entries? */
1153         res->parent = parent;
1154         res->child = *firstpp;
1155         res->sibling = *pp;
1156         *firstpp = res;
1157         *pp = NULL;
1158         for (p = res->child; p != NULL; p = p->sibling) {
1159                 p->parent = res;
1160                 pr_debug("PCI: Reparented %s %pR under %s\n",
1161                          p->name, p, res->name);
1162         }
1163         return 0;
1164 }
1165 
1166 /*
1167  *  Handle resources of PCI devices.  If the world were perfect, we could
1168  *  just allocate all the resource regions and do nothing more.  It isn't.
1169  *  On the other hand, we cannot just re-allocate all devices, as it would
1170  *  require us to know lots of host bridge internals.  So we attempt to
1171  *  keep as much of the original configuration as possible, but tweak it
1172  *  when it's found to be wrong.
1173  *
1174  *  Known BIOS problems we have to work around:
1175  *      - I/O or memory regions not configured
1176  *      - regions configured, but not enabled in the command register
1177  *      - bogus I/O addresses above 64K used
1178  *      - expansion ROMs left enabled (this may sound harmless, but given
1179  *        the fact the PCI specs explicitly allow address decoders to be
1180  *        shared between expansion ROMs and other resource regions, it's
1181  *        at least dangerous)
1182  *
1183  *  Our solution:
1184  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1185  *          This gives us fixed barriers on where we can allocate.
1186  *      (2) Allocate resources for all enabled devices.  If there is
1187  *          a collision, just mark the resource as unallocated. Also
1188  *          disable expansion ROMs during this step.
1189  *      (3) Try to allocate resources for disabled devices.  If the
1190  *          resources were assigned correctly, everything goes well,
1191  *          if they weren't, they won't disturb allocation of other
1192  *          resources.
1193  *      (4) Assign new addresses to resources which were either
1194  *          not configured at all or misconfigured.  If explicitly
1195  *          requested by the user, configure expansion ROM address
1196  *          as well.
1197  */
1198 
1199 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1200 {
1201         struct pci_bus *b;
1202         int i;
1203         struct resource *res, *pr;
1204 
1205         pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1206                  pci_domain_nr(bus), bus->number);
1207 
1208         pci_bus_for_each_resource(bus, res, i) {
1209                 if (!res || !res->flags || res->start > res->end || res->parent)
1210                         continue;
1211 
1212                 /* If the resource was left unset at this point, we clear it */
1213                 if (res->flags & IORESOURCE_UNSET)
1214                         goto clear_resource;
1215 
1216                 if (bus->parent == NULL)
1217                         pr = (res->flags & IORESOURCE_IO) ?
1218                                 &ioport_resource : &iomem_resource;
1219                 else {
1220                         pr = pci_find_parent_resource(bus->self, res);
1221                         if (pr == res) {
1222                                 /* this happens when the generic PCI
1223                                  * code (wrongly) decides that this
1224                                  * bridge is transparent  -- paulus
1225                                  */
1226                                 continue;
1227                         }
1228                 }
1229 
1230                 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1231                          bus->self ? pci_name(bus->self) : "PHB", bus->number,
1232                          i, res, pr, (pr && pr->name) ? pr->name : "nil");
1233 
1234                 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1235                         struct pci_dev *dev = bus->self;
1236 
1237                         if (request_resource(pr, res) == 0)
1238                                 continue;
1239                         /*
1240                          * Must be a conflict with an existing entry.
1241                          * Move that entry (or entries) under the
1242                          * bridge resource and try again.
1243                          */
1244                         if (reparent_resources(pr, res) == 0)
1245                                 continue;
1246 
1247                         if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1248                             pci_claim_bridge_resource(dev,
1249                                                 i + PCI_BRIDGE_RESOURCES) == 0)
1250                                 continue;
1251                 }
1252                 pr_warning("PCI: Cannot allocate resource region "
1253                            "%d of PCI bridge %d, will remap\n", i, bus->number);
1254         clear_resource:
1255                 /* The resource might be figured out when doing
1256                  * reassignment based on the resources required
1257                  * by the downstream PCI devices. Here we set
1258                  * the size of the resource to be 0 in order to
1259                  * save more space.
1260                  */
1261                 res->start = 0;
1262                 res->end = -1;
1263                 res->flags = 0;
1264         }
1265 
1266         list_for_each_entry(b, &bus->children, node)
1267                 pcibios_allocate_bus_resources(b);
1268 }
1269 
1270 static inline void alloc_resource(struct pci_dev *dev, int idx)
1271 {
1272         struct resource *pr, *r = &dev->resource[idx];
1273 
1274         pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1275                  pci_name(dev), idx, r);
1276 
1277         pr = pci_find_parent_resource(dev, r);
1278         if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1279             request_resource(pr, r) < 0) {
1280                 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1281                        " of device %s, will remap\n", idx, pci_name(dev));
1282                 if (pr)
1283                         pr_debug("PCI:  parent is %p: %pR\n", pr, pr);
1284                 /* We'll assign a new address later */
1285                 r->flags |= IORESOURCE_UNSET;
1286                 r->end -= r->start;
1287                 r->start = 0;
1288         }
1289 }
1290 
1291 static void __init pcibios_allocate_resources(int pass)
1292 {
1293         struct pci_dev *dev = NULL;
1294         int idx, disabled;
1295         u16 command;
1296         struct resource *r;
1297 
1298         for_each_pci_dev(dev) {
1299                 pci_read_config_word(dev, PCI_COMMAND, &command);
1300                 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1301                         r = &dev->resource[idx];
1302                         if (r->parent)          /* Already allocated */
1303                                 continue;
1304                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
1305                                 continue;       /* Not assigned at all */
1306                         /* We only allocate ROMs on pass 1 just in case they
1307                          * have been screwed up by firmware
1308                          */
1309                         if (idx == PCI_ROM_RESOURCE )
1310                                 disabled = 1;
1311                         if (r->flags & IORESOURCE_IO)
1312                                 disabled = !(command & PCI_COMMAND_IO);
1313                         else
1314                                 disabled = !(command & PCI_COMMAND_MEMORY);
1315                         if (pass == disabled)
1316                                 alloc_resource(dev, idx);
1317                 }
1318                 if (pass)
1319                         continue;
1320                 r = &dev->resource[PCI_ROM_RESOURCE];
1321                 if (r->flags) {
1322                         /* Turn the ROM off, leave the resource region,
1323                          * but keep it unregistered.
1324                          */
1325                         u32 reg;
1326                         pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1327                         if (reg & PCI_ROM_ADDRESS_ENABLE) {
1328                                 pr_debug("PCI: Switching off ROM of %s\n",
1329                                          pci_name(dev));
1330                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
1331                                 pci_write_config_dword(dev, dev->rom_base_reg,
1332                                                        reg & ~PCI_ROM_ADDRESS_ENABLE);
1333                         }
1334                 }
1335         }
1336 }
1337 
1338 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1339 {
1340         struct pci_controller *hose = pci_bus_to_host(bus);
1341         resource_size_t offset;
1342         struct resource *res, *pres;
1343         int i;
1344 
1345         pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1346 
1347         /* Check for IO */
1348         if (!(hose->io_resource.flags & IORESOURCE_IO))
1349                 goto no_io;
1350         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1351         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1352         BUG_ON(res == NULL);
1353         res->name = "Legacy IO";
1354         res->flags = IORESOURCE_IO;
1355         res->start = offset;
1356         res->end = (offset + 0xfff) & 0xfffffffful;
1357         pr_debug("Candidate legacy IO: %pR\n", res);
1358         if (request_resource(&hose->io_resource, res)) {
1359                 printk(KERN_DEBUG
1360                        "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1361                        pci_domain_nr(bus), bus->number, res);
1362                 kfree(res);
1363         }
1364 
1365  no_io:
1366         /* Check for memory */
1367         for (i = 0; i < 3; i++) {
1368                 pres = &hose->mem_resources[i];
1369                 offset = hose->mem_offset[i];
1370                 if (!(pres->flags & IORESOURCE_MEM))
1371                         continue;
1372                 pr_debug("hose mem res: %pR\n", pres);
1373                 if ((pres->start - offset) <= 0xa0000 &&
1374                     (pres->end - offset) >= 0xbffff)
1375                         break;
1376         }
1377         if (i >= 3)
1378                 return;
1379         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1380         BUG_ON(res == NULL);
1381         res->name = "Legacy VGA memory";
1382         res->flags = IORESOURCE_MEM;
1383         res->start = 0xa0000 + offset;
1384         res->end = 0xbffff + offset;
1385         pr_debug("Candidate VGA memory: %pR\n", res);
1386         if (request_resource(pres, res)) {
1387                 printk(KERN_DEBUG
1388                        "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1389                        pci_domain_nr(bus), bus->number, res);
1390                 kfree(res);
1391         }
1392 }
1393 
1394 void __init pcibios_resource_survey(void)
1395 {
1396         struct pci_bus *b;
1397 
1398         /* Allocate and assign resources */
1399         list_for_each_entry(b, &pci_root_buses, node)
1400                 pcibios_allocate_bus_resources(b);
1401         pcibios_allocate_resources(0);
1402         pcibios_allocate_resources(1);
1403 
1404         /* Before we start assigning unassigned resource, we try to reserve
1405          * the low IO area and the VGA memory area if they intersect the
1406          * bus available resources to avoid allocating things on top of them
1407          */
1408         if (!pci_has_flag(PCI_PROBE_ONLY)) {
1409                 list_for_each_entry(b, &pci_root_buses, node)
1410                         pcibios_reserve_legacy_regions(b);
1411         }
1412 
1413         /* Now, if the platform didn't decide to blindly trust the firmware,
1414          * we proceed to assigning things that were left unassigned
1415          */
1416         if (!pci_has_flag(PCI_PROBE_ONLY)) {
1417                 pr_debug("PCI: Assigning unassigned resources...\n");
1418                 pci_assign_unassigned_resources();
1419         }
1420 
1421         /* Call machine dependent fixup */
1422         if (ppc_md.pcibios_fixup)
1423                 ppc_md.pcibios_fixup();
1424 }
1425 
1426 /* This is used by the PCI hotplug driver to allocate resource
1427  * of newly plugged busses. We can try to consolidate with the
1428  * rest of the code later, for now, keep it as-is as our main
1429  * resource allocation function doesn't deal with sub-trees yet.
1430  */
1431 void pcibios_claim_one_bus(struct pci_bus *bus)
1432 {
1433         struct pci_dev *dev;
1434         struct pci_bus *child_bus;
1435 
1436         list_for_each_entry(dev, &bus->devices, bus_list) {
1437                 int i;
1438 
1439                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1440                         struct resource *r = &dev->resource[i];
1441 
1442                         if (r->parent || !r->start || !r->flags)
1443                                 continue;
1444 
1445                         pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1446                                  pci_name(dev), i, r);
1447 
1448                         if (pci_claim_resource(dev, i) == 0)
1449                                 continue;
1450 
1451                         pci_claim_bridge_resource(dev, i);
1452                 }
1453         }
1454 
1455         list_for_each_entry(child_bus, &bus->children, node)
1456                 pcibios_claim_one_bus(child_bus);
1457 }
1458 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1459 
1460 
1461 /* pcibios_finish_adding_to_bus
1462  *
1463  * This is to be called by the hotplug code after devices have been
1464  * added to a bus, this include calling it for a PHB that is just
1465  * being added
1466  */
1467 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1468 {
1469         pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1470                  pci_domain_nr(bus), bus->number);
1471 
1472         /* Allocate bus and devices resources */
1473         pcibios_allocate_bus_resources(bus);
1474         pcibios_claim_one_bus(bus);
1475         if (!pci_has_flag(PCI_PROBE_ONLY))
1476                 pci_assign_unassigned_bus_resources(bus);
1477 
1478         /* Fixup EEH */
1479         eeh_add_device_tree_late(bus);
1480 
1481         /* Add new devices to global lists.  Register in proc, sysfs. */
1482         pci_bus_add_devices(bus);
1483 
1484         /* sysfs files should only be added after devices are added */
1485         eeh_add_sysfs_files(bus);
1486 }
1487 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1488 
1489 int pcibios_enable_device(struct pci_dev *dev, int mask)
1490 {
1491         struct pci_controller *phb = pci_bus_to_host(dev->bus);
1492 
1493         if (phb->controller_ops.enable_device_hook)
1494                 if (!phb->controller_ops.enable_device_hook(dev))
1495                         return -EINVAL;
1496 
1497         return pci_enable_resources(dev, mask);
1498 }
1499 
1500 void pcibios_disable_device(struct pci_dev *dev)
1501 {
1502         struct pci_controller *phb = pci_bus_to_host(dev->bus);
1503 
1504         if (phb->controller_ops.disable_device)
1505                 phb->controller_ops.disable_device(dev);
1506 }
1507 
1508 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1509 {
1510         return (unsigned long) hose->io_base_virt - _IO_BASE;
1511 }
1512 
1513 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1514                                         struct list_head *resources)
1515 {
1516         struct resource *res;
1517         resource_size_t offset;
1518         int i;
1519 
1520         /* Hookup PHB IO resource */
1521         res = &hose->io_resource;
1522 
1523         if (!res->flags) {
1524                 pr_info("PCI: I/O resource not set for host"
1525                        " bridge %s (domain %d)\n",
1526                        hose->dn->full_name, hose->global_number);
1527         } else {
1528                 offset = pcibios_io_space_offset(hose);
1529 
1530                 pr_debug("PCI: PHB IO resource    = %pR off 0x%08llx\n",
1531                          res, (unsigned long long)offset);
1532                 pci_add_resource_offset(resources, res, offset);
1533         }
1534 
1535         /* Hookup PHB Memory resources */
1536         for (i = 0; i < 3; ++i) {
1537                 res = &hose->mem_resources[i];
1538                 if (!res->flags) {
1539                         if (i == 0)
1540                                 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1541                                        "host bridge %s (domain %d)\n",
1542                                        hose->dn->full_name, hose->global_number);
1543                         continue;
1544                 }
1545                 offset = hose->mem_offset[i];
1546 
1547 
1548                 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1549                          res, (unsigned long long)offset);
1550 
1551                 pci_add_resource_offset(resources, res, offset);
1552         }
1553 }
1554 
1555 /*
1556  * Null PCI config access functions, for the case when we can't
1557  * find a hose.
1558  */
1559 #define NULL_PCI_OP(rw, size, type)                                     \
1560 static int                                                              \
1561 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
1562 {                                                                       \
1563         return PCIBIOS_DEVICE_NOT_FOUND;                                \
1564 }
1565 
1566 static int
1567 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1568                  int len, u32 *val)
1569 {
1570         return PCIBIOS_DEVICE_NOT_FOUND;
1571 }
1572 
1573 static int
1574 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1575                   int len, u32 val)
1576 {
1577         return PCIBIOS_DEVICE_NOT_FOUND;
1578 }
1579 
1580 static struct pci_ops null_pci_ops =
1581 {
1582         .read = null_read_config,
1583         .write = null_write_config,
1584 };
1585 
1586 /*
1587  * These functions are used early on before PCI scanning is done
1588  * and all of the pci_dev and pci_bus structures have been created.
1589  */
1590 static struct pci_bus *
1591 fake_pci_bus(struct pci_controller *hose, int busnr)
1592 {
1593         static struct pci_bus bus;
1594 
1595         if (hose == NULL) {
1596                 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1597         }
1598         bus.number = busnr;
1599         bus.sysdata = hose;
1600         bus.ops = hose? hose->ops: &null_pci_ops;
1601         return &bus;
1602 }
1603 
1604 #define EARLY_PCI_OP(rw, size, type)                                    \
1605 int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
1606                                int devfn, int offset, type value)       \
1607 {                                                                       \
1608         return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
1609                                             devfn, offset, value);      \
1610 }
1611 
1612 EARLY_PCI_OP(read, byte, u8 *)
1613 EARLY_PCI_OP(read, word, u16 *)
1614 EARLY_PCI_OP(read, dword, u32 *)
1615 EARLY_PCI_OP(write, byte, u8)
1616 EARLY_PCI_OP(write, word, u16)
1617 EARLY_PCI_OP(write, dword, u32)
1618 
1619 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1620                           int cap)
1621 {
1622         return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1623 }
1624 
1625 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1626 {
1627         struct pci_controller *hose = bus->sysdata;
1628 
1629         return of_node_get(hose->dn);
1630 }
1631 
1632 /**
1633  * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1634  * @hose: Pointer to the PCI host controller instance structure
1635  */
1636 void pcibios_scan_phb(struct pci_controller *hose)
1637 {
1638         LIST_HEAD(resources);
1639         struct pci_bus *bus;
1640         struct device_node *node = hose->dn;
1641         int mode;
1642 
1643         pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1644 
1645         /* Get some IO space for the new PHB */
1646         pcibios_setup_phb_io_space(hose);
1647 
1648         /* Wire up PHB bus resources */
1649         pcibios_setup_phb_resources(hose, &resources);
1650 
1651         hose->busn.start = hose->first_busno;
1652         hose->busn.end   = hose->last_busno;
1653         hose->busn.flags = IORESOURCE_BUS;
1654         pci_add_resource(&resources, &hose->busn);
1655 
1656         /* Create an empty bus for the toplevel */
1657         bus = pci_create_root_bus(hose->parent, hose->first_busno,
1658                                   hose->ops, hose, &resources);
1659         if (bus == NULL) {
1660                 pr_err("Failed to create bus for PCI domain %04x\n",
1661                         hose->global_number);
1662                 pci_free_resource_list(&resources);
1663                 return;
1664         }
1665         hose->bus = bus;
1666 
1667         /* Get probe mode and perform scan */
1668         mode = PCI_PROBE_NORMAL;
1669         if (node && hose->controller_ops.probe_mode)
1670                 mode = hose->controller_ops.probe_mode(bus);
1671         pr_debug("    probe mode: %d\n", mode);
1672         if (mode == PCI_PROBE_DEVTREE)
1673                 of_scan_bus(node, bus);
1674 
1675         if (mode == PCI_PROBE_NORMAL) {
1676                 pci_bus_update_busn_res_end(bus, 255);
1677                 hose->last_busno = pci_scan_child_bus(bus);
1678                 pci_bus_update_busn_res_end(bus, hose->last_busno);
1679         }
1680 
1681         /* Platform gets a chance to do some global fixups before
1682          * we proceed to resource allocation
1683          */
1684         if (ppc_md.pcibios_fixup_phb)
1685                 ppc_md.pcibios_fixup_phb(hose);
1686 
1687         /* Configure PCI Express settings */
1688         if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1689                 struct pci_bus *child;
1690                 list_for_each_entry(child, &bus->children, node)
1691                         pcie_bus_configure_settings(child);
1692         }
1693 }
1694 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1695 
1696 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1697 {
1698         int i, class = dev->class >> 8;
1699         /* When configured as agent, programing interface = 1 */
1700         int prog_if = dev->class & 0xf;
1701 
1702         if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1703              class == PCI_CLASS_BRIDGE_OTHER) &&
1704                 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1705                 (prog_if == 0) &&
1706                 (dev->bus->parent == NULL)) {
1707                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1708                         dev->resource[i].start = 0;
1709                         dev->resource[i].end = 0;
1710                         dev->resource[i].flags = 0;
1711                 }
1712         }
1713 }
1714 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1716 
1717 static void fixup_vga(struct pci_dev *pdev)
1718 {
1719         u16 cmd;
1720 
1721         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1722         if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1723                 vga_set_default_device(pdev);
1724 
1725 }
1726 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1727                               PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);
1728 

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