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Linux/arch/powerpc/kernel/process.c

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  1 /*
  2  *  Derived from "arch/i386/kernel/process.c"
  3  *    Copyright (C) 1995  Linus Torvalds
  4  *
  5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
  6  *  Paul Mackerras (paulus@cs.anu.edu.au)
  7  *
  8  *  PowerPC version
  9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 10  *
 11  *  This program is free software; you can redistribute it and/or
 12  *  modify it under the terms of the GNU General Public License
 13  *  as published by the Free Software Foundation; either version
 14  *  2 of the License, or (at your option) any later version.
 15  */
 16 
 17 #include <linux/errno.h>
 18 #include <linux/sched.h>
 19 #include <linux/kernel.h>
 20 #include <linux/mm.h>
 21 #include <linux/smp.h>
 22 #include <linux/stddef.h>
 23 #include <linux/unistd.h>
 24 #include <linux/ptrace.h>
 25 #include <linux/slab.h>
 26 #include <linux/user.h>
 27 #include <linux/elf.h>
 28 #include <linux/prctl.h>
 29 #include <linux/init_task.h>
 30 #include <linux/export.h>
 31 #include <linux/kallsyms.h>
 32 #include <linux/mqueue.h>
 33 #include <linux/hardirq.h>
 34 #include <linux/utsname.h>
 35 #include <linux/ftrace.h>
 36 #include <linux/kernel_stat.h>
 37 #include <linux/personality.h>
 38 #include <linux/random.h>
 39 #include <linux/hw_breakpoint.h>
 40 
 41 #include <asm/pgtable.h>
 42 #include <asm/uaccess.h>
 43 #include <asm/io.h>
 44 #include <asm/processor.h>
 45 #include <asm/mmu.h>
 46 #include <asm/prom.h>
 47 #include <asm/machdep.h>
 48 #include <asm/time.h>
 49 #include <asm/runlatch.h>
 50 #include <asm/syscalls.h>
 51 #include <asm/switch_to.h>
 52 #include <asm/tm.h>
 53 #include <asm/debug.h>
 54 #ifdef CONFIG_PPC64
 55 #include <asm/firmware.h>
 56 #endif
 57 #include <asm/code-patching.h>
 58 #include <linux/kprobes.h>
 59 #include <linux/kdebug.h>
 60 
 61 /* Transactional Memory debug */
 62 #ifdef TM_DEBUG_SW
 63 #define TM_DEBUG(x...) printk(KERN_INFO x)
 64 #else
 65 #define TM_DEBUG(x...) do { } while(0)
 66 #endif
 67 
 68 extern unsigned long _get_SP(void);
 69 
 70 #ifndef CONFIG_SMP
 71 struct task_struct *last_task_used_math = NULL;
 72 struct task_struct *last_task_used_altivec = NULL;
 73 struct task_struct *last_task_used_vsx = NULL;
 74 struct task_struct *last_task_used_spe = NULL;
 75 #endif
 76 
 77 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 78 void giveup_fpu_maybe_transactional(struct task_struct *tsk)
 79 {
 80         /*
 81          * If we are saving the current thread's registers, and the
 82          * thread is in a transactional state, set the TIF_RESTORE_TM
 83          * bit so that we know to restore the registers before
 84          * returning to userspace.
 85          */
 86         if (tsk == current && tsk->thread.regs &&
 87             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
 88             !test_thread_flag(TIF_RESTORE_TM)) {
 89                 tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
 90                 set_thread_flag(TIF_RESTORE_TM);
 91         }
 92 
 93         giveup_fpu(tsk);
 94 }
 95 
 96 void giveup_altivec_maybe_transactional(struct task_struct *tsk)
 97 {
 98         /*
 99          * If we are saving the current thread's registers, and the
100          * thread is in a transactional state, set the TIF_RESTORE_TM
101          * bit so that we know to restore the registers before
102          * returning to userspace.
103          */
104         if (tsk == current && tsk->thread.regs &&
105             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
106             !test_thread_flag(TIF_RESTORE_TM)) {
107                 tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
108                 set_thread_flag(TIF_RESTORE_TM);
109         }
110 
111         giveup_altivec(tsk);
112 }
113 
114 #else
115 #define giveup_fpu_maybe_transactional(tsk)     giveup_fpu(tsk)
116 #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk)
117 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
118 
119 #ifdef CONFIG_PPC_FPU
120 /*
121  * Make sure the floating-point register state in the
122  * the thread_struct is up to date for task tsk.
123  */
124 void flush_fp_to_thread(struct task_struct *tsk)
125 {
126         if (tsk->thread.regs) {
127                 /*
128                  * We need to disable preemption here because if we didn't,
129                  * another process could get scheduled after the regs->msr
130                  * test but before we have finished saving the FP registers
131                  * to the thread_struct.  That process could take over the
132                  * FPU, and then when we get scheduled again we would store
133                  * bogus values for the remaining FP registers.
134                  */
135                 preempt_disable();
136                 if (tsk->thread.regs->msr & MSR_FP) {
137 #ifdef CONFIG_SMP
138                         /*
139                          * This should only ever be called for current or
140                          * for a stopped child process.  Since we save away
141                          * the FP register state on context switch on SMP,
142                          * there is something wrong if a stopped child appears
143                          * to still have its FP state in the CPU registers.
144                          */
145                         BUG_ON(tsk != current);
146 #endif
147                         giveup_fpu_maybe_transactional(tsk);
148                 }
149                 preempt_enable();
150         }
151 }
152 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
153 #endif /* CONFIG_PPC_FPU */
154 
155 void enable_kernel_fp(void)
156 {
157         WARN_ON(preemptible());
158 
159 #ifdef CONFIG_SMP
160         if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
161                 giveup_fpu_maybe_transactional(current);
162         else
163                 giveup_fpu(NULL);       /* just enables FP for kernel */
164 #else
165         giveup_fpu_maybe_transactional(last_task_used_math);
166 #endif /* CONFIG_SMP */
167 }
168 EXPORT_SYMBOL(enable_kernel_fp);
169 
170 #ifdef CONFIG_ALTIVEC
171 void enable_kernel_altivec(void)
172 {
173         WARN_ON(preemptible());
174 
175 #ifdef CONFIG_SMP
176         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
177                 giveup_altivec_maybe_transactional(current);
178         else
179                 giveup_altivec_notask();
180 #else
181         giveup_altivec_maybe_transactional(last_task_used_altivec);
182 #endif /* CONFIG_SMP */
183 }
184 EXPORT_SYMBOL(enable_kernel_altivec);
185 
186 /*
187  * Make sure the VMX/Altivec register state in the
188  * the thread_struct is up to date for task tsk.
189  */
190 void flush_altivec_to_thread(struct task_struct *tsk)
191 {
192         if (tsk->thread.regs) {
193                 preempt_disable();
194                 if (tsk->thread.regs->msr & MSR_VEC) {
195 #ifdef CONFIG_SMP
196                         BUG_ON(tsk != current);
197 #endif
198                         giveup_altivec_maybe_transactional(tsk);
199                 }
200                 preempt_enable();
201         }
202 }
203 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
204 #endif /* CONFIG_ALTIVEC */
205 
206 #ifdef CONFIG_VSX
207 #if 0
208 /* not currently used, but some crazy RAID module might want to later */
209 void enable_kernel_vsx(void)
210 {
211         WARN_ON(preemptible());
212 
213 #ifdef CONFIG_SMP
214         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
215                 giveup_vsx(current);
216         else
217                 giveup_vsx(NULL);       /* just enable vsx for kernel - force */
218 #else
219         giveup_vsx(last_task_used_vsx);
220 #endif /* CONFIG_SMP */
221 }
222 EXPORT_SYMBOL(enable_kernel_vsx);
223 #endif
224 
225 void giveup_vsx(struct task_struct *tsk)
226 {
227         giveup_fpu_maybe_transactional(tsk);
228         giveup_altivec_maybe_transactional(tsk);
229         __giveup_vsx(tsk);
230 }
231 EXPORT_SYMBOL(giveup_vsx);
232 
233 void flush_vsx_to_thread(struct task_struct *tsk)
234 {
235         if (tsk->thread.regs) {
236                 preempt_disable();
237                 if (tsk->thread.regs->msr & MSR_VSX) {
238 #ifdef CONFIG_SMP
239                         BUG_ON(tsk != current);
240 #endif
241                         giveup_vsx(tsk);
242                 }
243                 preempt_enable();
244         }
245 }
246 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
247 #endif /* CONFIG_VSX */
248 
249 #ifdef CONFIG_SPE
250 
251 void enable_kernel_spe(void)
252 {
253         WARN_ON(preemptible());
254 
255 #ifdef CONFIG_SMP
256         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
257                 giveup_spe(current);
258         else
259                 giveup_spe(NULL);       /* just enable SPE for kernel - force */
260 #else
261         giveup_spe(last_task_used_spe);
262 #endif /* __SMP __ */
263 }
264 EXPORT_SYMBOL(enable_kernel_spe);
265 
266 void flush_spe_to_thread(struct task_struct *tsk)
267 {
268         if (tsk->thread.regs) {
269                 preempt_disable();
270                 if (tsk->thread.regs->msr & MSR_SPE) {
271 #ifdef CONFIG_SMP
272                         BUG_ON(tsk != current);
273 #endif
274                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
275                         giveup_spe(tsk);
276                 }
277                 preempt_enable();
278         }
279 }
280 #endif /* CONFIG_SPE */
281 
282 #ifndef CONFIG_SMP
283 /*
284  * If we are doing lazy switching of CPU state (FP, altivec or SPE),
285  * and the current task has some state, discard it.
286  */
287 void discard_lazy_cpu_state(void)
288 {
289         preempt_disable();
290         if (last_task_used_math == current)
291                 last_task_used_math = NULL;
292 #ifdef CONFIG_ALTIVEC
293         if (last_task_used_altivec == current)
294                 last_task_used_altivec = NULL;
295 #endif /* CONFIG_ALTIVEC */
296 #ifdef CONFIG_VSX
297         if (last_task_used_vsx == current)
298                 last_task_used_vsx = NULL;
299 #endif /* CONFIG_VSX */
300 #ifdef CONFIG_SPE
301         if (last_task_used_spe == current)
302                 last_task_used_spe = NULL;
303 #endif
304         preempt_enable();
305 }
306 #endif /* CONFIG_SMP */
307 
308 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
309 void do_send_trap(struct pt_regs *regs, unsigned long address,
310                   unsigned long error_code, int signal_code, int breakpt)
311 {
312         siginfo_t info;
313 
314         current->thread.trap_nr = signal_code;
315         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
316                         11, SIGSEGV) == NOTIFY_STOP)
317                 return;
318 
319         /* Deliver the signal to userspace */
320         info.si_signo = SIGTRAP;
321         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
322         info.si_code = signal_code;
323         info.si_addr = (void __user *)address;
324         force_sig_info(SIGTRAP, &info, current);
325 }
326 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
327 void do_break (struct pt_regs *regs, unsigned long address,
328                     unsigned long error_code)
329 {
330         siginfo_t info;
331 
332         current->thread.trap_nr = TRAP_HWBKPT;
333         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
334                         11, SIGSEGV) == NOTIFY_STOP)
335                 return;
336 
337         if (debugger_break_match(regs))
338                 return;
339 
340         /* Clear the breakpoint */
341         hw_breakpoint_disable();
342 
343         /* Deliver the signal to userspace */
344         info.si_signo = SIGTRAP;
345         info.si_errno = 0;
346         info.si_code = TRAP_HWBKPT;
347         info.si_addr = (void __user *)address;
348         force_sig_info(SIGTRAP, &info, current);
349 }
350 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
351 
352 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
353 
354 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
355 /*
356  * Set the debug registers back to their default "safe" values.
357  */
358 static void set_debug_reg_defaults(struct thread_struct *thread)
359 {
360         thread->debug.iac1 = thread->debug.iac2 = 0;
361 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
362         thread->debug.iac3 = thread->debug.iac4 = 0;
363 #endif
364         thread->debug.dac1 = thread->debug.dac2 = 0;
365 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
366         thread->debug.dvc1 = thread->debug.dvc2 = 0;
367 #endif
368         thread->debug.dbcr0 = 0;
369 #ifdef CONFIG_BOOKE
370         /*
371          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
372          */
373         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
374                         DBCR1_IAC3US | DBCR1_IAC4US;
375         /*
376          * Force Data Address Compare User/Supervisor bits to be User-only
377          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
378          */
379         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
380 #else
381         thread->debug.dbcr1 = 0;
382 #endif
383 }
384 
385 static void prime_debug_regs(struct debug_reg *debug)
386 {
387         /*
388          * We could have inherited MSR_DE from userspace, since
389          * it doesn't get cleared on exception entry.  Make sure
390          * MSR_DE is clear before we enable any debug events.
391          */
392         mtmsr(mfmsr() & ~MSR_DE);
393 
394         mtspr(SPRN_IAC1, debug->iac1);
395         mtspr(SPRN_IAC2, debug->iac2);
396 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
397         mtspr(SPRN_IAC3, debug->iac3);
398         mtspr(SPRN_IAC4, debug->iac4);
399 #endif
400         mtspr(SPRN_DAC1, debug->dac1);
401         mtspr(SPRN_DAC2, debug->dac2);
402 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
403         mtspr(SPRN_DVC1, debug->dvc1);
404         mtspr(SPRN_DVC2, debug->dvc2);
405 #endif
406         mtspr(SPRN_DBCR0, debug->dbcr0);
407         mtspr(SPRN_DBCR1, debug->dbcr1);
408 #ifdef CONFIG_BOOKE
409         mtspr(SPRN_DBCR2, debug->dbcr2);
410 #endif
411 }
412 /*
413  * Unless neither the old or new thread are making use of the
414  * debug registers, set the debug registers from the values
415  * stored in the new thread.
416  */
417 void switch_booke_debug_regs(struct debug_reg *new_debug)
418 {
419         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
420                 || (new_debug->dbcr0 & DBCR0_IDM))
421                         prime_debug_regs(new_debug);
422 }
423 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
424 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
425 #ifndef CONFIG_HAVE_HW_BREAKPOINT
426 static void set_debug_reg_defaults(struct thread_struct *thread)
427 {
428         thread->hw_brk.address = 0;
429         thread->hw_brk.type = 0;
430         set_breakpoint(&thread->hw_brk);
431 }
432 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
433 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
434 
435 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
436 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
437 {
438         mtspr(SPRN_DAC1, dabr);
439 #ifdef CONFIG_PPC_47x
440         isync();
441 #endif
442         return 0;
443 }
444 #elif defined(CONFIG_PPC_BOOK3S)
445 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
446 {
447         mtspr(SPRN_DABR, dabr);
448         if (cpu_has_feature(CPU_FTR_DABRX))
449                 mtspr(SPRN_DABRX, dabrx);
450         return 0;
451 }
452 #else
453 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
454 {
455         return -EINVAL;
456 }
457 #endif
458 
459 static inline int set_dabr(struct arch_hw_breakpoint *brk)
460 {
461         unsigned long dabr, dabrx;
462 
463         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
464         dabrx = ((brk->type >> 3) & 0x7);
465 
466         if (ppc_md.set_dabr)
467                 return ppc_md.set_dabr(dabr, dabrx);
468 
469         return __set_dabr(dabr, dabrx);
470 }
471 
472 static inline int set_dawr(struct arch_hw_breakpoint *brk)
473 {
474         unsigned long dawr, dawrx, mrd;
475 
476         dawr = brk->address;
477 
478         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
479                                    << (63 - 58); //* read/write bits */
480         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
481                                    << (63 - 59); //* translate */
482         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
483                                    >> 3; //* PRIM bits */
484         /* dawr length is stored in field MDR bits 48:53.  Matches range in
485            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
486            0b111111=64DW.
487            brk->len is in bytes.
488            This aligns up to double word size, shifts and does the bias.
489         */
490         mrd = ((brk->len + 7) >> 3) - 1;
491         dawrx |= (mrd & 0x3f) << (63 - 53);
492 
493         if (ppc_md.set_dawr)
494                 return ppc_md.set_dawr(dawr, dawrx);
495         mtspr(SPRN_DAWR, dawr);
496         mtspr(SPRN_DAWRX, dawrx);
497         return 0;
498 }
499 
500 void __set_breakpoint(struct arch_hw_breakpoint *brk)
501 {
502         __get_cpu_var(current_brk) = *brk;
503 
504         if (cpu_has_feature(CPU_FTR_DAWR))
505                 set_dawr(brk);
506         else
507                 set_dabr(brk);
508 }
509 
510 void set_breakpoint(struct arch_hw_breakpoint *brk)
511 {
512         preempt_disable();
513         __set_breakpoint(brk);
514         preempt_enable();
515 }
516 
517 #ifdef CONFIG_PPC64
518 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
519 #endif
520 
521 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
522                               struct arch_hw_breakpoint *b)
523 {
524         if (a->address != b->address)
525                 return false;
526         if (a->type != b->type)
527                 return false;
528         if (a->len != b->len)
529                 return false;
530         return true;
531 }
532 
533 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
534 static void tm_reclaim_thread(struct thread_struct *thr,
535                               struct thread_info *ti, uint8_t cause)
536 {
537         unsigned long msr_diff = 0;
538 
539         /*
540          * If FP/VSX registers have been already saved to the
541          * thread_struct, move them to the transact_fp array.
542          * We clear the TIF_RESTORE_TM bit since after the reclaim
543          * the thread will no longer be transactional.
544          */
545         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
546                 msr_diff = thr->tm_orig_msr & ~thr->regs->msr;
547                 if (msr_diff & MSR_FP)
548                         memcpy(&thr->transact_fp, &thr->fp_state,
549                                sizeof(struct thread_fp_state));
550                 if (msr_diff & MSR_VEC)
551                         memcpy(&thr->transact_vr, &thr->vr_state,
552                                sizeof(struct thread_vr_state));
553                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
554                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
555         }
556 
557         tm_reclaim(thr, thr->regs->msr, cause);
558 
559         /* Having done the reclaim, we now have the checkpointed
560          * FP/VSX values in the registers.  These might be valid
561          * even if we have previously called enable_kernel_fp() or
562          * flush_fp_to_thread(), so update thr->regs->msr to
563          * indicate their current validity.
564          */
565         thr->regs->msr |= msr_diff;
566 }
567 
568 void tm_reclaim_current(uint8_t cause)
569 {
570         tm_enable();
571         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
572 }
573 
574 static inline void tm_reclaim_task(struct task_struct *tsk)
575 {
576         /* We have to work out if we're switching from/to a task that's in the
577          * middle of a transaction.
578          *
579          * In switching we need to maintain a 2nd register state as
580          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
581          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
582          * (current) FPRs into oldtask->thread.transact_fpr[].
583          *
584          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
585          */
586         struct thread_struct *thr = &tsk->thread;
587 
588         if (!thr->regs)
589                 return;
590 
591         if (!MSR_TM_ACTIVE(thr->regs->msr))
592                 goto out_and_saveregs;
593 
594         /* Stash the original thread MSR, as giveup_fpu et al will
595          * modify it.  We hold onto it to see whether the task used
596          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
597          * tm_orig_msr is already set.
598          */
599         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
600                 thr->tm_orig_msr = thr->regs->msr;
601 
602         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
603                  "ccr=%lx, msr=%lx, trap=%lx)\n",
604                  tsk->pid, thr->regs->nip,
605                  thr->regs->ccr, thr->regs->msr,
606                  thr->regs->trap);
607 
608         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
609 
610         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
611                  tsk->pid);
612 
613 out_and_saveregs:
614         /* Always save the regs here, even if a transaction's not active.
615          * This context-switches a thread's TM info SPRs.  We do it here to
616          * be consistent with the restore path (in recheckpoint) which
617          * cannot happen later in _switch().
618          */
619         tm_save_sprs(thr);
620 }
621 
622 extern void __tm_recheckpoint(struct thread_struct *thread,
623                               unsigned long orig_msr);
624 
625 void tm_recheckpoint(struct thread_struct *thread,
626                      unsigned long orig_msr)
627 {
628         unsigned long flags;
629 
630         /* We really can't be interrupted here as the TEXASR registers can't
631          * change and later in the trecheckpoint code, we have a userspace R1.
632          * So let's hard disable over this region.
633          */
634         local_irq_save(flags);
635         hard_irq_disable();
636 
637         /* The TM SPRs are restored here, so that TEXASR.FS can be set
638          * before the trecheckpoint and no explosion occurs.
639          */
640         tm_restore_sprs(thread);
641 
642         __tm_recheckpoint(thread, orig_msr);
643 
644         local_irq_restore(flags);
645 }
646 
647 static inline void tm_recheckpoint_new_task(struct task_struct *new)
648 {
649         unsigned long msr;
650 
651         if (!cpu_has_feature(CPU_FTR_TM))
652                 return;
653 
654         /* Recheckpoint the registers of the thread we're about to switch to.
655          *
656          * If the task was using FP, we non-lazily reload both the original and
657          * the speculative FP register states.  This is because the kernel
658          * doesn't see if/when a TM rollback occurs, so if we take an FP
659          * unavoidable later, we are unable to determine which set of FP regs
660          * need to be restored.
661          */
662         if (!new->thread.regs)
663                 return;
664 
665         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
666                 tm_restore_sprs(&new->thread);
667                 return;
668         }
669         msr = new->thread.tm_orig_msr;
670         /* Recheckpoint to restore original checkpointed register state. */
671         TM_DEBUG("*** tm_recheckpoint of pid %d "
672                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
673                  new->pid, new->thread.regs->msr, msr);
674 
675         /* This loads the checkpointed FP/VEC state, if used */
676         tm_recheckpoint(&new->thread, msr);
677 
678         /* This loads the speculative FP/VEC state, if used */
679         if (msr & MSR_FP) {
680                 do_load_up_transact_fpu(&new->thread);
681                 new->thread.regs->msr |=
682                         (MSR_FP | new->thread.fpexc_mode);
683         }
684 #ifdef CONFIG_ALTIVEC
685         if (msr & MSR_VEC) {
686                 do_load_up_transact_altivec(&new->thread);
687                 new->thread.regs->msr |= MSR_VEC;
688         }
689 #endif
690         /* We may as well turn on VSX too since all the state is restored now */
691         if (msr & MSR_VSX)
692                 new->thread.regs->msr |= MSR_VSX;
693 
694         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
695                  "(kernel msr 0x%lx)\n",
696                  new->pid, mfmsr());
697 }
698 
699 static inline void __switch_to_tm(struct task_struct *prev)
700 {
701         if (cpu_has_feature(CPU_FTR_TM)) {
702                 tm_enable();
703                 tm_reclaim_task(prev);
704         }
705 }
706 
707 /*
708  * This is called if we are on the way out to userspace and the
709  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
710  * FP and/or vector state and does so if necessary.
711  * If userspace is inside a transaction (whether active or
712  * suspended) and FP/VMX/VSX instructions have ever been enabled
713  * inside that transaction, then we have to keep them enabled
714  * and keep the FP/VMX/VSX state loaded while ever the transaction
715  * continues.  The reason is that if we didn't, and subsequently
716  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
717  * we don't know whether it's the same transaction, and thus we
718  * don't know which of the checkpointed state and the transactional
719  * state to use.
720  */
721 void restore_tm_state(struct pt_regs *regs)
722 {
723         unsigned long msr_diff;
724 
725         clear_thread_flag(TIF_RESTORE_TM);
726         if (!MSR_TM_ACTIVE(regs->msr))
727                 return;
728 
729         msr_diff = current->thread.tm_orig_msr & ~regs->msr;
730         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
731         if (msr_diff & MSR_FP) {
732                 fp_enable();
733                 load_fp_state(&current->thread.fp_state);
734                 regs->msr |= current->thread.fpexc_mode;
735         }
736         if (msr_diff & MSR_VEC) {
737                 vec_enable();
738                 load_vr_state(&current->thread.vr_state);
739         }
740         regs->msr |= msr_diff;
741 }
742 
743 #else
744 #define tm_recheckpoint_new_task(new)
745 #define __switch_to_tm(prev)
746 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
747 
748 struct task_struct *__switch_to(struct task_struct *prev,
749         struct task_struct *new)
750 {
751         struct thread_struct *new_thread, *old_thread;
752         struct task_struct *last;
753 #ifdef CONFIG_PPC_BOOK3S_64
754         struct ppc64_tlb_batch *batch;
755 #endif
756 
757         WARN_ON(!irqs_disabled());
758 
759         /* Back up the TAR and DSCR across context switches.
760          * Note that the TAR is not available for use in the kernel.  (To
761          * provide this, the TAR should be backed up/restored on exception
762          * entry/exit instead, and be in pt_regs.  FIXME, this should be in
763          * pt_regs anyway (for debug).)
764          * Save the TAR and DSCR here before we do treclaim/trecheckpoint as
765          * these will change them.
766          */
767         save_early_sprs(&prev->thread);
768 
769         __switch_to_tm(prev);
770 
771 #ifdef CONFIG_SMP
772         /* avoid complexity of lazy save/restore of fpu
773          * by just saving it every time we switch out if
774          * this task used the fpu during the last quantum.
775          *
776          * If it tries to use the fpu again, it'll trap and
777          * reload its fp regs.  So we don't have to do a restore
778          * every switch, just a save.
779          *  -- Cort
780          */
781         if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
782                 giveup_fpu(prev);
783 #ifdef CONFIG_ALTIVEC
784         /*
785          * If the previous thread used altivec in the last quantum
786          * (thus changing altivec regs) then save them.
787          * We used to check the VRSAVE register but not all apps
788          * set it, so we don't rely on it now (and in fact we need
789          * to save & restore VSCR even if VRSAVE == 0).  -- paulus
790          *
791          * On SMP we always save/restore altivec regs just to avoid the
792          * complexity of changing processors.
793          *  -- Cort
794          */
795         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
796                 giveup_altivec(prev);
797 #endif /* CONFIG_ALTIVEC */
798 #ifdef CONFIG_VSX
799         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
800                 /* VMX and FPU registers are already save here */
801                 __giveup_vsx(prev);
802 #endif /* CONFIG_VSX */
803 #ifdef CONFIG_SPE
804         /*
805          * If the previous thread used spe in the last quantum
806          * (thus changing spe regs) then save them.
807          *
808          * On SMP we always save/restore spe regs just to avoid the
809          * complexity of changing processors.
810          */
811         if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
812                 giveup_spe(prev);
813 #endif /* CONFIG_SPE */
814 
815 #else  /* CONFIG_SMP */
816 #ifdef CONFIG_ALTIVEC
817         /* Avoid the trap.  On smp this this never happens since
818          * we don't set last_task_used_altivec -- Cort
819          */
820         if (new->thread.regs && last_task_used_altivec == new)
821                 new->thread.regs->msr |= MSR_VEC;
822 #endif /* CONFIG_ALTIVEC */
823 #ifdef CONFIG_VSX
824         if (new->thread.regs && last_task_used_vsx == new)
825                 new->thread.regs->msr |= MSR_VSX;
826 #endif /* CONFIG_VSX */
827 #ifdef CONFIG_SPE
828         /* Avoid the trap.  On smp this this never happens since
829          * we don't set last_task_used_spe
830          */
831         if (new->thread.regs && last_task_used_spe == new)
832                 new->thread.regs->msr |= MSR_SPE;
833 #endif /* CONFIG_SPE */
834 
835 #endif /* CONFIG_SMP */
836 
837 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
838         switch_booke_debug_regs(&new->thread.debug);
839 #else
840 /*
841  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
842  * schedule DABR
843  */
844 #ifndef CONFIG_HAVE_HW_BREAKPOINT
845         if (unlikely(!hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
846                 __set_breakpoint(&new->thread.hw_brk);
847 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
848 #endif
849 
850 
851         new_thread = &new->thread;
852         old_thread = &current->thread;
853 
854 #ifdef CONFIG_PPC64
855         /*
856          * Collect processor utilization data per process
857          */
858         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
859                 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
860                 long unsigned start_tb, current_tb;
861                 start_tb = old_thread->start_tb;
862                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
863                 old_thread->accum_tb += (current_tb - start_tb);
864                 new_thread->start_tb = current_tb;
865         }
866 #endif /* CONFIG_PPC64 */
867 
868 #ifdef CONFIG_PPC_BOOK3S_64
869         batch = &__get_cpu_var(ppc64_tlb_batch);
870         if (batch->active) {
871                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
872                 if (batch->index)
873                         __flush_tlb_pending(batch);
874                 batch->active = 0;
875         }
876 #endif /* CONFIG_PPC_BOOK3S_64 */
877 
878         /*
879          * We can't take a PMU exception inside _switch() since there is a
880          * window where the kernel stack SLB and the kernel stack are out
881          * of sync. Hard disable here.
882          */
883         hard_irq_disable();
884 
885         tm_recheckpoint_new_task(new);
886 
887         last = _switch(old_thread, new_thread);
888 
889 #ifdef CONFIG_PPC_BOOK3S_64
890         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
891                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
892                 batch = &__get_cpu_var(ppc64_tlb_batch);
893                 batch->active = 1;
894         }
895 #endif /* CONFIG_PPC_BOOK3S_64 */
896 
897         return last;
898 }
899 
900 static int instructions_to_print = 16;
901 
902 static void show_instructions(struct pt_regs *regs)
903 {
904         int i;
905         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
906                         sizeof(int));
907 
908         printk("Instruction dump:");
909 
910         for (i = 0; i < instructions_to_print; i++) {
911                 int instr;
912 
913                 if (!(i % 8))
914                         printk("\n");
915 
916 #if !defined(CONFIG_BOOKE)
917                 /* If executing with the IMMU off, adjust pc rather
918                  * than print XXXXXXXX.
919                  */
920                 if (!(regs->msr & MSR_IR))
921                         pc = (unsigned long)phys_to_virt(pc);
922 #endif
923 
924                 /* We use __get_user here *only* to avoid an OOPS on a
925                  * bad address because the pc *should* only be a
926                  * kernel address.
927                  */
928                 if (!__kernel_text_address(pc) ||
929                      __get_user(instr, (unsigned int __user *)pc)) {
930                         printk(KERN_CONT "XXXXXXXX ");
931                 } else {
932                         if (regs->nip == pc)
933                                 printk(KERN_CONT "<%08x> ", instr);
934                         else
935                                 printk(KERN_CONT "%08x ", instr);
936                 }
937 
938                 pc += sizeof(int);
939         }
940 
941         printk("\n");
942 }
943 
944 static struct regbit {
945         unsigned long bit;
946         const char *name;
947 } msr_bits[] = {
948 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
949         {MSR_SF,        "SF"},
950         {MSR_HV,        "HV"},
951 #endif
952         {MSR_VEC,       "VEC"},
953         {MSR_VSX,       "VSX"},
954 #ifdef CONFIG_BOOKE
955         {MSR_CE,        "CE"},
956 #endif
957         {MSR_EE,        "EE"},
958         {MSR_PR,        "PR"},
959         {MSR_FP,        "FP"},
960         {MSR_ME,        "ME"},
961 #ifdef CONFIG_BOOKE
962         {MSR_DE,        "DE"},
963 #else
964         {MSR_SE,        "SE"},
965         {MSR_BE,        "BE"},
966 #endif
967         {MSR_IR,        "IR"},
968         {MSR_DR,        "DR"},
969         {MSR_PMM,       "PMM"},
970 #ifndef CONFIG_BOOKE
971         {MSR_RI,        "RI"},
972         {MSR_LE,        "LE"},
973 #endif
974         {0,             NULL}
975 };
976 
977 static void printbits(unsigned long val, struct regbit *bits)
978 {
979         const char *sep = "";
980 
981         printk("<");
982         for (; bits->bit; ++bits)
983                 if (val & bits->bit) {
984                         printk("%s%s", sep, bits->name);
985                         sep = ",";
986                 }
987         printk(">");
988 }
989 
990 #ifdef CONFIG_PPC64
991 #define REG             "%016lx"
992 #define REGS_PER_LINE   4
993 #define LAST_VOLATILE   13
994 #else
995 #define REG             "%08lx"
996 #define REGS_PER_LINE   8
997 #define LAST_VOLATILE   12
998 #endif
999 
1000 void show_regs(struct pt_regs * regs)
1001 {
1002         int i, trap;
1003 
1004         show_regs_print_info(KERN_DEFAULT);
1005 
1006         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1007                regs->nip, regs->link, regs->ctr);
1008         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1009                regs, regs->trap, print_tainted(), init_utsname()->release);
1010         printk("MSR: "REG" ", regs->msr);
1011         printbits(regs->msr, msr_bits);
1012         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1013         trap = TRAP(regs);
1014         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1015                 printk("CFAR: "REG" ", regs->orig_gpr3);
1016         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1017 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1018                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1019 #else
1020                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1021 #endif
1022 #ifdef CONFIG_PPC64
1023         printk("SOFTE: %ld ", regs->softe);
1024 #endif
1025 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1026         if (MSR_TM_ACTIVE(regs->msr))
1027                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1028 #endif
1029 
1030         for (i = 0;  i < 32;  i++) {
1031                 if ((i % REGS_PER_LINE) == 0)
1032                         printk("\nGPR%02d: ", i);
1033                 printk(REG " ", regs->gpr[i]);
1034                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1035                         break;
1036         }
1037         printk("\n");
1038 #ifdef CONFIG_KALLSYMS
1039         /*
1040          * Lookup NIP late so we have the best change of getting the
1041          * above info out without failing
1042          */
1043         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1044         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1045 #endif
1046         show_stack(current, (unsigned long *) regs->gpr[1]);
1047         if (!user_mode(regs))
1048                 show_instructions(regs);
1049 }
1050 
1051 void exit_thread(void)
1052 {
1053         discard_lazy_cpu_state();
1054 }
1055 
1056 void flush_thread(void)
1057 {
1058         discard_lazy_cpu_state();
1059 
1060 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1061         flush_ptrace_hw_breakpoint(current);
1062 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1063         set_debug_reg_defaults(&current->thread);
1064 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1065 }
1066 
1067 void
1068 release_thread(struct task_struct *t)
1069 {
1070 }
1071 
1072 /*
1073  * this gets called so that we can store coprocessor state into memory and
1074  * copy the current task into the new thread.
1075  */
1076 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1077 {
1078         flush_fp_to_thread(src);
1079         flush_altivec_to_thread(src);
1080         flush_vsx_to_thread(src);
1081         flush_spe_to_thread(src);
1082         /*
1083          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1084          * flush but it removes the checkpointed state from the current CPU and
1085          * transitions the CPU out of TM mode.  Hence we need to call
1086          * tm_recheckpoint_new_task() (on the same task) to restore the
1087          * checkpointed state back and the TM mode.
1088          */
1089         __switch_to_tm(src);
1090         tm_recheckpoint_new_task(src);
1091 
1092         *dst = *src;
1093 
1094         clear_task_ebb(dst);
1095 
1096         return 0;
1097 }
1098 
1099 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1100 {
1101 #ifdef CONFIG_PPC_STD_MMU_64
1102         unsigned long sp_vsid;
1103         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1104 
1105         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1106                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1107                         << SLB_VSID_SHIFT_1T;
1108         else
1109                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1110                         << SLB_VSID_SHIFT;
1111         sp_vsid |= SLB_VSID_KERNEL | llp;
1112         p->thread.ksp_vsid = sp_vsid;
1113 #endif
1114 }
1115 
1116 /*
1117  * Copy a thread..
1118  */
1119 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
1120 
1121 int copy_thread(unsigned long clone_flags, unsigned long usp,
1122                 unsigned long arg, struct task_struct *p)
1123 {
1124         struct pt_regs *childregs, *kregs;
1125         extern void ret_from_fork(void);
1126         extern void ret_from_kernel_thread(void);
1127         void (*f)(void);
1128         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1129 
1130         /* Copy registers */
1131         sp -= sizeof(struct pt_regs);
1132         childregs = (struct pt_regs *) sp;
1133         if (unlikely(p->flags & PF_KTHREAD)) {
1134                 struct thread_info *ti = (void *)task_stack_page(p);
1135                 memset(childregs, 0, sizeof(struct pt_regs));
1136                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1137                 /* function */
1138                 if (usp)
1139                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1140 #ifdef CONFIG_PPC64
1141                 clear_tsk_thread_flag(p, TIF_32BIT);
1142                 childregs->softe = 1;
1143 #endif
1144                 childregs->gpr[15] = arg;
1145                 p->thread.regs = NULL;  /* no user register state */
1146                 ti->flags |= _TIF_RESTOREALL;
1147                 f = ret_from_kernel_thread;
1148         } else {
1149                 struct pt_regs *regs = current_pt_regs();
1150                 CHECK_FULL_REGS(regs);
1151                 *childregs = *regs;
1152                 if (usp)
1153                         childregs->gpr[1] = usp;
1154                 p->thread.regs = childregs;
1155                 childregs->gpr[3] = 0;  /* Result from fork() */
1156                 if (clone_flags & CLONE_SETTLS) {
1157 #ifdef CONFIG_PPC64
1158                         if (!is_32bit_task())
1159                                 childregs->gpr[13] = childregs->gpr[6];
1160                         else
1161 #endif
1162                                 childregs->gpr[2] = childregs->gpr[6];
1163                 }
1164 
1165                 f = ret_from_fork;
1166         }
1167         sp -= STACK_FRAME_OVERHEAD;
1168 
1169         /*
1170          * The way this works is that at some point in the future
1171          * some task will call _switch to switch to the new task.
1172          * That will pop off the stack frame created below and start
1173          * the new task running at ret_from_fork.  The new task will
1174          * do some house keeping and then return from the fork or clone
1175          * system call, using the stack frame created above.
1176          */
1177         ((unsigned long *)sp)[0] = 0;
1178         sp -= sizeof(struct pt_regs);
1179         kregs = (struct pt_regs *) sp;
1180         sp -= STACK_FRAME_OVERHEAD;
1181         p->thread.ksp = sp;
1182 #ifdef CONFIG_PPC32
1183         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1184                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1185 #endif
1186 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1187         p->thread.ptrace_bps[0] = NULL;
1188 #endif
1189 
1190         p->thread.fp_save_area = NULL;
1191 #ifdef CONFIG_ALTIVEC
1192         p->thread.vr_save_area = NULL;
1193 #endif
1194 
1195         setup_ksp_vsid(p, sp);
1196 
1197 #ifdef CONFIG_PPC64 
1198         if (cpu_has_feature(CPU_FTR_DSCR)) {
1199                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1200                 p->thread.dscr = current->thread.dscr;
1201         }
1202         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1203                 p->thread.ppr = INIT_PPR;
1204 #endif
1205         kregs->nip = ppc_function_entry(f);
1206         return 0;
1207 }
1208 
1209 /*
1210  * Set up a thread for executing a new program
1211  */
1212 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1213 {
1214 #ifdef CONFIG_PPC64
1215         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1216 #endif
1217 
1218         /*
1219          * If we exec out of a kernel thread then thread.regs will not be
1220          * set.  Do it now.
1221          */
1222         if (!current->thread.regs) {
1223                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1224                 current->thread.regs = regs - 1;
1225         }
1226 
1227 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1228         /*
1229          * Clear any transactional state, we're exec()ing. The cause is
1230          * not important as there will never be a recheckpoint so it's not
1231          * user visible.
1232          */
1233         if (MSR_TM_SUSPENDED(mfmsr()))
1234                 tm_reclaim_current(0);
1235 #endif
1236 
1237         memset(regs->gpr, 0, sizeof(regs->gpr));
1238         regs->ctr = 0;
1239         regs->link = 0;
1240         regs->xer = 0;
1241         regs->ccr = 0;
1242         regs->gpr[1] = sp;
1243 
1244         /*
1245          * We have just cleared all the nonvolatile GPRs, so make
1246          * FULL_REGS(regs) return true.  This is necessary to allow
1247          * ptrace to examine the thread immediately after exec.
1248          */
1249         regs->trap &= ~1UL;
1250 
1251 #ifdef CONFIG_PPC32
1252         regs->mq = 0;
1253         regs->nip = start;
1254         regs->msr = MSR_USER;
1255 #else
1256         if (!is_32bit_task()) {
1257                 unsigned long entry;
1258 
1259                 if (is_elf2_task()) {
1260                         /* Look ma, no function descriptors! */
1261                         entry = start;
1262 
1263                         /*
1264                          * Ulrich says:
1265                          *   The latest iteration of the ABI requires that when
1266                          *   calling a function (at its global entry point),
1267                          *   the caller must ensure r12 holds the entry point
1268                          *   address (so that the function can quickly
1269                          *   establish addressability).
1270                          */
1271                         regs->gpr[12] = start;
1272                         /* Make sure that's restored on entry to userspace. */
1273                         set_thread_flag(TIF_RESTOREALL);
1274                 } else {
1275                         unsigned long toc;
1276 
1277                         /* start is a relocated pointer to the function
1278                          * descriptor for the elf _start routine.  The first
1279                          * entry in the function descriptor is the entry
1280                          * address of _start and the second entry is the TOC
1281                          * value we need to use.
1282                          */
1283                         __get_user(entry, (unsigned long __user *)start);
1284                         __get_user(toc, (unsigned long __user *)start+1);
1285 
1286                         /* Check whether the e_entry function descriptor entries
1287                          * need to be relocated before we can use them.
1288                          */
1289                         if (load_addr != 0) {
1290                                 entry += load_addr;
1291                                 toc   += load_addr;
1292                         }
1293                         regs->gpr[2] = toc;
1294                 }
1295                 regs->nip = entry;
1296                 regs->msr = MSR_USER64;
1297         } else {
1298                 regs->nip = start;
1299                 regs->gpr[2] = 0;
1300                 regs->msr = MSR_USER32;
1301         }
1302 #endif
1303         discard_lazy_cpu_state();
1304 #ifdef CONFIG_VSX
1305         current->thread.used_vsr = 0;
1306 #endif
1307         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1308         current->thread.fp_save_area = NULL;
1309 #ifdef CONFIG_ALTIVEC
1310         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1311         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1312         current->thread.vr_save_area = NULL;
1313         current->thread.vrsave = 0;
1314         current->thread.used_vr = 0;
1315 #endif /* CONFIG_ALTIVEC */
1316 #ifdef CONFIG_SPE
1317         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1318         current->thread.acc = 0;
1319         current->thread.spefscr = 0;
1320         current->thread.used_spe = 0;
1321 #endif /* CONFIG_SPE */
1322 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1323         if (cpu_has_feature(CPU_FTR_TM))
1324                 regs->msr |= MSR_TM;
1325         current->thread.tm_tfhar = 0;
1326         current->thread.tm_texasr = 0;
1327         current->thread.tm_tfiar = 0;
1328 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1329 }
1330 EXPORT_SYMBOL(start_thread);
1331 
1332 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1333                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1334 
1335 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1336 {
1337         struct pt_regs *regs = tsk->thread.regs;
1338 
1339         /* This is a bit hairy.  If we are an SPE enabled  processor
1340          * (have embedded fp) we store the IEEE exception enable flags in
1341          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1342          * mode (asyn, precise, disabled) for 'Classic' FP. */
1343         if (val & PR_FP_EXC_SW_ENABLE) {
1344 #ifdef CONFIG_SPE
1345                 if (cpu_has_feature(CPU_FTR_SPE)) {
1346                         /*
1347                          * When the sticky exception bits are set
1348                          * directly by userspace, it must call prctl
1349                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1350                          * in the existing prctl settings) or
1351                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1352                          * the bits being set).  <fenv.h> functions
1353                          * saving and restoring the whole
1354                          * floating-point environment need to do so
1355                          * anyway to restore the prctl settings from
1356                          * the saved environment.
1357                          */
1358                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1359                         tsk->thread.fpexc_mode = val &
1360                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1361                         return 0;
1362                 } else {
1363                         return -EINVAL;
1364                 }
1365 #else
1366                 return -EINVAL;
1367 #endif
1368         }
1369 
1370         /* on a CONFIG_SPE this does not hurt us.  The bits that
1371          * __pack_fe01 use do not overlap with bits used for
1372          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1373          * on CONFIG_SPE implementations are reserved so writing to
1374          * them does not change anything */
1375         if (val > PR_FP_EXC_PRECISE)
1376                 return -EINVAL;
1377         tsk->thread.fpexc_mode = __pack_fe01(val);
1378         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1379                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1380                         | tsk->thread.fpexc_mode;
1381         return 0;
1382 }
1383 
1384 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1385 {
1386         unsigned int val;
1387 
1388         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1389 #ifdef CONFIG_SPE
1390                 if (cpu_has_feature(CPU_FTR_SPE)) {
1391                         /*
1392                          * When the sticky exception bits are set
1393                          * directly by userspace, it must call prctl
1394                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1395                          * in the existing prctl settings) or
1396                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1397                          * the bits being set).  <fenv.h> functions
1398                          * saving and restoring the whole
1399                          * floating-point environment need to do so
1400                          * anyway to restore the prctl settings from
1401                          * the saved environment.
1402                          */
1403                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1404                         val = tsk->thread.fpexc_mode;
1405                 } else
1406                         return -EINVAL;
1407 #else
1408                 return -EINVAL;
1409 #endif
1410         else
1411                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1412         return put_user(val, (unsigned int __user *) adr);
1413 }
1414 
1415 int set_endian(struct task_struct *tsk, unsigned int val)
1416 {
1417         struct pt_regs *regs = tsk->thread.regs;
1418 
1419         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1420             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1421                 return -EINVAL;
1422 
1423         if (regs == NULL)
1424                 return -EINVAL;
1425 
1426         if (val == PR_ENDIAN_BIG)
1427                 regs->msr &= ~MSR_LE;
1428         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1429                 regs->msr |= MSR_LE;
1430         else
1431                 return -EINVAL;
1432 
1433         return 0;
1434 }
1435 
1436 int get_endian(struct task_struct *tsk, unsigned long adr)
1437 {
1438         struct pt_regs *regs = tsk->thread.regs;
1439         unsigned int val;
1440 
1441         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1442             !cpu_has_feature(CPU_FTR_REAL_LE))
1443                 return -EINVAL;
1444 
1445         if (regs == NULL)
1446                 return -EINVAL;
1447 
1448         if (regs->msr & MSR_LE) {
1449                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1450                         val = PR_ENDIAN_LITTLE;
1451                 else
1452                         val = PR_ENDIAN_PPC_LITTLE;
1453         } else
1454                 val = PR_ENDIAN_BIG;
1455 
1456         return put_user(val, (unsigned int __user *)adr);
1457 }
1458 
1459 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1460 {
1461         tsk->thread.align_ctl = val;
1462         return 0;
1463 }
1464 
1465 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1466 {
1467         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1468 }
1469 
1470 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1471                                   unsigned long nbytes)
1472 {
1473         unsigned long stack_page;
1474         unsigned long cpu = task_cpu(p);
1475 
1476         /*
1477          * Avoid crashing if the stack has overflowed and corrupted
1478          * task_cpu(p), which is in the thread_info struct.
1479          */
1480         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1481                 stack_page = (unsigned long) hardirq_ctx[cpu];
1482                 if (sp >= stack_page + sizeof(struct thread_struct)
1483                     && sp <= stack_page + THREAD_SIZE - nbytes)
1484                         return 1;
1485 
1486                 stack_page = (unsigned long) softirq_ctx[cpu];
1487                 if (sp >= stack_page + sizeof(struct thread_struct)
1488                     && sp <= stack_page + THREAD_SIZE - nbytes)
1489                         return 1;
1490         }
1491         return 0;
1492 }
1493 
1494 int validate_sp(unsigned long sp, struct task_struct *p,
1495                        unsigned long nbytes)
1496 {
1497         unsigned long stack_page = (unsigned long)task_stack_page(p);
1498 
1499         if (sp >= stack_page + sizeof(struct thread_struct)
1500             && sp <= stack_page + THREAD_SIZE - nbytes)
1501                 return 1;
1502 
1503         return valid_irq_stack(sp, p, nbytes);
1504 }
1505 
1506 EXPORT_SYMBOL(validate_sp);
1507 
1508 unsigned long get_wchan(struct task_struct *p)
1509 {
1510         unsigned long ip, sp;
1511         int count = 0;
1512 
1513         if (!p || p == current || p->state == TASK_RUNNING)
1514                 return 0;
1515 
1516         sp = p->thread.ksp;
1517         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1518                 return 0;
1519 
1520         do {
1521                 sp = *(unsigned long *)sp;
1522                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1523                         return 0;
1524                 if (count > 0) {
1525                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1526                         if (!in_sched_functions(ip))
1527                                 return ip;
1528                 }
1529         } while (count++ < 16);
1530         return 0;
1531 }
1532 
1533 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1534 
1535 void show_stack(struct task_struct *tsk, unsigned long *stack)
1536 {
1537         unsigned long sp, ip, lr, newsp;
1538         int count = 0;
1539         int firstframe = 1;
1540 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1541         int curr_frame = current->curr_ret_stack;
1542         extern void return_to_handler(void);
1543         unsigned long rth = (unsigned long)return_to_handler;
1544         unsigned long mrth = -1;
1545 #ifdef CONFIG_PPC64
1546         extern void mod_return_to_handler(void);
1547         rth = *(unsigned long *)rth;
1548         mrth = (unsigned long)mod_return_to_handler;
1549         mrth = *(unsigned long *)mrth;
1550 #endif
1551 #endif
1552 
1553         sp = (unsigned long) stack;
1554         if (tsk == NULL)
1555                 tsk = current;
1556         if (sp == 0) {
1557                 if (tsk == current)
1558                         sp = current_stack_pointer();
1559                 else
1560                         sp = tsk->thread.ksp;
1561         }
1562 
1563         lr = 0;
1564         printk("Call Trace:\n");
1565         do {
1566                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1567                         return;
1568 
1569                 stack = (unsigned long *) sp;
1570                 newsp = stack[0];
1571                 ip = stack[STACK_FRAME_LR_SAVE];
1572                 if (!firstframe || ip != lr) {
1573                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1574 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1575                         if ((ip == rth || ip == mrth) && curr_frame >= 0) {
1576                                 printk(" (%pS)",
1577                                        (void *)current->ret_stack[curr_frame].ret);
1578                                 curr_frame--;
1579                         }
1580 #endif
1581                         if (firstframe)
1582                                 printk(" (unreliable)");
1583                         printk("\n");
1584                 }
1585                 firstframe = 0;
1586 
1587                 /*
1588                  * See if this is an exception frame.
1589                  * We look for the "regshere" marker in the current frame.
1590                  */
1591                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1592                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1593                         struct pt_regs *regs = (struct pt_regs *)
1594                                 (sp + STACK_FRAME_OVERHEAD);
1595                         lr = regs->link;
1596                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1597                                regs->trap, (void *)regs->nip, (void *)lr);
1598                         firstframe = 1;
1599                 }
1600 
1601                 sp = newsp;
1602         } while (count++ < kstack_depth_to_print);
1603 }
1604 
1605 #ifdef CONFIG_PPC64
1606 /* Called with hard IRQs off */
1607 void notrace __ppc64_runlatch_on(void)
1608 {
1609         struct thread_info *ti = current_thread_info();
1610         unsigned long ctrl;
1611 
1612         ctrl = mfspr(SPRN_CTRLF);
1613         ctrl |= CTRL_RUNLATCH;
1614         mtspr(SPRN_CTRLT, ctrl);
1615 
1616         ti->local_flags |= _TLF_RUNLATCH;
1617 }
1618 
1619 /* Called with hard IRQs off */
1620 void notrace __ppc64_runlatch_off(void)
1621 {
1622         struct thread_info *ti = current_thread_info();
1623         unsigned long ctrl;
1624 
1625         ti->local_flags &= ~_TLF_RUNLATCH;
1626 
1627         ctrl = mfspr(SPRN_CTRLF);
1628         ctrl &= ~CTRL_RUNLATCH;
1629         mtspr(SPRN_CTRLT, ctrl);
1630 }
1631 #endif /* CONFIG_PPC64 */
1632 
1633 unsigned long arch_align_stack(unsigned long sp)
1634 {
1635         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1636                 sp -= get_random_int() & ~PAGE_MASK;
1637         return sp & ~0xf;
1638 }
1639 
1640 static inline unsigned long brk_rnd(void)
1641 {
1642         unsigned long rnd = 0;
1643 
1644         /* 8MB for 32bit, 1GB for 64bit */
1645         if (is_32bit_task())
1646                 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1647         else
1648                 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1649 
1650         return rnd << PAGE_SHIFT;
1651 }
1652 
1653 unsigned long arch_randomize_brk(struct mm_struct *mm)
1654 {
1655         unsigned long base = mm->brk;
1656         unsigned long ret;
1657 
1658 #ifdef CONFIG_PPC_STD_MMU_64
1659         /*
1660          * If we are using 1TB segments and we are allowed to randomise
1661          * the heap, we can put it above 1TB so it is backed by a 1TB
1662          * segment. Otherwise the heap will be in the bottom 1TB
1663          * which always uses 256MB segments and this may result in a
1664          * performance penalty.
1665          */
1666         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1667                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1668 #endif
1669 
1670         ret = PAGE_ALIGN(base + brk_rnd());
1671 
1672         if (ret < mm->brk)
1673                 return mm->brk;
1674 
1675         return ret;
1676 }
1677 
1678 unsigned long randomize_et_dyn(unsigned long base)
1679 {
1680         unsigned long ret = PAGE_ALIGN(base + brk_rnd());
1681 
1682         if (ret < base)
1683                 return base;
1684 
1685         return ret;
1686 }
1687 

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