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Linux/arch/powerpc/platforms/52xx/mpc52xx_gpt.c

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  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  * MPC5200 General Purpose Timer device driver
  4  *
  5  * Copyright (c) 2009 Secret Lab Technologies Ltd.
  6  * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  7  *
  8  * This file is a driver for the the General Purpose Timer (gpt) devices
  9  * found on the MPC5200 SoC.  Each timer has an IO pin which can be used
 10  * for GPIO or can be used to raise interrupts.  The timer function can
 11  * be used independently from the IO pin, or it can be used to control
 12  * output signals or measure input signals.
 13  *
 14  * This driver supports the GPIO and IRQ controller functions of the GPT
 15  * device.  Timer functions are not yet supported.
 16  *
 17  * The timer gpt0 can be used as watchdog (wdt).  If the wdt mode is used,
 18  * this prevents the use of any gpt0 gpt function (i.e. they will fail with
 19  * -EBUSY).  Thus, the safety wdt function always has precedence over the gpt
 20  * function.  If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
 21  * this means that gpt0 is locked in wdt mode until the next reboot - this
 22  * may be a requirement in safety applications.
 23  *
 24  * To use the GPIO function, the following two properties must be added
 25  * to the device tree node for the gpt device (typically in the .dts file
 26  * for the board):
 27  *      gpio-controller;
 28  *      #gpio-cells = < 2 >;
 29  * This driver will register the GPIO pin if it finds the gpio-controller
 30  * property in the device tree.
 31  *
 32  * To use the IRQ controller function, the following two properties must
 33  * be added to the device tree node for the gpt device:
 34  *      interrupt-controller;
 35  *      #interrupt-cells = < 1 >;
 36  * The IRQ controller binding only uses one cell to specify the interrupt,
 37  * and the IRQ flags are encoded in the cell.  A cell is not used to encode
 38  * the IRQ number because the GPT only has a single IRQ source.  For flags,
 39  * a value of '1' means rising edge sensitive and '2' means falling edge.
 40  *
 41  * The GPIO and the IRQ controller functions can be used at the same time,
 42  * but in this use case the IO line will only work as an input.  Trying to
 43  * use it as a GPIO output will not work.
 44  *
 45  * When using the GPIO line as an output, it can either be driven as normal
 46  * IO, or it can be an Open Collector (OC) output.  At the moment it is the
 47  * responsibility of either the bootloader or the platform setup code to set
 48  * the output mode.  This driver does not change the output mode setting.
 49  */
 50 
 51 #include <linux/device.h>
 52 #include <linux/irq.h>
 53 #include <linux/interrupt.h>
 54 #include <linux/io.h>
 55 #include <linux/list.h>
 56 #include <linux/mutex.h>
 57 #include <linux/of.h>
 58 #include <linux/of_platform.h>
 59 #include <linux/of_gpio.h>
 60 #include <linux/kernel.h>
 61 #include <linux/slab.h>
 62 #include <linux/fs.h>
 63 #include <linux/watchdog.h>
 64 #include <linux/miscdevice.h>
 65 #include <linux/uaccess.h>
 66 #include <linux/module.h>
 67 #include <asm/div64.h>
 68 #include <asm/mpc52xx.h>
 69 
 70 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
 71 MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht DreƟ");
 72 MODULE_LICENSE("GPL");
 73 
 74 /**
 75  * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
 76  * @dev: pointer to device structure
 77  * @regs: virtual address of GPT registers
 78  * @lock: spinlock to coordinate between different functions.
 79  * @gc: gpio_chip instance structure; used when GPIO is enabled
 80  * @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported
 81  * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
 82  *   if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
 83  *   if the timer is actively used as wdt which blocks gpt functions
 84  */
 85 struct mpc52xx_gpt_priv {
 86         struct list_head list;          /* List of all GPT devices */
 87         struct device *dev;
 88         struct mpc52xx_gpt __iomem *regs;
 89         raw_spinlock_t lock;
 90         struct irq_domain *irqhost;
 91         u32 ipb_freq;
 92         u8 wdt_mode;
 93 
 94 #if defined(CONFIG_GPIOLIB)
 95         struct gpio_chip gc;
 96 #endif
 97 };
 98 
 99 LIST_HEAD(mpc52xx_gpt_list);
100 DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
101 
102 #define MPC52xx_GPT_MODE_MS_MASK        (0x07)
103 #define MPC52xx_GPT_MODE_MS_IC          (0x01)
104 #define MPC52xx_GPT_MODE_MS_OC          (0x02)
105 #define MPC52xx_GPT_MODE_MS_PWM         (0x03)
106 #define MPC52xx_GPT_MODE_MS_GPIO        (0x04)
107 
108 #define MPC52xx_GPT_MODE_GPIO_MASK      (0x30)
109 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW   (0x20)
110 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH  (0x30)
111 
112 #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
113 #define MPC52xx_GPT_MODE_CONTINUOUS     (0x0400)
114 #define MPC52xx_GPT_MODE_OPEN_DRAIN     (0x0200)
115 #define MPC52xx_GPT_MODE_IRQ_EN         (0x0100)
116 #define MPC52xx_GPT_MODE_WDT_EN         (0x8000)
117 
118 #define MPC52xx_GPT_MODE_ICT_MASK       (0x030000)
119 #define MPC52xx_GPT_MODE_ICT_RISING     (0x010000)
120 #define MPC52xx_GPT_MODE_ICT_FALLING    (0x020000)
121 #define MPC52xx_GPT_MODE_ICT_TOGGLE     (0x030000)
122 
123 #define MPC52xx_GPT_MODE_WDT_PING       (0xa5)
124 
125 #define MPC52xx_GPT_STATUS_IRQMASK      (0x000f)
126 
127 #define MPC52xx_GPT_CAN_WDT             (1 << 0)
128 #define MPC52xx_GPT_IS_WDT              (1 << 1)
129 
130 
131 /* ---------------------------------------------------------------------
132  * Cascaded interrupt controller hooks
133  */
134 
135 static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
136 {
137         struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
138         unsigned long flags;
139 
140         raw_spin_lock_irqsave(&gpt->lock, flags);
141         setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
142         raw_spin_unlock_irqrestore(&gpt->lock, flags);
143 }
144 
145 static void mpc52xx_gpt_irq_mask(struct irq_data *d)
146 {
147         struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
148         unsigned long flags;
149 
150         raw_spin_lock_irqsave(&gpt->lock, flags);
151         clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
152         raw_spin_unlock_irqrestore(&gpt->lock, flags);
153 }
154 
155 static void mpc52xx_gpt_irq_ack(struct irq_data *d)
156 {
157         struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
158 
159         out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
160 }
161 
162 static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
163 {
164         struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
165         unsigned long flags;
166         u32 reg;
167 
168         dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
169 
170         raw_spin_lock_irqsave(&gpt->lock, flags);
171         reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
172         if (flow_type & IRQF_TRIGGER_RISING)
173                 reg |= MPC52xx_GPT_MODE_ICT_RISING;
174         if (flow_type & IRQF_TRIGGER_FALLING)
175                 reg |= MPC52xx_GPT_MODE_ICT_FALLING;
176         out_be32(&gpt->regs->mode, reg);
177         raw_spin_unlock_irqrestore(&gpt->lock, flags);
178 
179         return 0;
180 }
181 
182 static struct irq_chip mpc52xx_gpt_irq_chip = {
183         .name = "MPC52xx GPT",
184         .irq_unmask = mpc52xx_gpt_irq_unmask,
185         .irq_mask = mpc52xx_gpt_irq_mask,
186         .irq_ack = mpc52xx_gpt_irq_ack,
187         .irq_set_type = mpc52xx_gpt_irq_set_type,
188 };
189 
190 static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
191 {
192         struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
193         int sub_virq;
194         u32 status;
195 
196         status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
197         if (status) {
198                 sub_virq = irq_linear_revmap(gpt->irqhost, 0);
199                 generic_handle_irq(sub_virq);
200         }
201 }
202 
203 static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
204                                irq_hw_number_t hw)
205 {
206         struct mpc52xx_gpt_priv *gpt = h->host_data;
207 
208         dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
209         irq_set_chip_data(virq, gpt);
210         irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
211 
212         return 0;
213 }
214 
215 static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct,
216                                  const u32 *intspec, unsigned int intsize,
217                                  irq_hw_number_t *out_hwirq,
218                                  unsigned int *out_flags)
219 {
220         struct mpc52xx_gpt_priv *gpt = h->host_data;
221 
222         dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
223 
224         if ((intsize < 1) || (intspec[0] > 3)) {
225                 dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct);
226                 return -EINVAL;
227         }
228 
229         *out_hwirq = 0; /* The GPT only has 1 IRQ line */
230         *out_flags = intspec[0];
231 
232         return 0;
233 }
234 
235 static const struct irq_domain_ops mpc52xx_gpt_irq_ops = {
236         .map = mpc52xx_gpt_irq_map,
237         .xlate = mpc52xx_gpt_irq_xlate,
238 };
239 
240 static void
241 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
242 {
243         int cascade_virq;
244         unsigned long flags;
245         u32 mode;
246 
247         cascade_virq = irq_of_parse_and_map(node, 0);
248         if (!cascade_virq)
249                 return;
250 
251         gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt);
252         if (!gpt->irqhost) {
253                 dev_err(gpt->dev, "irq_domain_add_linear() failed\n");
254                 return;
255         }
256 
257         irq_set_handler_data(cascade_virq, gpt);
258         irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
259 
260         /* If the GPT is currently disabled, then change it to be in Input
261          * Capture mode.  If the mode is non-zero, then the pin could be
262          * already in use for something. */
263         raw_spin_lock_irqsave(&gpt->lock, flags);
264         mode = in_be32(&gpt->regs->mode);
265         if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
266                 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
267         raw_spin_unlock_irqrestore(&gpt->lock, flags);
268 
269         dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
270 }
271 
272 
273 /* ---------------------------------------------------------------------
274  * GPIOLIB hooks
275  */
276 #if defined(CONFIG_GPIOLIB)
277 static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
278 {
279         struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
280 
281         return (in_be32(&gpt->regs->status) >> 8) & 1;
282 }
283 
284 static void
285 mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
286 {
287         struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
288         unsigned long flags;
289         u32 r;
290 
291         dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
292         r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
293 
294         raw_spin_lock_irqsave(&gpt->lock, flags);
295         clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
296         raw_spin_unlock_irqrestore(&gpt->lock, flags);
297 }
298 
299 static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
300 {
301         struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
302         unsigned long flags;
303 
304         dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
305 
306         raw_spin_lock_irqsave(&gpt->lock, flags);
307         clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
308         raw_spin_unlock_irqrestore(&gpt->lock, flags);
309 
310         return 0;
311 }
312 
313 static int
314 mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
315 {
316         mpc52xx_gpt_gpio_set(gc, gpio, val);
317         return 0;
318 }
319 
320 static void
321 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
322 {
323         int rc;
324 
325         /* Only setup GPIO if the device tree claims the GPT is
326          * a GPIO controller */
327         if (!of_find_property(node, "gpio-controller", NULL))
328                 return;
329 
330         gpt->gc.label = kasprintf(GFP_KERNEL, "%pOF", node);
331         if (!gpt->gc.label) {
332                 dev_err(gpt->dev, "out of memory\n");
333                 return;
334         }
335 
336         gpt->gc.ngpio = 1;
337         gpt->gc.direction_input  = mpc52xx_gpt_gpio_dir_in;
338         gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
339         gpt->gc.get = mpc52xx_gpt_gpio_get;
340         gpt->gc.set = mpc52xx_gpt_gpio_set;
341         gpt->gc.base = -1;
342         gpt->gc.of_node = node;
343 
344         /* Setup external pin in GPIO mode */
345         clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
346                         MPC52xx_GPT_MODE_MS_GPIO);
347 
348         rc = gpiochip_add_data(&gpt->gc, gpt);
349         if (rc)
350                 dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc);
351 
352         dev_dbg(gpt->dev, "%s() complete.\n", __func__);
353 }
354 #else /* defined(CONFIG_GPIOLIB) */
355 static void
356 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
357 #endif /* defined(CONFIG_GPIOLIB) */
358 
359 /***********************************************************************
360  * Timer API
361  */
362 
363 /**
364  * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
365  * @irq: irq of timer.
366  */
367 struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
368 {
369         struct mpc52xx_gpt_priv *gpt;
370         struct list_head *pos;
371 
372         /* Iterate over the list of timers looking for a matching device */
373         mutex_lock(&mpc52xx_gpt_list_mutex);
374         list_for_each(pos, &mpc52xx_gpt_list) {
375                 gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
376                 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
377                         mutex_unlock(&mpc52xx_gpt_list_mutex);
378                         return gpt;
379                 }
380         }
381         mutex_unlock(&mpc52xx_gpt_list_mutex);
382 
383         return NULL;
384 }
385 EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
386 
387 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
388                                 int continuous, int as_wdt)
389 {
390         u32 clear, set;
391         u64 clocks;
392         u32 prescale;
393         unsigned long flags;
394 
395         clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
396         set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
397         if (as_wdt) {
398                 clear |= MPC52xx_GPT_MODE_IRQ_EN;
399                 set |= MPC52xx_GPT_MODE_WDT_EN;
400         } else if (continuous)
401                 set |= MPC52xx_GPT_MODE_CONTINUOUS;
402 
403         /* Determine the number of clocks in the requested period.  64 bit
404          * arithmatic is done here to preserve the precision until the value
405          * is scaled back down into the u32 range.  Period is in 'ns', bus
406          * frequency is in Hz. */
407         clocks = period * (u64)gpt->ipb_freq;
408         do_div(clocks, 1000000000); /* Scale it down to ns range */
409 
410         /* This device cannot handle a clock count greater than 32 bits */
411         if (clocks > 0xffffffff)
412                 return -EINVAL;
413 
414         /* Calculate the prescaler and count values from the clocks value.
415          * 'clocks' is the number of clock ticks in the period.  The timer
416          * has 16 bit precision and a 16 bit prescaler.  Prescaler is
417          * calculated by integer dividing the clocks by 0x10000 (shifting
418          * down 16 bits) to obtain the smallest possible divisor for clocks
419          * to get a 16 bit count value.
420          *
421          * Note: the prescale register is '1' based, not '' based.  ie. a
422          * value of '1' means divide the clock by one.  0xffff divides the
423          * clock by 0xffff.  '0x0000' does not divide by zero, but wraps
424          * around and divides by 0x10000.  That is why prescale must be
425          * a u32 variable, not a u16, for this calculation. */
426         prescale = (clocks >> 16) + 1;
427         do_div(clocks, prescale);
428         if (clocks > 0xffff) {
429                 pr_err("calculation error; prescale:%x clocks:%llx\n",
430                        prescale, clocks);
431                 return -EINVAL;
432         }
433 
434         /* Set and enable the timer, reject an attempt to use a wdt as gpt */
435         raw_spin_lock_irqsave(&gpt->lock, flags);
436         if (as_wdt)
437                 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
438         else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
439                 raw_spin_unlock_irqrestore(&gpt->lock, flags);
440                 return -EBUSY;
441         }
442         out_be32(&gpt->regs->count, prescale << 16 | clocks);
443         clrsetbits_be32(&gpt->regs->mode, clear, set);
444         raw_spin_unlock_irqrestore(&gpt->lock, flags);
445 
446         return 0;
447 }
448 
449 /**
450  * mpc52xx_gpt_start_timer - Set and enable the GPT timer
451  * @gpt: Pointer to gpt private data structure
452  * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
453  * @continuous: set to 1 to make timer continuous free running
454  *
455  * An interrupt will be generated every time the timer fires
456  */
457 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
458                             int continuous)
459 {
460         return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
461 }
462 EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
463 
464 /**
465  * mpc52xx_gpt_stop_timer - Stop a gpt
466  * @gpt: Pointer to gpt private data structure
467  *
468  * Returns an error if attempting to stop a wdt
469  */
470 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
471 {
472         unsigned long flags;
473 
474         /* reject the operation if the timer is used as watchdog (gpt 0 only) */
475         raw_spin_lock_irqsave(&gpt->lock, flags);
476         if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
477                 raw_spin_unlock_irqrestore(&gpt->lock, flags);
478                 return -EBUSY;
479         }
480 
481         clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
482         raw_spin_unlock_irqrestore(&gpt->lock, flags);
483         return 0;
484 }
485 EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
486 
487 /**
488  * mpc52xx_gpt_timer_period - Read the timer period
489  * @gpt: Pointer to gpt private data structure
490  *
491  * Returns the timer period in ns
492  */
493 u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
494 {
495         u64 period;
496         u64 prescale;
497         unsigned long flags;
498 
499         raw_spin_lock_irqsave(&gpt->lock, flags);
500         period = in_be32(&gpt->regs->count);
501         raw_spin_unlock_irqrestore(&gpt->lock, flags);
502 
503         prescale = period >> 16;
504         period &= 0xffff;
505         if (prescale == 0)
506                 prescale = 0x10000;
507         period = period * prescale * 1000000000ULL;
508         do_div(period, (u64)gpt->ipb_freq);
509         return period;
510 }
511 EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
512 
513 #if defined(CONFIG_MPC5200_WDT)
514 /***********************************************************************
515  * Watchdog API for gpt0
516  */
517 
518 #define WDT_IDENTITY        "mpc52xx watchdog on GPT0"
519 
520 /* wdt_is_active stores whether or not the /dev/watchdog device is opened */
521 static unsigned long wdt_is_active;
522 
523 /* wdt-capable gpt */
524 static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
525 
526 /* low-level wdt functions */
527 static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
528 {
529         unsigned long flags;
530 
531         raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
532         out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
533         raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
534 }
535 
536 /* wdt misc device api */
537 static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
538                                  size_t len, loff_t *ppos)
539 {
540         struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
541         mpc52xx_gpt_wdt_ping(gpt_wdt);
542         return 0;
543 }
544 
545 static const struct watchdog_info mpc5200_wdt_info = {
546         .options        = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
547         .identity       = WDT_IDENTITY,
548 };
549 
550 static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
551                               unsigned long arg)
552 {
553         struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
554         int __user *data = (int __user *)arg;
555         int timeout;
556         u64 real_timeout;
557         int ret = 0;
558 
559         switch (cmd) {
560         case WDIOC_GETSUPPORT:
561                 ret = copy_to_user(data, &mpc5200_wdt_info,
562                                    sizeof(mpc5200_wdt_info));
563                 if (ret)
564                         ret = -EFAULT;
565                 break;
566 
567         case WDIOC_GETSTATUS:
568         case WDIOC_GETBOOTSTATUS:
569                 ret = put_user(0, data);
570                 break;
571 
572         case WDIOC_KEEPALIVE:
573                 mpc52xx_gpt_wdt_ping(gpt_wdt);
574                 break;
575 
576         case WDIOC_SETTIMEOUT:
577                 ret = get_user(timeout, data);
578                 if (ret)
579                         break;
580                 real_timeout = (u64) timeout * 1000000000ULL;
581                 ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
582                 if (ret)
583                         break;
584                 /* fall through and return the timeout */
585 
586         case WDIOC_GETTIMEOUT:
587                 /* we need to round here as to avoid e.g. the following
588                  * situation:
589                  * - timeout requested is 1 second;
590                  * - real timeout @33MHz is 999997090ns
591                  * - the int divide by 10^9 will return 0.
592                  */
593                 real_timeout =
594                         mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
595                 do_div(real_timeout, 1000000000ULL);
596                 timeout = (int) real_timeout;
597                 ret = put_user(timeout, data);
598                 break;
599 
600         default:
601                 ret = -ENOTTY;
602         }
603         return ret;
604 }
605 
606 static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
607 {
608         int ret;
609 
610         /* sanity check */
611         if (!mpc52xx_gpt_wdt)
612                 return -ENODEV;
613 
614         /* /dev/watchdog can only be opened once */
615         if (test_and_set_bit(0, &wdt_is_active))
616                 return -EBUSY;
617 
618         /* Set and activate the watchdog with 30 seconds timeout */
619         ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
620                                    0, 1);
621         if (ret) {
622                 clear_bit(0, &wdt_is_active);
623                 return ret;
624         }
625 
626         file->private_data = mpc52xx_gpt_wdt;
627         return stream_open(inode, file);
628 }
629 
630 static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
631 {
632         /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
633 #if !defined(CONFIG_WATCHDOG_NOWAYOUT)
634         struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
635         unsigned long flags;
636 
637         raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
638         clrbits32(&gpt_wdt->regs->mode,
639                   MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
640         gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
641         raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
642 #endif
643         clear_bit(0, &wdt_is_active);
644         return 0;
645 }
646 
647 
648 static const struct file_operations mpc52xx_wdt_fops = {
649         .owner          = THIS_MODULE,
650         .llseek         = no_llseek,
651         .write          = mpc52xx_wdt_write,
652         .unlocked_ioctl = mpc52xx_wdt_ioctl,
653         .compat_ioctl   = compat_ptr_ioctl,
654         .open           = mpc52xx_wdt_open,
655         .release        = mpc52xx_wdt_release,
656 };
657 
658 static struct miscdevice mpc52xx_wdt_miscdev = {
659         .minor          = WATCHDOG_MINOR,
660         .name           = "watchdog",
661         .fops           = &mpc52xx_wdt_fops,
662 };
663 
664 static int mpc52xx_gpt_wdt_init(void)
665 {
666         int err;
667 
668         /* try to register the watchdog misc device */
669         err = misc_register(&mpc52xx_wdt_miscdev);
670         if (err)
671                 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
672         else
673                 pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
674         return err;
675 }
676 
677 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
678                                  const u32 *period)
679 {
680         u64 real_timeout;
681 
682         /* remember the gpt for the wdt operation */
683         mpc52xx_gpt_wdt = gpt;
684 
685         /* configure the wdt if the device tree contained a timeout */
686         if (!period || *period == 0)
687                 return 0;
688 
689         real_timeout = (u64) *period * 1000000000ULL;
690         if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
691                 dev_warn(gpt->dev, "starting as wdt failed\n");
692         else
693                 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
694         return 0;
695 }
696 
697 #else
698 
699 static int mpc52xx_gpt_wdt_init(void)
700 {
701         return 0;
702 }
703 
704 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
705                                         const u32 *period)
706 {
707         return 0;
708 }
709 
710 #endif  /*  CONFIG_MPC5200_WDT  */
711 
712 /* ---------------------------------------------------------------------
713  * of_platform bus binding code
714  */
715 static int mpc52xx_gpt_probe(struct platform_device *ofdev)
716 {
717         struct mpc52xx_gpt_priv *gpt;
718 
719         gpt = devm_kzalloc(&ofdev->dev, sizeof *gpt, GFP_KERNEL);
720         if (!gpt)
721                 return -ENOMEM;
722 
723         raw_spin_lock_init(&gpt->lock);
724         gpt->dev = &ofdev->dev;
725         gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
726         gpt->regs = of_iomap(ofdev->dev.of_node, 0);
727         if (!gpt->regs)
728                 return -ENOMEM;
729 
730         dev_set_drvdata(&ofdev->dev, gpt);
731 
732         mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node);
733         mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);
734 
735         mutex_lock(&mpc52xx_gpt_list_mutex);
736         list_add(&gpt->list, &mpc52xx_gpt_list);
737         mutex_unlock(&mpc52xx_gpt_list_mutex);
738 
739         /* check if this device could be a watchdog */
740         if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) ||
741             of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) {
742                 const u32 *on_boot_wdt;
743 
744                 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
745                 on_boot_wdt = of_get_property(ofdev->dev.of_node,
746                                               "fsl,wdt-on-boot", NULL);
747                 if (on_boot_wdt) {
748                         dev_info(gpt->dev, "used as watchdog\n");
749                         gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
750                 } else
751                         dev_info(gpt->dev, "can function as watchdog\n");
752                 mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
753         }
754 
755         return 0;
756 }
757 
758 static int mpc52xx_gpt_remove(struct platform_device *ofdev)
759 {
760         return -EBUSY;
761 }
762 
763 static const struct of_device_id mpc52xx_gpt_match[] = {
764         { .compatible = "fsl,mpc5200-gpt", },
765 
766         /* Depreciated compatible values; don't use for new dts files */
767         { .compatible = "fsl,mpc5200-gpt-gpio", },
768         { .compatible = "mpc5200-gpt", },
769         {}
770 };
771 
772 static struct platform_driver mpc52xx_gpt_driver = {
773         .driver = {
774                 .name = "mpc52xx-gpt",
775                 .of_match_table = mpc52xx_gpt_match,
776         },
777         .probe = mpc52xx_gpt_probe,
778         .remove = mpc52xx_gpt_remove,
779 };
780 
781 static int __init mpc52xx_gpt_init(void)
782 {
783         return platform_driver_register(&mpc52xx_gpt_driver);
784 }
785 
786 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */
787 subsys_initcall(mpc52xx_gpt_init);
788 device_initcall(mpc52xx_gpt_wdt_init);
789 

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