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TOMOYO Linux Cross Reference
Linux/arch/sparc/include/asm/hypervisor.h

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  1 #ifndef _SPARC64_HYPERVISOR_H
  2 #define _SPARC64_HYPERVISOR_H
  3 
  4 /* Sun4v hypervisor interfaces and defines.
  5  *
  6  * Hypervisor calls are made via traps to software traps number 0x80
  7  * and above.  Registers %o0 to %o5 serve as argument, status, and
  8  * return value registers.
  9  *
 10  * There are two kinds of these traps.  First there are the normal
 11  * "fast traps" which use software trap 0x80 and encode the function
 12  * to invoke by number in register %o5.  Argument and return value
 13  * handling is as follows:
 14  *
 15  * -----------------------------------------------
 16  * |  %o5  | function number |     undefined     |
 17  * |  %o0  |   argument 0    |   return status   |
 18  * |  %o1  |   argument 1    |   return value 1  |
 19  * |  %o2  |   argument 2    |   return value 2  |
 20  * |  %o3  |   argument 3    |   return value 3  |
 21  * |  %o4  |   argument 4    |   return value 4  |
 22  * -----------------------------------------------
 23  *
 24  * The second type are "hyper-fast traps" which encode the function
 25  * number in the software trap number itself.  So these use trap
 26  * numbers > 0x80.  The register usage for hyper-fast traps is as
 27  * follows:
 28  *
 29  * -----------------------------------------------
 30  * |  %o0  |   argument 0    |   return status   |
 31  * |  %o1  |   argument 1    |   return value 1  |
 32  * |  %o2  |   argument 2    |   return value 2  |
 33  * |  %o3  |   argument 3    |   return value 3  |
 34  * |  %o4  |   argument 4    |   return value 4  |
 35  * -----------------------------------------------
 36  *
 37  * Registers providing explicit arguments to the hypervisor calls
 38  * are volatile across the call.  Upon return their values are
 39  * undefined unless explicitly specified as containing a particular
 40  * return value by the specific call.  The return status is always
 41  * returned in register %o0, zero indicates a successful execution of
 42  * the hypervisor call and other values indicate an error status as
 43  * defined below.  So, for example, if a hyper-fast trap takes
 44  * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
 45  * the call and %o3, %o4, and %o5 would be preserved.
 46  *
 47  * If the hypervisor trap is invalid, or the fast trap function number
 48  * is invalid, HV_EBADTRAP will be returned in %o0.  Also, all 64-bits
 49  * of the argument and return values are significant.
 50  */
 51 
 52 /* Trap numbers.  */
 53 #define HV_FAST_TRAP            0x80
 54 #define HV_MMU_MAP_ADDR_TRAP    0x83
 55 #define HV_MMU_UNMAP_ADDR_TRAP  0x84
 56 #define HV_TTRACE_ADDENTRY_TRAP 0x85
 57 #define HV_CORE_TRAP            0xff
 58 
 59 /* Error codes.  */
 60 #define HV_EOK                          0  /* Successful return            */
 61 #define HV_ENOCPU                       1  /* Invalid CPU id               */
 62 #define HV_ENORADDR                     2  /* Invalid real address         */
 63 #define HV_ENOINTR                      3  /* Invalid interrupt id         */
 64 #define HV_EBADPGSZ                     4  /* Invalid pagesize encoding    */
 65 #define HV_EBADTSB                      5  /* Invalid TSB description      */
 66 #define HV_EINVAL                       6  /* Invalid argument             */
 67 #define HV_EBADTRAP                     7  /* Invalid function number      */
 68 #define HV_EBADALIGN                    8  /* Invalid address alignment    */
 69 #define HV_EWOULDBLOCK                  9  /* Cannot complete w/o blocking */
 70 #define HV_ENOACCESS                    10 /* No access to resource        */
 71 #define HV_EIO                          11 /* I/O error                    */
 72 #define HV_ECPUERROR                    12 /* CPU in error state           */
 73 #define HV_ENOTSUPPORTED                13 /* Function not supported       */
 74 #define HV_ENOMAP                       14 /* No mapping found             */
 75 #define HV_ETOOMANY                     15 /* Too many items specified     */
 76 #define HV_ECHANNEL                     16 /* Invalid LDC channel          */
 77 #define HV_EBUSY                        17 /* Resource busy                */
 78 
 79 /* mach_exit()
 80  * TRAP:        HV_FAST_TRAP
 81  * FUNCTION:    HV_FAST_MACH_EXIT
 82  * ARG0:        exit code
 83  * ERRORS:      This service does not return.
 84  *
 85  * Stop all CPUs in the virtual domain and place them into the stopped
 86  * state.  The 64-bit exit code may be passed to a service entity as
 87  * the domain's exit status.  On systems without a service entity, the
 88  * domain will undergo a reset, and the boot firmware will be
 89  * reloaded.
 90  *
 91  * This function will never return to the guest that invokes it.
 92  *
 93  * Note: By convention an exit code of zero denotes a successful exit by
 94  *       the guest code.  A non-zero exit code denotes a guest specific
 95  *       error indication.
 96  *
 97  */
 98 #define HV_FAST_MACH_EXIT               0x00
 99 
100 #ifndef __ASSEMBLY__
101 void sun4v_mach_exit(unsigned long exit_code);
102 #endif
103 
104 /* Domain services.  */
105 
106 /* mach_desc()
107  * TRAP:        HV_FAST_TRAP
108  * FUNCTION:    HV_FAST_MACH_DESC
109  * ARG0:        buffer
110  * ARG1:        length
111  * RET0:        status
112  * RET1:        length
113  * ERRORS:      HV_EBADALIGN    Buffer is badly aligned
114  *              HV_ENORADDR     Buffer is to an illegal real address.
115  *              HV_EINVAL       Buffer length is too small for complete
116  *                              machine description.
117  *
118  * Copy the most current machine description into the buffer indicated
119  * by the real address in ARG0.  The buffer provided must be 16 byte
120  * aligned.  Upon success or HV_EINVAL, this service returns the
121  * actual size of the machine description in the RET1 return value.
122  *
123  * Note: A method of determining the appropriate buffer size for the
124  *       machine description is to first call this service with a buffer
125  *       length of 0 bytes.
126  */
127 #define HV_FAST_MACH_DESC               0x01
128 
129 #ifndef __ASSEMBLY__
130 unsigned long sun4v_mach_desc(unsigned long buffer_pa,
131                               unsigned long buf_len,
132                               unsigned long *real_buf_len);
133 #endif
134 
135 /* mach_sir()
136  * TRAP:        HV_FAST_TRAP
137  * FUNCTION:    HV_FAST_MACH_SIR
138  * ERRORS:      This service does not return.
139  *
140  * Perform a software initiated reset of the virtual machine domain.
141  * All CPUs are captured as soon as possible, all hardware devices are
142  * returned to the entry default state, and the domain is restarted at
143  * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
144  * of the CPUs.  The single CPU restarted is selected as determined by
145  * platform specific policy.  Memory is preserved across this
146  * operation.
147  */
148 #define HV_FAST_MACH_SIR                0x02
149 
150 #ifndef __ASSEMBLY__
151 void sun4v_mach_sir(void);
152 #endif
153 
154 /* mach_set_watchdog()
155  * TRAP:        HV_FAST_TRAP
156  * FUNCTION:    HV_FAST_MACH_SET_WATCHDOG
157  * ARG0:        timeout in milliseconds
158  * RET0:        status
159  * RET1:        time remaining in milliseconds
160  *
161  * A guest uses this API to set a watchdog timer.  Once the gues has set
162  * the timer, it must call the timer service again either to disable or
163  * postpone the expiration.  If the timer expires before being reset or
164  * disabled, then the hypervisor take a platform specific action leading
165  * to guest termination within a bounded time period.  The platform action
166  * may include recovery actions such as reporting the expiration to a
167  * Service Processor, and/or automatically restarting the gues.
168  *
169  * The 'timeout' parameter is specified in milliseconds, however the
170  * implementated granularity is given by the 'watchdog-resolution'
171  * property in the 'platform' node of the guest's machine description.
172  * The largest allowed timeout value is specified by the
173  * 'watchdog-max-timeout' property of the 'platform' node.
174  *
175  * If the 'timeout' argument is not zero, the watchdog timer is set to
176  * expire after a minimum of 'timeout' milliseconds.
177  *
178  * If the 'timeout' argument is zero, the watchdog timer is disabled.
179  *
180  * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
181  * property, the hypervisor leaves the watchdog timer state unchanged,
182  * and returns a status of EINVAL.
183  *
184  * The 'time remaining' return value is valid regardless of whether the
185  * return status is EOK or EINVAL.  A non-zero return value indicates the
186  * number of milliseconds that were remaining until the timer was to expire.
187  * If less than one millisecond remains, the return value is '1'.  If the
188  * watchdog timer was disabled at the time of the call, the return value is
189  * zero.
190  *
191  * If the hypervisor cannot support the exact timeout value requested, but
192  * can support a larger timeout value, the hypervisor may round the actual
193  * timeout to a value larger than the requested timeout, consequently the
194  * 'time remaining' return value may be larger than the previously requested
195  * timeout value.
196  *
197  * Any guest OS debugger should be aware that the watchdog service may be in
198  * use.  Consequently, it is recommended that the watchdog service is
199  * disabled upon debugger entry (e.g. reaching a breakpoint), and then
200  * re-enabled upon returning to normal execution.  The API has been designed
201  * with this in mind, and the 'time remaining' result of the disable call may
202  * be used directly as the timeout argument of the re-enable call.
203  */
204 #define HV_FAST_MACH_SET_WATCHDOG       0x05
205 
206 #ifndef __ASSEMBLY__
207 unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
208                                       unsigned long *orig_timeout);
209 #endif
210 
211 /* CPU services.
212  *
213  * CPUs represent devices that can execute software threads.  A single
214  * chip that contains multiple cores or strands is represented as
215  * multiple CPUs with unique CPU identifiers.  CPUs are exported to
216  * OBP via the machine description (and to the OS via the OBP device
217  * tree).  CPUs are always in one of three states: stopped, running,
218  * or error.
219  *
220  * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
221  * CPU within a logical domain.  Operations that are to be performed
222  * on multiple CPUs specify them via a CPU list.  A CPU list is an
223  * array in real memory, of which each 16-bit word is a CPU ID.  CPU
224  * lists are passed through the API as two arguments.  The first is
225  * the number of entries (16-bit words) in the CPU list, and the
226  * second is the (real address) pointer to the CPU ID list.
227  */
228 
229 /* cpu_start()
230  * TRAP:        HV_FAST_TRAP
231  * FUNCTION:    HV_FAST_CPU_START
232  * ARG0:        CPU ID
233  * ARG1:        PC
234  * ARG2:        RTBA
235  * ARG3:        target ARG0
236  * RET0:        status
237  * ERRORS:      ENOCPU          Invalid CPU ID
238  *              EINVAL          Target CPU ID is not in the stopped state
239  *              ENORADDR        Invalid PC or RTBA real address
240  *              EBADALIGN       Unaligned PC or unaligned RTBA
241  *              EWOULDBLOCK     Starting resources are not available
242  *
243  * Start CPU with given CPU ID with PC in %pc and with a real trap
244  * base address value of RTBA.  The indicated CPU must be in the
245  * stopped state.  The supplied RTBA must be aligned on a 256 byte
246  * boundary.  On successful completion, the specified CPU will be in
247  * the running state and will be supplied with "target ARG0" in %o0
248  * and RTBA in %tba.
249  */
250 #define HV_FAST_CPU_START               0x10
251 
252 #ifndef __ASSEMBLY__
253 unsigned long sun4v_cpu_start(unsigned long cpuid,
254                               unsigned long pc,
255                               unsigned long rtba,
256                               unsigned long arg0);
257 #endif
258 
259 /* cpu_stop()
260  * TRAP:        HV_FAST_TRAP
261  * FUNCTION:    HV_FAST_CPU_STOP
262  * ARG0:        CPU ID
263  * RET0:        status
264  * ERRORS:      ENOCPU          Invalid CPU ID
265  *              EINVAL          Target CPU ID is the current cpu
266  *              EINVAL          Target CPU ID is not in the running state
267  *              EWOULDBLOCK     Stopping resources are not available
268  *              ENOTSUPPORTED   Not supported on this platform
269  *
270  * The specified CPU is stopped.  The indicated CPU must be in the
271  * running state.  On completion, it will be in the stopped state.  It
272  * is not legal to stop the current CPU.
273  *
274  * Note: As this service cannot be used to stop the current cpu, this service
275  *       may not be used to stop the last running CPU in a domain.  To stop
276  *       and exit a running domain, a guest must use the mach_exit() service.
277  */
278 #define HV_FAST_CPU_STOP                0x11
279 
280 #ifndef __ASSEMBLY__
281 unsigned long sun4v_cpu_stop(unsigned long cpuid);
282 #endif
283 
284 /* cpu_yield()
285  * TRAP:        HV_FAST_TRAP
286  * FUNCTION:    HV_FAST_CPU_YIELD
287  * RET0:        status
288  * ERRORS:      No possible error.
289  *
290  * Suspend execution on the current CPU.  Execution will resume when
291  * an interrupt (device, %stick_compare, or cross-call) is targeted to
292  * the CPU.  On some CPUs, this API may be used by the hypervisor to
293  * save power by disabling hardware strands.
294  */
295 #define HV_FAST_CPU_YIELD               0x12
296 
297 #ifndef __ASSEMBLY__
298 unsigned long sun4v_cpu_yield(void);
299 #endif
300 
301 /* cpu_qconf()
302  * TRAP:        HV_FAST_TRAP
303  * FUNCTION:    HV_FAST_CPU_QCONF
304  * ARG0:        queue
305  * ARG1:        base real address
306  * ARG2:        number of entries
307  * RET0:        status
308  * ERRORS:      ENORADDR        Invalid base real address
309  *              EINVAL          Invalid queue or number of entries is less
310  *                              than 2 or too large.
311  *              EBADALIGN       Base real address is not correctly aligned
312  *                              for size.
313  *
314  * Configure the given queue to be placed at the given base real
315  * address, with the given number of entries.  The number of entries
316  * must be a power of 2.  The base real address must be aligned
317  * exactly to match the queue size.  Each queue entry is 64 bytes
318  * long, so for example a 32 entry queue must be aligned on a 2048
319  * byte real address boundary.
320  *
321  * The specified queue is unconfigured if the number of entries is given
322  * as zero.
323  *
324  * For the current version of this API service, the argument queue is defined
325  * as follows:
326  *
327  *      queue           description
328  *      -----           -------------------------
329  *      0x3c            cpu mondo queue
330  *      0x3d            device mondo queue
331  *      0x3e            resumable error queue
332  *      0x3f            non-resumable error queue
333  *
334  * Note: The maximum number of entries for each queue for a specific cpu may
335  *       be determined from the machine description.
336  */
337 #define HV_FAST_CPU_QCONF               0x14
338 #define  HV_CPU_QUEUE_CPU_MONDO          0x3c
339 #define  HV_CPU_QUEUE_DEVICE_MONDO       0x3d
340 #define  HV_CPU_QUEUE_RES_ERROR          0x3e
341 #define  HV_CPU_QUEUE_NONRES_ERROR       0x3f
342 
343 #ifndef __ASSEMBLY__
344 unsigned long sun4v_cpu_qconf(unsigned long type,
345                               unsigned long queue_paddr,
346                               unsigned long num_queue_entries);
347 #endif
348 
349 /* cpu_qinfo()
350  * TRAP:        HV_FAST_TRAP
351  * FUNCTION:    HV_FAST_CPU_QINFO
352  * ARG0:        queue
353  * RET0:        status
354  * RET1:        base real address
355  * RET1:        number of entries
356  * ERRORS:      EINVAL          Invalid queue
357  *
358  * Return the configuration info for the given queue.  The base real
359  * address and number of entries of the defined queue are returned.
360  * The queue argument values are the same as for cpu_qconf() above.
361  *
362  * If the specified queue is a valid queue number, but no queue has
363  * been defined, the number of entries will be set to zero and the
364  * base real address returned is undefined.
365  */
366 #define HV_FAST_CPU_QINFO               0x15
367 
368 /* cpu_mondo_send()
369  * TRAP:        HV_FAST_TRAP
370  * FUNCTION:    HV_FAST_CPU_MONDO_SEND
371  * ARG0-1:      CPU list
372  * ARG2:        data real address
373  * RET0:        status
374  * ERRORS:      EBADALIGN       Mondo data is not 64-byte aligned or CPU list
375  *                              is not 2-byte aligned.
376  *              ENORADDR        Invalid data mondo address, or invalid cpu list
377  *                              address.
378  *              ENOCPU          Invalid cpu in CPU list
379  *              EWOULDBLOCK     Some or all of the listed CPUs did not receive
380  *                              the mondo
381  *              ECPUERROR       One or more of the listed CPUs are in error
382  *                              state, use HV_FAST_CPU_STATE to see which ones
383  *              EINVAL          CPU list includes caller's CPU ID
384  *
385  * Send a mondo interrupt to the CPUs in the given CPU list with the
386  * 64-bytes at the given data real address.  The data must be 64-byte
387  * aligned.  The mondo data will be delivered to the cpu_mondo queues
388  * of the recipient CPUs.
389  *
390  * In all cases, error or not, the CPUs in the CPU list to which the
391  * mondo has been successfully delivered will be indicated by having
392  * their entry in CPU list updated with the value 0xffff.
393  */
394 #define HV_FAST_CPU_MONDO_SEND          0x42
395 
396 #ifndef __ASSEMBLY__
397 unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count,
398                                    unsigned long cpu_list_pa,
399                                    unsigned long mondo_block_pa);
400 #endif
401 
402 /* cpu_myid()
403  * TRAP:        HV_FAST_TRAP
404  * FUNCTION:    HV_FAST_CPU_MYID
405  * RET0:        status
406  * RET1:        CPU ID
407  * ERRORS:      No errors defined.
408  *
409  * Return the hypervisor ID handle for the current CPU.  Use by a
410  * virtual CPU to discover it's own identity.
411  */
412 #define HV_FAST_CPU_MYID                0x16
413 
414 /* cpu_state()
415  * TRAP:        HV_FAST_TRAP
416  * FUNCTION:    HV_FAST_CPU_STATE
417  * ARG0:        CPU ID
418  * RET0:        status
419  * RET1:        state
420  * ERRORS:      ENOCPU          Invalid CPU ID
421  *
422  * Retrieve the current state of the CPU with the given CPU ID.
423  */
424 #define HV_FAST_CPU_STATE               0x17
425 #define  HV_CPU_STATE_STOPPED            0x01
426 #define  HV_CPU_STATE_RUNNING            0x02
427 #define  HV_CPU_STATE_ERROR              0x03
428 
429 #ifndef __ASSEMBLY__
430 long sun4v_cpu_state(unsigned long cpuid);
431 #endif
432 
433 /* cpu_set_rtba()
434  * TRAP:        HV_FAST_TRAP
435  * FUNCTION:    HV_FAST_CPU_SET_RTBA
436  * ARG0:        RTBA
437  * RET0:        status
438  * RET1:        previous RTBA
439  * ERRORS:      ENORADDR        Invalid RTBA real address
440  *              EBADALIGN       RTBA is incorrectly aligned for a trap table
441  *
442  * Set the real trap base address of the local cpu to the given RTBA.
443  * The supplied RTBA must be aligned on a 256 byte boundary.  Upon
444  * success the previous value of the RTBA is returned in RET1.
445  *
446  * Note: This service does not affect %tba
447  */
448 #define HV_FAST_CPU_SET_RTBA            0x18
449 
450 /* cpu_set_rtba()
451  * TRAP:        HV_FAST_TRAP
452  * FUNCTION:    HV_FAST_CPU_GET_RTBA
453  * RET0:        status
454  * RET1:        previous RTBA
455  * ERRORS:      No possible error.
456  *
457  * Returns the current value of RTBA in RET1.
458  */
459 #define HV_FAST_CPU_GET_RTBA            0x19
460 
461 /* MMU services.
462  *
463  * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
464  */
465 #ifndef __ASSEMBLY__
466 struct hv_tsb_descr {
467         unsigned short          pgsz_idx;
468         unsigned short          assoc;
469         unsigned int            num_ttes;       /* in TTEs */
470         unsigned int            ctx_idx;
471         unsigned int            pgsz_mask;
472         unsigned long           tsb_base;
473         unsigned long           resv;
474 };
475 #endif
476 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET    0x00
477 #define HV_TSB_DESCR_ASSOC_OFFSET       0x02
478 #define HV_TSB_DESCR_NUM_TTES_OFFSET    0x04
479 #define HV_TSB_DESCR_CTX_IDX_OFFSET     0x08
480 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET   0x0c
481 #define HV_TSB_DESCR_TSB_BASE_OFFSET    0x10
482 #define HV_TSB_DESCR_RESV_OFFSET        0x18
483 
484 /* Page size bitmask.  */
485 #define HV_PGSZ_MASK_8K                 (1 << 0)
486 #define HV_PGSZ_MASK_64K                (1 << 1)
487 #define HV_PGSZ_MASK_512K               (1 << 2)
488 #define HV_PGSZ_MASK_4MB                (1 << 3)
489 #define HV_PGSZ_MASK_32MB               (1 << 4)
490 #define HV_PGSZ_MASK_256MB              (1 << 5)
491 #define HV_PGSZ_MASK_2GB                (1 << 6)
492 #define HV_PGSZ_MASK_16GB               (1 << 7)
493 
494 /* Page size index.  The value given in the TSB descriptor must correspond
495  * to the smallest page size specified in the pgsz_mask page size bitmask.
496  */
497 #define HV_PGSZ_IDX_8K                  0
498 #define HV_PGSZ_IDX_64K                 1
499 #define HV_PGSZ_IDX_512K                2
500 #define HV_PGSZ_IDX_4MB                 3
501 #define HV_PGSZ_IDX_32MB                4
502 #define HV_PGSZ_IDX_256MB               5
503 #define HV_PGSZ_IDX_2GB                 6
504 #define HV_PGSZ_IDX_16GB                7
505 
506 /* MMU fault status area.
507  *
508  * MMU related faults have their status and fault address information
509  * placed into a memory region made available by privileged code.  Each
510  * virtual processor must make a mmu_fault_area_conf() call to tell the
511  * hypervisor where that processor's fault status should be stored.
512  *
513  * The fault status block is a multiple of 64-bytes and must be aligned
514  * on a 64-byte boundary.
515  */
516 #ifndef __ASSEMBLY__
517 struct hv_fault_status {
518         unsigned long           i_fault_type;
519         unsigned long           i_fault_addr;
520         unsigned long           i_fault_ctx;
521         unsigned long           i_reserved[5];
522         unsigned long           d_fault_type;
523         unsigned long           d_fault_addr;
524         unsigned long           d_fault_ctx;
525         unsigned long           d_reserved[5];
526 };
527 #endif
528 #define HV_FAULT_I_TYPE_OFFSET  0x00
529 #define HV_FAULT_I_ADDR_OFFSET  0x08
530 #define HV_FAULT_I_CTX_OFFSET   0x10
531 #define HV_FAULT_D_TYPE_OFFSET  0x40
532 #define HV_FAULT_D_ADDR_OFFSET  0x48
533 #define HV_FAULT_D_CTX_OFFSET   0x50
534 
535 #define HV_FAULT_TYPE_FAST_MISS 1
536 #define HV_FAULT_TYPE_FAST_PROT 2
537 #define HV_FAULT_TYPE_MMU_MISS  3
538 #define HV_FAULT_TYPE_INV_RA    4
539 #define HV_FAULT_TYPE_PRIV_VIOL 5
540 #define HV_FAULT_TYPE_PROT_VIOL 6
541 #define HV_FAULT_TYPE_NFO       7
542 #define HV_FAULT_TYPE_NFO_SEFF  8
543 #define HV_FAULT_TYPE_INV_VA    9
544 #define HV_FAULT_TYPE_INV_ASI   10
545 #define HV_FAULT_TYPE_NC_ATOMIC 11
546 #define HV_FAULT_TYPE_PRIV_ACT  12
547 #define HV_FAULT_TYPE_RESV1     13
548 #define HV_FAULT_TYPE_UNALIGNED 14
549 #define HV_FAULT_TYPE_INV_PGSZ  15
550 /* Values 16 --> -2 are reserved.  */
551 #define HV_FAULT_TYPE_MULTIPLE  -1
552 
553 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
554  * and mmu_{map,unmap}_perm_addr().
555  */
556 #define HV_MMU_DMMU                     0x01
557 #define HV_MMU_IMMU                     0x02
558 #define HV_MMU_ALL                      (HV_MMU_DMMU | HV_MMU_IMMU)
559 
560 /* mmu_map_addr()
561  * TRAP:        HV_MMU_MAP_ADDR_TRAP
562  * ARG0:        virtual address
563  * ARG1:        mmu context
564  * ARG2:        TTE
565  * ARG3:        flags (HV_MMU_{IMMU,DMMU})
566  * ERRORS:      EINVAL          Invalid virtual address, mmu context, or flags
567  *              EBADPGSZ        Invalid page size value
568  *              ENORADDR        Invalid real address in TTE
569  *
570  * Create a non-permanent mapping using the given TTE, virtual
571  * address, and mmu context.  The flags argument determines which
572  * (data, or instruction, or both) TLB the mapping gets loaded into.
573  *
574  * The behavior is undefined if the valid bit is clear in the TTE.
575  *
576  * Note: This API call is for privileged code to specify temporary translation
577  *       mappings without the need to create and manage a TSB.
578  */
579 
580 /* mmu_unmap_addr()
581  * TRAP:        HV_MMU_UNMAP_ADDR_TRAP
582  * ARG0:        virtual address
583  * ARG1:        mmu context
584  * ARG2:        flags (HV_MMU_{IMMU,DMMU})
585  * ERRORS:      EINVAL          Invalid virtual address, mmu context, or flags
586  *
587  * Demaps the given virtual address in the given mmu context on this
588  * CPU.  This function is intended to be used to demap pages mapped
589  * with mmu_map_addr.  This service is equivalent to invoking
590  * mmu_demap_page() with only the current CPU in the CPU list. The
591  * flags argument determines which (data, or instruction, or both) TLB
592  * the mapping gets unmapped from.
593  *
594  * Attempting to perform an unmap operation for a previously defined
595  * permanent mapping will have undefined results.
596  */
597 
598 /* mmu_tsb_ctx0()
599  * TRAP:        HV_FAST_TRAP
600  * FUNCTION:    HV_FAST_MMU_TSB_CTX0
601  * ARG0:        number of TSB descriptions
602  * ARG1:        TSB descriptions pointer
603  * RET0:        status
604  * ERRORS:      ENORADDR                Invalid TSB descriptions pointer or
605  *                                      TSB base within a descriptor
606  *              EBADALIGN               TSB descriptions pointer is not aligned
607  *                                      to an 8-byte boundary, or TSB base
608  *                                      within a descriptor is not aligned for
609  *                                      the given TSB size
610  *              EBADPGSZ                Invalid page size in a TSB descriptor
611  *              EBADTSB                 Invalid associativity or size in a TSB
612  *                                      descriptor
613  *              EINVAL                  Invalid number of TSB descriptions, or
614  *                                      invalid context index in a TSB
615  *                                      descriptor, or index page size not
616  *                                      equal to smallest page size in page
617  *                                      size bitmask field.
618  *
619  * Configures the TSBs for the current CPU for virtual addresses with
620  * context zero.  The TSB descriptions pointer is a pointer to an
621  * array of the given number of TSB descriptions.
622  *
623  * Note: The maximum number of TSBs available to a virtual CPU is given by the
624  *       mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
625  *       machine description.
626  */
627 #define HV_FAST_MMU_TSB_CTX0            0x20
628 
629 #ifndef __ASSEMBLY__
630 unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
631                                  unsigned long tsb_desc_ra);
632 #endif
633 
634 /* mmu_tsb_ctxnon0()
635  * TRAP:        HV_FAST_TRAP
636  * FUNCTION:    HV_FAST_MMU_TSB_CTXNON0
637  * ARG0:        number of TSB descriptions
638  * ARG1:        TSB descriptions pointer
639  * RET0:        status
640  * ERRORS:      Same as for mmu_tsb_ctx0() above.
641  *
642  * Configures the TSBs for the current CPU for virtual addresses with
643  * non-zero contexts.  The TSB descriptions pointer is a pointer to an
644  * array of the given number of TSB descriptions.
645  *
646  * Note: A maximum of 16 TSBs may be specified in the TSB description list.
647  */
648 #define HV_FAST_MMU_TSB_CTXNON0         0x21
649 
650 /* mmu_demap_page()
651  * TRAP:        HV_FAST_TRAP
652  * FUNCTION:    HV_FAST_MMU_DEMAP_PAGE
653  * ARG0:        reserved, must be zero
654  * ARG1:        reserved, must be zero
655  * ARG2:        virtual address
656  * ARG3:        mmu context
657  * ARG4:        flags (HV_MMU_{IMMU,DMMU})
658  * RET0:        status
659  * ERRORS:      EINVAL                  Invalid virtual address, context, or
660  *                                      flags value
661  *              ENOTSUPPORTED           ARG0 or ARG1 is non-zero
662  *
663  * Demaps any page mapping of the given virtual address in the given
664  * mmu context for the current virtual CPU.  Any virtually tagged
665  * caches are guaranteed to be kept consistent.  The flags argument
666  * determines which TLB (instruction, or data, or both) participate in
667  * the operation.
668  *
669  * ARG0 and ARG1 are both reserved and must be set to zero.
670  */
671 #define HV_FAST_MMU_DEMAP_PAGE          0x22
672 
673 /* mmu_demap_ctx()
674  * TRAP:        HV_FAST_TRAP
675  * FUNCTION:    HV_FAST_MMU_DEMAP_CTX
676  * ARG0:        reserved, must be zero
677  * ARG1:        reserved, must be zero
678  * ARG2:        mmu context
679  * ARG3:        flags (HV_MMU_{IMMU,DMMU})
680  * RET0:        status
681  * ERRORS:      EINVAL                  Invalid context or flags value
682  *              ENOTSUPPORTED           ARG0 or ARG1 is non-zero
683  *
684  * Demaps all non-permanent virtual page mappings previously specified
685  * for the given context for the current virtual CPU.  Any virtual
686  * tagged caches are guaranteed to be kept consistent.  The flags
687  * argument determines which TLB (instruction, or data, or both)
688  * participate in the operation.
689  *
690  * ARG0 and ARG1 are both reserved and must be set to zero.
691  */
692 #define HV_FAST_MMU_DEMAP_CTX           0x23
693 
694 /* mmu_demap_all()
695  * TRAP:        HV_FAST_TRAP
696  * FUNCTION:    HV_FAST_MMU_DEMAP_ALL
697  * ARG0:        reserved, must be zero
698  * ARG1:        reserved, must be zero
699  * ARG2:        flags (HV_MMU_{IMMU,DMMU})
700  * RET0:        status
701  * ERRORS:      EINVAL                  Invalid flags value
702  *              ENOTSUPPORTED           ARG0 or ARG1 is non-zero
703  *
704  * Demaps all non-permanent virtual page mappings previously specified
705  * for the current virtual CPU.  Any virtual tagged caches are
706  * guaranteed to be kept consistent.  The flags argument determines
707  * which TLB (instruction, or data, or both) participate in the
708  * operation.
709  *
710  * ARG0 and ARG1 are both reserved and must be set to zero.
711  */
712 #define HV_FAST_MMU_DEMAP_ALL           0x24
713 
714 #ifndef __ASSEMBLY__
715 void sun4v_mmu_demap_all(void);
716 #endif
717 
718 /* mmu_map_perm_addr()
719  * TRAP:        HV_FAST_TRAP
720  * FUNCTION:    HV_FAST_MMU_MAP_PERM_ADDR
721  * ARG0:        virtual address
722  * ARG1:        reserved, must be zero
723  * ARG2:        TTE
724  * ARG3:        flags (HV_MMU_{IMMU,DMMU})
725  * RET0:        status
726  * ERRORS:      EINVAL                  Invalid virtual address or flags value
727  *              EBADPGSZ                Invalid page size value
728  *              ENORADDR                Invalid real address in TTE
729  *              ETOOMANY                Too many mappings (max of 8 reached)
730  *
731  * Create a permanent mapping using the given TTE and virtual address
732  * for context 0 on the calling virtual CPU.  A maximum of 8 such
733  * permanent mappings may be specified by privileged code.  Mappings
734  * may be removed with mmu_unmap_perm_addr().
735  *
736  * The behavior is undefined if a TTE with the valid bit clear is given.
737  *
738  * Note: This call is used to specify address space mappings for which
739  *       privileged code does not expect to receive misses.  For example,
740  *       this mechanism can be used to map kernel nucleus code and data.
741  */
742 #define HV_FAST_MMU_MAP_PERM_ADDR       0x25
743 
744 #ifndef __ASSEMBLY__
745 unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
746                                       unsigned long set_to_zero,
747                                       unsigned long tte,
748                                       unsigned long flags);
749 #endif
750 
751 /* mmu_fault_area_conf()
752  * TRAP:        HV_FAST_TRAP
753  * FUNCTION:    HV_FAST_MMU_FAULT_AREA_CONF
754  * ARG0:        real address
755  * RET0:        status
756  * RET1:        previous mmu fault area real address
757  * ERRORS:      ENORADDR                Invalid real address
758  *              EBADALIGN               Invalid alignment for fault area
759  *
760  * Configure the MMU fault status area for the calling CPU.  A 64-byte
761  * aligned real address specifies where MMU fault status information
762  * is placed.  The return value is the previously specified area, or 0
763  * for the first invocation.  Specifying a fault area at real address
764  * 0 is not allowed.
765  */
766 #define HV_FAST_MMU_FAULT_AREA_CONF     0x26
767 
768 /* mmu_enable()
769  * TRAP:        HV_FAST_TRAP
770  * FUNCTION:    HV_FAST_MMU_ENABLE
771  * ARG0:        enable flag
772  * ARG1:        return target address
773  * RET0:        status
774  * ERRORS:      ENORADDR                Invalid real address when disabling
775  *                                      translation.
776  *              EBADALIGN               The return target address is not
777  *                                      aligned to an instruction.
778  *              EINVAL                  The enable flag request the current
779  *                                      operating mode (e.g. disable if already
780  *                                      disabled)
781  *
782  * Enable or disable virtual address translation for the calling CPU
783  * within the virtual machine domain.  If the enable flag is zero,
784  * translation is disabled, any non-zero value will enable
785  * translation.
786  *
787  * When this function returns, the newly selected translation mode
788  * will be active.  If the mmu is being enabled, then the return
789  * target address is a virtual address else it is a real address.
790  *
791  * Upon successful completion, control will be returned to the given
792  * return target address (ie. the cpu will jump to that address).  On
793  * failure, the previous mmu mode remains and the trap simply returns
794  * as normal with the appropriate error code in RET0.
795  */
796 #define HV_FAST_MMU_ENABLE              0x27
797 
798 /* mmu_unmap_perm_addr()
799  * TRAP:        HV_FAST_TRAP
800  * FUNCTION:    HV_FAST_MMU_UNMAP_PERM_ADDR
801  * ARG0:        virtual address
802  * ARG1:        reserved, must be zero
803  * ARG2:        flags (HV_MMU_{IMMU,DMMU})
804  * RET0:        status
805  * ERRORS:      EINVAL                  Invalid virtual address or flags value
806  *              ENOMAP                  Specified mapping was not found
807  *
808  * Demaps any permanent page mapping (established via
809  * mmu_map_perm_addr()) at the given virtual address for context 0 on
810  * the current virtual CPU.  Any virtual tagged caches are guaranteed
811  * to be kept consistent.
812  */
813 #define HV_FAST_MMU_UNMAP_PERM_ADDR     0x28
814 
815 /* mmu_tsb_ctx0_info()
816  * TRAP:        HV_FAST_TRAP
817  * FUNCTION:    HV_FAST_MMU_TSB_CTX0_INFO
818  * ARG0:        max TSBs
819  * ARG1:        buffer pointer
820  * RET0:        status
821  * RET1:        number of TSBs
822  * ERRORS:      EINVAL                  Supplied buffer is too small
823  *              EBADALIGN               The buffer pointer is badly aligned
824  *              ENORADDR                Invalid real address for buffer pointer
825  *
826  * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
827  * into the provided buffer.  The size of the buffer is given in ARG1
828  * in terms of the number of TSB description entries.
829  *
830  * Upon return, RET1 always contains the number of TSB descriptions
831  * previously configured.  If zero TSBs were configured, EOK is
832  * returned with RET1 containing 0.
833  */
834 #define HV_FAST_MMU_TSB_CTX0_INFO       0x29
835 
836 /* mmu_tsb_ctxnon0_info()
837  * TRAP:        HV_FAST_TRAP
838  * FUNCTION:    HV_FAST_MMU_TSB_CTXNON0_INFO
839  * ARG0:        max TSBs
840  * ARG1:        buffer pointer
841  * RET0:        status
842  * RET1:        number of TSBs
843  * ERRORS:      EINVAL                  Supplied buffer is too small
844  *              EBADALIGN               The buffer pointer is badly aligned
845  *              ENORADDR                Invalid real address for buffer pointer
846  *
847  * Return the TSB configuration as previous defined by
848  * mmu_tsb_ctxnon0() into the provided buffer.  The size of the buffer
849  * is given in ARG1 in terms of the number of TSB description entries.
850  *
851  * Upon return, RET1 always contains the number of TSB descriptions
852  * previously configured.  If zero TSBs were configured, EOK is
853  * returned with RET1 containing 0.
854  */
855 #define HV_FAST_MMU_TSB_CTXNON0_INFO    0x2a
856 
857 /* mmu_fault_area_info()
858  * TRAP:        HV_FAST_TRAP
859  * FUNCTION:    HV_FAST_MMU_FAULT_AREA_INFO
860  * RET0:        status
861  * RET1:        fault area real address
862  * ERRORS:      No errors defined.
863  *
864  * Return the currently defined MMU fault status area for the current
865  * CPU.  The real address of the fault status area is returned in
866  * RET1, or 0 is returned in RET1 if no fault status area is defined.
867  *
868  * Note: mmu_fault_area_conf() may be called with the return value (RET1)
869  *       from this service if there is a need to save and restore the fault
870  *       area for a cpu.
871  */
872 #define HV_FAST_MMU_FAULT_AREA_INFO     0x2b
873 
874 /* Cache and Memory services. */
875 
876 /* mem_scrub()
877  * TRAP:        HV_FAST_TRAP
878  * FUNCTION:    HV_FAST_MEM_SCRUB
879  * ARG0:        real address
880  * ARG1:        length
881  * RET0:        status
882  * RET1:        length scrubbed
883  * ERRORS:      ENORADDR        Invalid real address
884  *              EBADALIGN       Start address or length are not correctly
885  *                              aligned
886  *              EINVAL          Length is zero
887  *
888  * Zero the memory contents in the range real address to real address
889  * plus length minus 1.  Also, valid ECC will be generated for that
890  * memory address range.  Scrubbing is started at the given real
891  * address, but may not scrub the entire given length.  The actual
892  * length scrubbed will be returned in RET1.
893  *
894  * The real address and length must be aligned on an 8K boundary, or
895  * contain the start address and length from a sun4v error report.
896  *
897  * Note: There are two uses for this function.  The first use is to block clear
898  *       and initialize memory and the second is to scrub an u ncorrectable
899  *       error reported via a resumable or non-resumable trap.  The second
900  *       use requires the arguments to be equal to the real address and length
901  *       provided in a sun4v memory error report.
902  */
903 #define HV_FAST_MEM_SCRUB               0x31
904 
905 /* mem_sync()
906  * TRAP:        HV_FAST_TRAP
907  * FUNCTION:    HV_FAST_MEM_SYNC
908  * ARG0:        real address
909  * ARG1:        length
910  * RET0:        status
911  * RET1:        length synced
912  * ERRORS:      ENORADDR        Invalid real address
913  *              EBADALIGN       Start address or length are not correctly
914  *                              aligned
915  *              EINVAL          Length is zero
916  *
917  * Force the next access within the real address to real address plus
918  * length minus 1 to be fetches from main system memory.  Less than
919  * the given length may be synced, the actual amount synced is
920  * returned in RET1.  The real address and length must be aligned on
921  * an 8K boundary.
922  */
923 #define HV_FAST_MEM_SYNC                0x32
924 
925 /* Time of day services.
926  *
927  * The hypervisor maintains the time of day on a per-domain basis.
928  * Changing the time of day in one domain does not affect the time of
929  * day on any other domain.
930  *
931  * Time is described by a single unsigned 64-bit word which is the
932  * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
933  * 1970).
934  */
935 
936 /* tod_get()
937  * TRAP:        HV_FAST_TRAP
938  * FUNCTION:    HV_FAST_TOD_GET
939  * RET0:        status
940  * RET1:        TOD
941  * ERRORS:      EWOULDBLOCK     TOD resource is temporarily unavailable
942  *              ENOTSUPPORTED   If TOD not supported on this platform
943  *
944  * Return the current time of day.  May block if TOD access is
945  * temporarily not possible.
946  */
947 #define HV_FAST_TOD_GET                 0x50
948 
949 #ifndef __ASSEMBLY__
950 unsigned long sun4v_tod_get(unsigned long *time);
951 #endif
952 
953 /* tod_set()
954  * TRAP:        HV_FAST_TRAP
955  * FUNCTION:    HV_FAST_TOD_SET
956  * ARG0:        TOD
957  * RET0:        status
958  * ERRORS:      EWOULDBLOCK     TOD resource is temporarily unavailable
959  *              ENOTSUPPORTED   If TOD not supported on this platform
960  *
961  * The current time of day is set to the value specified in ARG0.  May
962  * block if TOD access is temporarily not possible.
963  */
964 #define HV_FAST_TOD_SET                 0x51
965 
966 #ifndef __ASSEMBLY__
967 unsigned long sun4v_tod_set(unsigned long time);
968 #endif
969 
970 /* Console services */
971 
972 /* con_getchar()
973  * TRAP:        HV_FAST_TRAP
974  * FUNCTION:    HV_FAST_CONS_GETCHAR
975  * RET0:        status
976  * RET1:        character
977  * ERRORS:      EWOULDBLOCK     No character available.
978  *
979  * Returns a character from the console device.  If no character is
980  * available then an EWOULDBLOCK error is returned.  If a character is
981  * available, then the returned status is EOK and the character value
982  * is in RET1.
983  *
984  * A virtual BREAK is represented by the 64-bit value -1.
985  *
986  * A virtual HUP signal is represented by the 64-bit value -2.
987  */
988 #define HV_FAST_CONS_GETCHAR            0x60
989 
990 /* con_putchar()
991  * TRAP:        HV_FAST_TRAP
992  * FUNCTION:    HV_FAST_CONS_PUTCHAR
993  * ARG0:        character
994  * RET0:        status
995  * ERRORS:      EINVAL          Illegal character
996  *              EWOULDBLOCK     Output buffer currently full, would block
997  *
998  * Send a character to the console device.  Only character values
999  * between 0 and 255 may be used.  Values outside this range are
1000  * invalid except for the 64-bit value -1 which is used to send a
1001  * virtual BREAK.
1002  */
1003 #define HV_FAST_CONS_PUTCHAR            0x61
1004 
1005 /* con_read()
1006  * TRAP:        HV_FAST_TRAP
1007  * FUNCTION:    HV_FAST_CONS_READ
1008  * ARG0:        buffer real address
1009  * ARG1:        buffer size in bytes
1010  * RET0:        status
1011  * RET1:        bytes read or BREAK or HUP
1012  * ERRORS:      EWOULDBLOCK     No character available.
1013  *
1014  * Reads characters into a buffer from the console device.  If no
1015  * character is available then an EWOULDBLOCK error is returned.
1016  * If a character is available, then the returned status is EOK
1017  * and the number of bytes read into the given buffer is provided
1018  * in RET1.
1019  *
1020  * A virtual BREAK is represented by the 64-bit RET1 value -1.
1021  *
1022  * A virtual HUP signal is represented by the 64-bit RET1 value -2.
1023  *
1024  * If BREAK or HUP are indicated, no bytes were read into buffer.
1025  */
1026 #define HV_FAST_CONS_READ               0x62
1027 
1028 /* con_write()
1029  * TRAP:        HV_FAST_TRAP
1030  * FUNCTION:    HV_FAST_CONS_WRITE
1031  * ARG0:        buffer real address
1032  * ARG1:        buffer size in bytes
1033  * RET0:        status
1034  * RET1:        bytes written
1035  * ERRORS:      EWOULDBLOCK     Output buffer currently full, would block
1036  *
1037  * Send a characters in buffer to the console device.  Breaks must be
1038  * sent using con_putchar().
1039  */
1040 #define HV_FAST_CONS_WRITE              0x63
1041 
1042 #ifndef __ASSEMBLY__
1043 long sun4v_con_getchar(long *status);
1044 long sun4v_con_putchar(long c);
1045 long sun4v_con_read(unsigned long buffer,
1046                     unsigned long size,
1047                     unsigned long *bytes_read);
1048 unsigned long sun4v_con_write(unsigned long buffer,
1049                               unsigned long size,
1050                               unsigned long *bytes_written);
1051 #endif
1052 
1053 /* mach_set_soft_state()
1054  * TRAP:        HV_FAST_TRAP
1055  * FUNCTION:    HV_FAST_MACH_SET_SOFT_STATE
1056  * ARG0:        software state
1057  * ARG1:        software state description pointer
1058  * RET0:        status
1059  * ERRORS:      EINVAL          software state not valid or software state
1060  *                              description is not NULL terminated
1061  *              ENORADDR        software state description pointer is not a
1062  *                              valid real address
1063  *              EBADALIGNED     software state description is not correctly
1064  *                              aligned
1065  *
1066  * This allows the guest to report it's soft state to the hypervisor.  There
1067  * are two primary components to this state.  The first part states whether
1068  * the guest software is running or not.  The second containts optional
1069  * details specific to the software.
1070  *
1071  * The software state argument is defined below in HV_SOFT_STATE_*, and
1072  * indicates whether the guest is operating normally or in a transitional
1073  * state.
1074  *
1075  * The software state description argument is a real address of a data buffer
1076  * of size 32-bytes aligned on a 32-byte boundary.  It is treated as a NULL
1077  * terminated 7-bit ASCII string of up to 31 characters not including the
1078  * NULL termination.
1079  */
1080 #define HV_FAST_MACH_SET_SOFT_STATE     0x70
1081 #define  HV_SOFT_STATE_NORMAL            0x01
1082 #define  HV_SOFT_STATE_TRANSITION        0x02
1083 
1084 #ifndef __ASSEMBLY__
1085 unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
1086                                         unsigned long msg_string_ra);
1087 #endif
1088 
1089 /* mach_get_soft_state()
1090  * TRAP:        HV_FAST_TRAP
1091  * FUNCTION:    HV_FAST_MACH_GET_SOFT_STATE
1092  * ARG0:        software state description pointer
1093  * RET0:        status
1094  * RET1:        software state
1095  * ERRORS:      ENORADDR        software state description pointer is not a
1096  *                              valid real address
1097  *              EBADALIGNED     software state description is not correctly
1098  *                              aligned
1099  *
1100  * Retrieve the current value of the guest's software state.  The rules
1101  * for the software state pointer are the same as for mach_set_soft_state()
1102  * above.
1103  */
1104 #define HV_FAST_MACH_GET_SOFT_STATE     0x71
1105 
1106 /* svc_send()
1107  * TRAP:        HV_FAST_TRAP
1108  * FUNCTION:    HV_FAST_SVC_SEND
1109  * ARG0:        service ID
1110  * ARG1:        buffer real address
1111  * ARG2:        buffer size
1112  * RET0:        STATUS
1113  * RET1:        sent_bytes
1114  *
1115  * Be careful, all output registers are clobbered by this operation,
1116  * so for example it is not possible to save away a value in %o4
1117  * across the trap.
1118  */
1119 #define HV_FAST_SVC_SEND                0x80
1120 
1121 /* svc_recv()
1122  * TRAP:        HV_FAST_TRAP
1123  * FUNCTION:    HV_FAST_SVC_RECV
1124  * ARG0:        service ID
1125  * ARG1:        buffer real address
1126  * ARG2:        buffer size
1127  * RET0:        STATUS
1128  * RET1:        recv_bytes
1129  *
1130  * Be careful, all output registers are clobbered by this operation,
1131  * so for example it is not possible to save away a value in %o4
1132  * across the trap.
1133  */
1134 #define HV_FAST_SVC_RECV                0x81
1135 
1136 /* svc_getstatus()
1137  * TRAP:        HV_FAST_TRAP
1138  * FUNCTION:    HV_FAST_SVC_GETSTATUS
1139  * ARG0:        service ID
1140  * RET0:        STATUS
1141  * RET1:        status bits
1142  */
1143 #define HV_FAST_SVC_GETSTATUS           0x82
1144 
1145 /* svc_setstatus()
1146  * TRAP:        HV_FAST_TRAP
1147  * FUNCTION:    HV_FAST_SVC_SETSTATUS
1148  * ARG0:        service ID
1149  * ARG1:        bits to set
1150  * RET0:        STATUS
1151  */
1152 #define HV_FAST_SVC_SETSTATUS           0x83
1153 
1154 /* svc_clrstatus()
1155  * TRAP:        HV_FAST_TRAP
1156  * FUNCTION:    HV_FAST_SVC_CLRSTATUS
1157  * ARG0:        service ID
1158  * ARG1:        bits to clear
1159  * RET0:        STATUS
1160  */
1161 #define HV_FAST_SVC_CLRSTATUS           0x84
1162 
1163 #ifndef __ASSEMBLY__
1164 unsigned long sun4v_svc_send(unsigned long svc_id,
1165                              unsigned long buffer,
1166                              unsigned long buffer_size,
1167                              unsigned long *sent_bytes);
1168 unsigned long sun4v_svc_recv(unsigned long svc_id,
1169                              unsigned long buffer,
1170                              unsigned long buffer_size,
1171                              unsigned long *recv_bytes);
1172 unsigned long sun4v_svc_getstatus(unsigned long svc_id,
1173                                   unsigned long *status_bits);
1174 unsigned long sun4v_svc_setstatus(unsigned long svc_id,
1175                                   unsigned long status_bits);
1176 unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
1177                                   unsigned long status_bits);
1178 #endif
1179 
1180 /* Trap trace services.
1181  *
1182  * The hypervisor provides a trap tracing capability for privileged
1183  * code running on each virtual CPU.  Privileged code provides a
1184  * round-robin trap trace queue within which the hypervisor writes
1185  * 64-byte entries detailing hyperprivileged traps taken n behalf of
1186  * privileged code.  This is provided as a debugging capability for
1187  * privileged code.
1188  *
1189  * The trap trace control structure is 64-bytes long and placed at the
1190  * start (offset 0) of the trap trace buffer, and is described as
1191  * follows:
1192  */
1193 #ifndef __ASSEMBLY__
1194 struct hv_trap_trace_control {
1195         unsigned long           head_offset;
1196         unsigned long           tail_offset;
1197         unsigned long           __reserved[0x30 / sizeof(unsigned long)];
1198 };
1199 #endif
1200 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET  0x00
1201 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET  0x08
1202 
1203 /* The head offset is the offset of the most recently completed entry
1204  * in the trap-trace buffer.  The tail offset is the offset of the
1205  * next entry to be written.  The control structure is owned and
1206  * modified by the hypervisor.  A guest may not modify the control
1207  * structure contents.  Attempts to do so will result in undefined
1208  * behavior for the guest.
1209  *
1210  * Each trap trace buffer entry is laid out as follows:
1211  */
1212 #ifndef __ASSEMBLY__
1213 struct hv_trap_trace_entry {
1214         unsigned char   type;           /* Hypervisor or guest entry?   */
1215         unsigned char   hpstate;        /* Hyper-privileged state       */
1216         unsigned char   tl;             /* Trap level                   */
1217         unsigned char   gl;             /* Global register level        */
1218         unsigned short  tt;             /* Trap type                    */
1219         unsigned short  tag;            /* Extended trap identifier     */
1220         unsigned long   tstate;         /* Trap state                   */
1221         unsigned long   tick;           /* Tick                         */
1222         unsigned long   tpc;            /* Trap PC                      */
1223         unsigned long   f1;             /* Entry specific               */
1224         unsigned long   f2;             /* Entry specific               */
1225         unsigned long   f3;             /* Entry specific               */
1226         unsigned long   f4;             /* Entry specific               */
1227 };
1228 #endif
1229 #define HV_TRAP_TRACE_ENTRY_TYPE        0x00
1230 #define HV_TRAP_TRACE_ENTRY_HPSTATE     0x01
1231 #define HV_TRAP_TRACE_ENTRY_TL          0x02
1232 #define HV_TRAP_TRACE_ENTRY_GL          0x03
1233 #define HV_TRAP_TRACE_ENTRY_TT          0x04
1234 #define HV_TRAP_TRACE_ENTRY_TAG         0x06
1235 #define HV_TRAP_TRACE_ENTRY_TSTATE      0x08
1236 #define HV_TRAP_TRACE_ENTRY_TICK        0x10
1237 #define HV_TRAP_TRACE_ENTRY_TPC         0x18
1238 #define HV_TRAP_TRACE_ENTRY_F1          0x20
1239 #define HV_TRAP_TRACE_ENTRY_F2          0x28
1240 #define HV_TRAP_TRACE_ENTRY_F3          0x30
1241 #define HV_TRAP_TRACE_ENTRY_F4          0x38
1242 
1243 /* The type field is encoded as follows.  */
1244 #define HV_TRAP_TYPE_UNDEF              0x00 /* Entry content undefined     */
1245 #define HV_TRAP_TYPE_HV                 0x01 /* Hypervisor trap entry       */
1246 #define HV_TRAP_TYPE_GUEST              0xff /* Added via ttrace_addentry() */
1247 
1248 /* ttrace_buf_conf()
1249  * TRAP:        HV_FAST_TRAP
1250  * FUNCTION:    HV_FAST_TTRACE_BUF_CONF
1251  * ARG0:        real address
1252  * ARG1:        number of entries
1253  * RET0:        status
1254  * RET1:        number of entries
1255  * ERRORS:      ENORADDR        Invalid real address
1256  *              EINVAL          Size is too small
1257  *              EBADALIGN       Real address not aligned on 64-byte boundary
1258  *
1259  * Requests hypervisor trap tracing and declares a virtual CPU's trap
1260  * trace buffer to the hypervisor.  The real address supplies the real
1261  * base address of the trap trace queue and must be 64-byte aligned.
1262  * Specifying a value of 0 for the number of entries disables trap
1263  * tracing for the calling virtual CPU.  The buffer allocated must be
1264  * sized for a power of two number of 64-byte trap trace entries plus
1265  * an initial 64-byte control structure.
1266  *
1267  * This may be invoked any number of times so that a virtual CPU may
1268  * relocate a trap trace buffer or create "snapshots" of information.
1269  *
1270  * If the real address is illegal or badly aligned, then trap tracing
1271  * is disabled and an error is returned.
1272  *
1273  * Upon failure with EINVAL, this service call returns in RET1 the
1274  * minimum number of buffer entries required.  Upon other failures
1275  * RET1 is undefined.
1276  */
1277 #define HV_FAST_TTRACE_BUF_CONF         0x90
1278 
1279 /* ttrace_buf_info()
1280  * TRAP:        HV_FAST_TRAP
1281  * FUNCTION:    HV_FAST_TTRACE_BUF_INFO
1282  * RET0:        status
1283  * RET1:        real address
1284  * RET2:        size
1285  * ERRORS:      None defined.
1286  *
1287  * Returns the size and location of the previously declared trap-trace
1288  * buffer.  In the event that no buffer was previously defined, or the
1289  * buffer is disabled, this call will return a size of zero bytes.
1290  */
1291 #define HV_FAST_TTRACE_BUF_INFO         0x91
1292 
1293 /* ttrace_enable()
1294  * TRAP:        HV_FAST_TRAP
1295  * FUNCTION:    HV_FAST_TTRACE_ENABLE
1296  * ARG0:        enable
1297  * RET0:        status
1298  * RET1:        previous enable state
1299  * ERRORS:      EINVAL          No trap trace buffer currently defined
1300  *
1301  * Enable or disable trap tracing, and return the previous enabled
1302  * state in RET1.  Future systems may define various flags for the
1303  * enable argument (ARG0), for the moment a guest should pass
1304  * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1305  * tracing - which will ensure future compatibility.
1306  */
1307 #define HV_FAST_TTRACE_ENABLE           0x92
1308 
1309 /* ttrace_freeze()
1310  * TRAP:        HV_FAST_TRAP
1311  * FUNCTION:    HV_FAST_TTRACE_FREEZE
1312  * ARG0:        freeze
1313  * RET0:        status
1314  * RET1:        previous freeze state
1315  * ERRORS:      EINVAL          No trap trace buffer currently defined
1316  *
1317  * Freeze or unfreeze trap tracing, returning the previous freeze
1318  * state in RET1.  A guest should pass a non-zero value to freeze and
1319  * a zero value to unfreeze all tracing.  The returned previous state
1320  * is 0 for not frozen and 1 for frozen.
1321  */
1322 #define HV_FAST_TTRACE_FREEZE           0x93
1323 
1324 /* ttrace_addentry()
1325  * TRAP:        HV_TTRACE_ADDENTRY_TRAP
1326  * ARG0:        tag (16-bits)
1327  * ARG1:        data word 0
1328  * ARG2:        data word 1
1329  * ARG3:        data word 2
1330  * ARG4:        data word 3
1331  * RET0:        status
1332  * ERRORS:      EINVAL          No trap trace buffer currently defined
1333  *
1334  * Add an entry to the trap trace buffer.  Upon return only ARG0/RET0
1335  * is modified - none of the other registers holding arguments are
1336  * volatile across this hypervisor service.
1337  */
1338 
1339 /* Core dump services.
1340  *
1341  * Since the hypervisor viraulizes and thus obscures a lot of the
1342  * physical machine layout and state, traditional OS crash dumps can
1343  * be difficult to diagnose especially when the problem is a
1344  * configuration error of some sort.
1345  *
1346  * The dump services provide an opaque buffer into which the
1347  * hypervisor can place it's internal state in order to assist in
1348  * debugging such situations.  The contents are opaque and extremely
1349  * platform and hypervisor implementation specific.  The guest, during
1350  * a core dump, requests that the hypervisor update any information in
1351  * the dump buffer in preparation to being dumped as part of the
1352  * domain's memory image.
1353  */
1354 
1355 /* dump_buf_update()
1356  * TRAP:        HV_FAST_TRAP
1357  * FUNCTION:    HV_FAST_DUMP_BUF_UPDATE
1358  * ARG0:        real address
1359  * ARG1:        size
1360  * RET0:        status
1361  * RET1:        required size of dump buffer
1362  * ERRORS:      ENORADDR        Invalid real address
1363  *              EBADALIGN       Real address is not aligned on a 64-byte
1364  *                              boundary
1365  *              EINVAL          Size is non-zero but less than minimum size
1366  *                              required
1367  *              ENOTSUPPORTED   Operation not supported on current logical
1368  *                              domain
1369  *
1370  * Declare a domain dump buffer to the hypervisor.  The real address
1371  * provided for the domain dump buffer must be 64-byte aligned.  The
1372  * size specifies the size of the dump buffer and may be larger than
1373  * the minimum size specified in the machine description.  The
1374  * hypervisor will fill the dump buffer with opaque data.
1375  *
1376  * Note: A guest may elect to include dump buffer contents as part of a crash
1377  *       dump to assist with debugging.  This function may be called any number
1378  *       of times so that a guest may relocate a dump buffer, or create
1379  *       "snapshots" of any dump-buffer information.  Each call to
1380  *       dump_buf_update() atomically declares the new dump buffer to the
1381  *       hypervisor.
1382  *
1383  * A specified size of 0 unconfigures the dump buffer.  If the real
1384  * address is illegal or badly aligned, then any currently active dump
1385  * buffer is disabled and an error is returned.
1386  *
1387  * In the event that the call fails with EINVAL, RET1 contains the
1388  * minimum size requires by the hypervisor for a valid dump buffer.
1389  */
1390 #define HV_FAST_DUMP_BUF_UPDATE         0x94
1391 
1392 /* dump_buf_info()
1393  * TRAP:        HV_FAST_TRAP
1394  * FUNCTION:    HV_FAST_DUMP_BUF_INFO
1395  * RET0:        status
1396  * RET1:        real address of current dump buffer
1397  * RET2:        size of current dump buffer
1398  * ERRORS:      No errors defined.
1399  *
1400  * Return the currently configures dump buffer description.  A
1401  * returned size of 0 bytes indicates an undefined dump buffer.  In
1402  * this case the return address in RET1 is undefined.
1403  */
1404 #define HV_FAST_DUMP_BUF_INFO           0x95
1405 
1406 /* Device interrupt services.
1407  *
1408  * Device interrupts are allocated to system bus bridges by the hypervisor,
1409  * and described to OBP in the machine description.  OBP then describes
1410  * these interrupts to the OS via properties in the device tree.
1411  *
1412  * Terminology:
1413  *
1414  *      cpuid           Unique opaque value which represents a target cpu.
1415  *
1416  *      devhandle       Device handle.  It uniquely identifies a device, and
1417  *                      consistes of the lower 28-bits of the hi-cell of the
1418  *                      first entry of the device's "reg" property in the
1419  *                      OBP device tree.
1420  *
1421  *      devino          Device interrupt number.  Specifies the relative
1422  *                      interrupt number within the device.  The unique
1423  *                      combination of devhandle and devino are used to
1424  *                      identify a specific device interrupt.
1425  *
1426  *                      Note: The devino value is the same as the values in the
1427  *                            "interrupts" property or "interrupt-map" property
1428  *                            in the OBP device tree for that device.
1429  *
1430  *      sysino          System interrupt number.  A 64-bit unsigned interger
1431  *                      representing a unique interrupt within a virtual
1432  *                      machine.
1433  *
1434  *      intr_state      A flag representing the interrupt state for a given
1435  *                      sysino.  The state values are defined below.
1436  *
1437  *      intr_enabled    A flag representing the 'enabled' state for a given
1438  *                      sysino.  The enable values are defined below.
1439  */
1440 
1441 #define HV_INTR_STATE_IDLE              0 /* Nothing pending */
1442 #define HV_INTR_STATE_RECEIVED          1 /* Interrupt received by hardware */
1443 #define HV_INTR_STATE_DELIVERED         2 /* Interrupt delivered to queue */
1444 
1445 #define HV_INTR_DISABLED                0 /* sysino not enabled */
1446 #define HV_INTR_ENABLED                 1 /* sysino enabled */
1447 
1448 /* intr_devino_to_sysino()
1449  * TRAP:        HV_FAST_TRAP
1450  * FUNCTION:    HV_FAST_INTR_DEVINO2SYSINO
1451  * ARG0:        devhandle
1452  * ARG1:        devino
1453  * RET0:        status
1454  * RET1:        sysino
1455  * ERRORS:      EINVAL          Invalid devhandle/devino
1456  *
1457  * Converts a device specific interrupt number of the given
1458  * devhandle/devino into a system specific ino (sysino).
1459  */
1460 #define HV_FAST_INTR_DEVINO2SYSINO      0xa0
1461 
1462 #ifndef __ASSEMBLY__
1463 unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1464                                      unsigned long devino);
1465 #endif
1466 
1467 /* intr_getenabled()
1468  * TRAP:        HV_FAST_TRAP
1469  * FUNCTION:    HV_FAST_INTR_GETENABLED
1470  * ARG0:        sysino
1471  * RET0:        status
1472  * RET1:        intr_enabled (HV_INTR_{DISABLED,ENABLED})
1473  * ERRORS:      EINVAL          Invalid sysino
1474  *
1475  * Returns interrupt enabled state in RET1 for the interrupt defined
1476  * by the given sysino.
1477  */
1478 #define HV_FAST_INTR_GETENABLED         0xa1
1479 
1480 #ifndef __ASSEMBLY__
1481 unsigned long sun4v_intr_getenabled(unsigned long sysino);
1482 #endif
1483 
1484 /* intr_setenabled()
1485  * TRAP:        HV_FAST_TRAP
1486  * FUNCTION:    HV_FAST_INTR_SETENABLED
1487  * ARG0:        sysino
1488  * ARG1:        intr_enabled (HV_INTR_{DISABLED,ENABLED})
1489  * RET0:        status
1490  * ERRORS:      EINVAL          Invalid sysino or intr_enabled value
1491  *
1492  * Set the 'enabled' state of the interrupt sysino.
1493  */
1494 #define HV_FAST_INTR_SETENABLED         0xa2
1495 
1496 #ifndef __ASSEMBLY__
1497 unsigned long sun4v_intr_setenabled(unsigned long sysino,
1498                                     unsigned long intr_enabled);
1499 #endif
1500 
1501 /* intr_getstate()
1502  * TRAP:        HV_FAST_TRAP
1503  * FUNCTION:    HV_FAST_INTR_GETSTATE
1504  * ARG0:        sysino
1505  * RET0:        status
1506  * RET1:        intr_state (HV_INTR_STATE_*)
1507  * ERRORS:      EINVAL          Invalid sysino
1508  *
1509  * Returns current state of the interrupt defined by the given sysino.
1510  */
1511 #define HV_FAST_INTR_GETSTATE           0xa3
1512 
1513 #ifndef __ASSEMBLY__
1514 unsigned long sun4v_intr_getstate(unsigned long sysino);
1515 #endif
1516 
1517 /* intr_setstate()
1518  * TRAP:        HV_FAST_TRAP
1519  * FUNCTION:    HV_FAST_INTR_SETSTATE
1520  * ARG0:        sysino
1521  * ARG1:        intr_state (HV_INTR_STATE_*)
1522  * RET0:        status
1523  * ERRORS:      EINVAL          Invalid sysino or intr_state value
1524  *
1525  * Sets the current state of the interrupt described by the given sysino
1526  * value.
1527  *
1528  * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1529  *       interrupt for sysino.
1530  */
1531 #define HV_FAST_INTR_SETSTATE           0xa4
1532 
1533 #ifndef __ASSEMBLY__
1534 unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1535 #endif
1536 
1537 /* intr_gettarget()
1538  * TRAP:        HV_FAST_TRAP
1539  * FUNCTION:    HV_FAST_INTR_GETTARGET
1540  * ARG0:        sysino
1541  * RET0:        status
1542  * RET1:        cpuid
1543  * ERRORS:      EINVAL          Invalid sysino
1544  *
1545  * Returns CPU that is the current target of the interrupt defined by
1546  * the given sysino.  The CPU value returned is undefined if the target
1547  * has not been set via intr_settarget().
1548  */
1549 #define HV_FAST_INTR_GETTARGET          0xa5
1550 
1551 #ifndef __ASSEMBLY__
1552 unsigned long sun4v_intr_gettarget(unsigned long sysino);
1553 #endif
1554 
1555 /* intr_settarget()
1556  * TRAP:        HV_FAST_TRAP
1557  * FUNCTION:    HV_FAST_INTR_SETTARGET
1558  * ARG0:        sysino
1559  * ARG1:        cpuid
1560  * RET0:        status
1561  * ERRORS:      EINVAL          Invalid sysino
1562  *              ENOCPU          Invalid cpuid
1563  *
1564  * Set the target CPU for the interrupt defined by the given sysino.
1565  */
1566 #define HV_FAST_INTR_SETTARGET          0xa6
1567 
1568 #ifndef __ASSEMBLY__
1569 unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1570 #endif
1571 
1572 /* vintr_get_cookie()
1573  * TRAP:        HV_FAST_TRAP
1574  * FUNCTION:    HV_FAST_VINTR_GET_COOKIE
1575  * ARG0:        device handle
1576  * ARG1:        device ino
1577  * RET0:        status
1578  * RET1:        cookie
1579  */
1580 #define HV_FAST_VINTR_GET_COOKIE        0xa7
1581 
1582 /* vintr_set_cookie()
1583  * TRAP:        HV_FAST_TRAP
1584  * FUNCTION:    HV_FAST_VINTR_SET_COOKIE
1585  * ARG0:        device handle
1586  * ARG1:        device ino
1587  * ARG2:        cookie
1588  * RET0:        status
1589  */
1590 #define HV_FAST_VINTR_SET_COOKIE        0xa8
1591 
1592 /* vintr_get_valid()
1593  * TRAP:        HV_FAST_TRAP
1594  * FUNCTION:    HV_FAST_VINTR_GET_VALID
1595  * ARG0:        device handle
1596  * ARG1:        device ino
1597  * RET0:        status
1598  * RET1:        valid state
1599  */
1600 #define HV_FAST_VINTR_GET_VALID         0xa9
1601 
1602 /* vintr_set_valid()
1603  * TRAP:        HV_FAST_TRAP
1604  * FUNCTION:    HV_FAST_VINTR_SET_VALID
1605  * ARG0:        device handle
1606  * ARG1:        device ino
1607  * ARG2:        valid state
1608  * RET0:        status
1609  */
1610 #define HV_FAST_VINTR_SET_VALID         0xaa
1611 
1612 /* vintr_get_state()
1613  * TRAP:        HV_FAST_TRAP
1614  * FUNCTION:    HV_FAST_VINTR_GET_STATE
1615  * ARG0:        device handle
1616  * ARG1:        device ino
1617  * RET0:        status
1618  * RET1:        state
1619  */
1620 #define HV_FAST_VINTR_GET_STATE         0xab
1621 
1622 /* vintr_set_state()
1623  * TRAP:        HV_FAST_TRAP
1624  * FUNCTION:    HV_FAST_VINTR_SET_STATE
1625  * ARG0:        device handle
1626  * ARG1:        device ino
1627  * ARG2:        state
1628  * RET0:        status
1629  */
1630 #define HV_FAST_VINTR_SET_STATE         0xac
1631 
1632 /* vintr_get_target()
1633  * TRAP:        HV_FAST_TRAP
1634  * FUNCTION:    HV_FAST_VINTR_GET_TARGET
1635  * ARG0:        device handle
1636  * ARG1:        device ino
1637  * RET0:        status
1638  * RET1:        cpuid
1639  */
1640 #define HV_FAST_VINTR_GET_TARGET        0xad
1641 
1642 /* vintr_set_target()
1643  * TRAP:        HV_FAST_TRAP
1644  * FUNCTION:    HV_FAST_VINTR_SET_TARGET
1645  * ARG0:        device handle
1646  * ARG1:        device ino
1647  * ARG2:        cpuid
1648  * RET0:        status
1649  */
1650 #define HV_FAST_VINTR_SET_TARGET        0xae
1651 
1652 #ifndef __ASSEMBLY__
1653 unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
1654                                      unsigned long dev_ino,
1655                                      unsigned long *cookie);
1656 unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
1657                                      unsigned long dev_ino,
1658                                      unsigned long cookie);
1659 unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
1660                                     unsigned long dev_ino,
1661                                     unsigned long *valid);
1662 unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
1663                                     unsigned long dev_ino,
1664                                     unsigned long valid);
1665 unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
1666                                     unsigned long dev_ino,
1667                                     unsigned long *state);
1668 unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
1669                                     unsigned long dev_ino,
1670                                     unsigned long state);
1671 unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
1672                                      unsigned long dev_ino,
1673                                      unsigned long *cpuid);
1674 unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1675                                      unsigned long dev_ino,
1676                                      unsigned long cpuid);
1677 #endif
1678 
1679 /* PCI IO services.
1680  *
1681  * See the terminology descriptions in the device interrupt services
1682  * section above as those apply here too.  Here are terminology
1683  * definitions specific to these PCI IO services:
1684  *
1685  *      tsbnum          TSB number.  Indentifies which io-tsb is used.
1686  *                      For this version of the specification, tsbnum
1687  *                      must be zero.
1688  *
1689  *      tsbindex        TSB index.  Identifies which entry in the TSB
1690  *                      is used.  The first entry is zero.
1691  *
1692  *      tsbid           A 64-bit aligned data structure which contains
1693  *                      a tsbnum and a tsbindex.  Bits 63:32 contain the
1694  *                      tsbnum and bits 31:00 contain the tsbindex.
1695  *
1696  *                      Use the HV_PCI_TSBID() macro to construct such
1697  *                      values.
1698  *
1699  *      io_attributes   IO attributes for IOMMU mappings.  One of more
1700  *                      of the attritbute bits are stores in a 64-bit
1701  *                      value.  The values are defined below.
1702  *
1703  *      r_addr          64-bit real address
1704  *
1705  *      pci_device      PCI device address.  A PCI device address identifies
1706  *                      a specific device on a specific PCI bus segment.
1707  *                      A PCI device address ia a 32-bit unsigned integer
1708  *                      with the following format:
1709  *
1710  *                              00000000.bbbbbbbb.dddddfff.00000000
1711  *
1712  *                      Use the HV_PCI_DEVICE_BUILD() macro to construct
1713  *                      such values.
1714  *
1715  *      pci_config_offset
1716  *                      PCI configureation space offset.  For conventional
1717  *                      PCI a value between 0 and 255.  For extended
1718  *                      configuration space, a value between 0 and 4095.
1719  *
1720  *                      Note: For PCI configuration space accesses, the offset
1721  *                            must be aligned to the access size.
1722  *
1723  *      error_flag      A return value which specifies if the action succeeded
1724  *                      or failed.  0 means no error, non-0 means some error
1725  *                      occurred while performing the service.
1726  *
1727  *      io_sync_direction
1728  *                      Direction definition for pci_dma_sync(), defined
1729  *                      below in HV_PCI_SYNC_*.
1730  *
1731  *      io_page_list    A list of io_page_addresses, an io_page_address is
1732  *                      a real address.
1733  *
1734  *      io_page_list_p  A pointer to an io_page_list.
1735  *
1736  *      "size based byte swap" - Some functions do size based byte swapping
1737  *                               which allows sw to access pointers and
1738  *                               counters in native form when the processor
1739  *                               operates in a different endianness than the
1740  *                               IO bus.  Size-based byte swapping converts a
1741  *                               multi-byte field between big-endian and
1742  *                               little-endian format.
1743  */
1744 
1745 #define HV_PCI_MAP_ATTR_READ            0x01
1746 #define HV_PCI_MAP_ATTR_WRITE           0x02
1747 
1748 #define HV_PCI_DEVICE_BUILD(b,d,f)      \
1749         ((((b) & 0xff) << 16) | \
1750          (((d) & 0x1f) << 11) | \
1751          (((f) & 0x07) <<  8))
1752 
1753 #define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1754         ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1755 
1756 #define HV_PCI_SYNC_FOR_DEVICE          0x01
1757 #define HV_PCI_SYNC_FOR_CPU             0x02
1758 
1759 /* pci_iommu_map()
1760  * TRAP:        HV_FAST_TRAP
1761  * FUNCTION:    HV_FAST_PCI_IOMMU_MAP
1762  * ARG0:        devhandle
1763  * ARG1:        tsbid
1764  * ARG2:        #ttes
1765  * ARG3:        io_attributes
1766  * ARG4:        io_page_list_p
1767  * RET0:        status
1768  * RET1:        #ttes mapped
1769  * ERRORS:      EINVAL          Invalid devhandle/tsbnum/tsbindex/io_attributes
1770  *              EBADALIGN       Improperly aligned real address
1771  *              ENORADDR        Invalid real address
1772  *
1773  * Create IOMMU mappings in the sun4v device defined by the given
1774  * devhandle.  The mappings are created in the TSB defined by the
1775  * tsbnum component of the given tsbid.  The first mapping is created
1776  * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1777  * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1778  * the second at tsbnum, tsbindex + 1, etc.
1779  *
1780  * All mappings are created with the attributes defined by the io_attributes
1781  * argument.  The page mapping addresses are described in the io_page_list
1782  * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1783  * The first entry in the io_page_list is the address for the first iotte, the
1784  * 2nd for the 2nd iotte, and so on.
1785  *
1786  * Each io_page_address in the io_page_list must be appropriately aligned.
1787  * #ttes must be greater than zero.  For this version of the spec, the tsbnum
1788  * component of the given tsbid must be zero.
1789  *
1790  * Returns the actual number of mappings creates, which may be less than
1791  * or equal to the argument #ttes.  If the function returns a value which
1792  * is less than the #ttes, the caller may continus to call the function with
1793  * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1794  * mapped.
1795  *
1796  * Note: This function does not imply an iotte cache flush.  The guest must
1797  *       demap an entry before re-mapping it.
1798  */
1799 #define HV_FAST_PCI_IOMMU_MAP           0xb0
1800 
1801 /* pci_iommu_demap()
1802  * TRAP:        HV_FAST_TRAP
1803  * FUNCTION:    HV_FAST_PCI_IOMMU_DEMAP
1804  * ARG0:        devhandle
1805  * ARG1:        tsbid
1806  * ARG2:        #ttes
1807  * RET0:        status
1808  * RET1:        #ttes demapped
1809  * ERRORS:      EINVAL          Invalid devhandle/tsbnum/tsbindex
1810  *
1811  * Demap and flush IOMMU mappings in the device defined by the given
1812  * devhandle.  Demaps up to #ttes entries in the TSB defined by the tsbnum
1813  * component of the given tsbid, starting at the TSB index defined by the
1814  * tsbindex component of the given tsbid.
1815  *
1816  * For this version of the spec, the tsbnum of the given tsbid must be zero.
1817  * #ttes must be greater than zero.
1818  *
1819  * Returns the actual number of ttes demapped, which may be less than or equal
1820  * to the argument #ttes.  If #ttes demapped is less than #ttes, the caller
1821  * may continue to call this function with updated tsbid and #ttes arguments
1822  * until all pages are demapped.
1823  *
1824  * Note: Entries do not have to be mapped to be demapped.  A demap of an
1825  *       unmapped page will flush the entry from the tte cache.
1826  */
1827 #define HV_FAST_PCI_IOMMU_DEMAP         0xb1
1828 
1829 /* pci_iommu_getmap()
1830  * TRAP:        HV_FAST_TRAP
1831  * FUNCTION:    HV_FAST_PCI_IOMMU_GETMAP
1832  * ARG0:        devhandle
1833  * ARG1:        tsbid
1834  * RET0:        status
1835  * RET1:        io_attributes
1836  * RET2:        real address
1837  * ERRORS:      EINVAL          Invalid devhandle/tsbnum/tsbindex
1838  *              ENOMAP          Mapping is not valid, no translation exists
1839  *
1840  * Read and return the mapping in the device described by the given devhandle
1841  * and tsbid.  If successful, the io_attributes shall be returned in RET1
1842  * and the page address of the mapping shall be returned in RET2.
1843  *
1844  * For this version of the spec, the tsbnum component of the given tsbid
1845  * must be zero.
1846  */
1847 #define HV_FAST_PCI_IOMMU_GETMAP        0xb2
1848 
1849 /* pci_iommu_getbypass()
1850  * TRAP:        HV_FAST_TRAP
1851  * FUNCTION:    HV_FAST_PCI_IOMMU_GETBYPASS
1852  * ARG0:        devhandle
1853  * ARG1:        real address
1854  * ARG2:        io_attributes
1855  * RET0:        status
1856  * RET1:        io_addr
1857  * ERRORS:      EINVAL          Invalid devhandle/io_attributes
1858  *              ENORADDR        Invalid real address
1859  *              ENOTSUPPORTED   Function not supported in this implementation.
1860  *
1861  * Create a "special" mapping in the device described by the given devhandle,
1862  * for the given real address and attributes.  Return the IO address in RET1
1863  * if successful.
1864  */
1865 #define HV_FAST_PCI_IOMMU_GETBYPASS     0xb3
1866 
1867 /* pci_config_get()
1868  * TRAP:        HV_FAST_TRAP
1869  * FUNCTION:    HV_FAST_PCI_CONFIG_GET
1870  * ARG0:        devhandle
1871  * ARG1:        pci_device
1872  * ARG2:        pci_config_offset
1873  * ARG3:        size
1874  * RET0:        status
1875  * RET1:        error_flag
1876  * RET2:        data
1877  * ERRORS:      EINVAL          Invalid devhandle/pci_device/offset/size
1878  *              EBADALIGN       pci_config_offset not size aligned
1879  *              ENOACCESS       Access to this offset is not permitted
1880  *
1881  * Read PCI configuration space for the adapter described by the given
1882  * devhandle.  Read size (1, 2, or 4) bytes of data from the given
1883  * pci_device, at pci_config_offset from the beginning of the device's
1884  * configuration space.  If there was no error, RET1 is set to zero and
1885  * RET2 is set to the data read.  Insignificant bits in RET2 are not
1886  * guaranteed to have any specific value and therefore must be ignored.
1887  *
1888  * The data returned in RET2 is size based byte swapped.
1889  *
1890  * If an error occurs during the read, set RET1 to a non-zero value.  The
1891  * given pci_config_offset must be 'size' aligned.
1892  */
1893 #define HV_FAST_PCI_CONFIG_GET          0xb4
1894 
1895 /* pci_config_put()
1896  * TRAP:        HV_FAST_TRAP
1897  * FUNCTION:    HV_FAST_PCI_CONFIG_PUT
1898  * ARG0:        devhandle
1899  * ARG1:        pci_device
1900  * ARG2:        pci_config_offset
1901  * ARG3:        size
1902  * ARG4:        data
1903  * RET0:        status
1904  * RET1:        error_flag
1905  * ERRORS:      EINVAL          Invalid devhandle/pci_device/offset/size
1906  *              EBADALIGN       pci_config_offset not size aligned
1907  *              ENOACCESS       Access to this offset is not permitted
1908  *
1909  * Write PCI configuration space for the adapter described by the given
1910  * devhandle.  Write size (1, 2, or 4) bytes of data in a single operation,
1911  * at pci_config_offset from the beginning of the device's configuration
1912  * space.  The data argument contains the data to be written to configuration
1913  * space.  Prior to writing, the data is size based byte swapped.
1914  *
1915  * If an error occurs during the write access, do not generate an error
1916  * report, do set RET1 to a non-zero value.  Otherwise RET1 is zero.
1917  * The given pci_config_offset must be 'size' aligned.
1918  *
1919  * This function is permitted to read from offset zero in the configuration
1920  * space described by the given pci_device if necessary to ensure that the
1921  * write access to config space completes.
1922  */
1923 #define HV_FAST_PCI_CONFIG_PUT          0xb5
1924 
1925 /* pci_peek()
1926  * TRAP:        HV_FAST_TRAP
1927  * FUNCTION:    HV_FAST_PCI_PEEK
1928  * ARG0:        devhandle
1929  * ARG1:        real address
1930  * ARG2:        size
1931  * RET0:        status
1932  * RET1:        error_flag
1933  * RET2:        data
1934  * ERRORS:      EINVAL          Invalid devhandle or size
1935  *              EBADALIGN       Improperly aligned real address
1936  *              ENORADDR        Bad real address
1937  *              ENOACCESS       Guest access prohibited
1938  *
1939  * Attempt to read the IO address given by the given devhandle, real address,
1940  * and size.  Size must be 1, 2, 4, or 8.  The read is performed as a single
1941  * access operation using the given size.  If an error occurs when reading
1942  * from the given location, do not generate an error report, but return a
1943  * non-zero value in RET1.  If the read was successful, return zero in RET1
1944  * and return the actual data read in RET2.  The data returned is size based
1945  * byte swapped.
1946  *
1947  * Non-significant bits in RET2 are not guaranteed to have any specific value
1948  * and therefore must be ignored.  If RET1 is returned as non-zero, the data
1949  * value is not guaranteed to have any specific value and should be ignored.
1950  *
1951  * The caller must have permission to read from the given devhandle, real
1952  * address, which must be an IO address.  The argument real address must be a
1953  * size aligned address.
1954  *
1955  * The hypervisor implementation of this function must block access to any
1956  * IO address that the guest does not have explicit permission to access.
1957  */
1958 #define HV_FAST_PCI_PEEK                0xb6
1959 
1960 /* pci_poke()
1961  * TRAP:        HV_FAST_TRAP
1962  * FUNCTION:    HV_FAST_PCI_POKE
1963  * ARG0:        devhandle
1964  * ARG1:        real address
1965  * ARG2:        size
1966  * ARG3:        data
1967  * ARG4:        pci_device
1968  * RET0:        status
1969  * RET1:        error_flag
1970  * ERRORS:      EINVAL          Invalid devhandle, size, or pci_device
1971  *              EBADALIGN       Improperly aligned real address
1972  *              ENORADDR        Bad real address
1973  *              ENOACCESS       Guest access prohibited
1974  *              ENOTSUPPORTED   Function is not supported by implementation
1975  *
1976  * Attempt to write data to the IO address given by the given devhandle,
1977  * real address, and size.  Size must be 1, 2, 4, or 8.  The write is
1978  * performed as a single access operation using the given size. Prior to
1979  * writing the data is size based swapped.
1980  *
1981  * If an error occurs when writing to the given location, do not generate an
1982  * error report, but return a non-zero value in RET1.  If the write was
1983  * successful, return zero in RET1.
1984  *
1985  * pci_device describes the configuration address of the device being
1986  * written to.  The implementation may safely read from offset 0 with
1987  * the configuration space of the device described by devhandle and
1988  * pci_device in order to guarantee that the write portion of the operation
1989  * completes
1990  *
1991  * Any error that occurs due to the read shall be reported using the normal
1992  * error reporting mechanisms .. the read error is not suppressed.
1993  *
1994  * The caller must have permission to write to the given devhandle, real
1995  * address, which must be an IO address.  The argument real address must be a
1996  * size aligned address.  The caller must have permission to read from
1997  * the given devhandle, pci_device cofiguration space offset 0.
1998  *
1999  * The hypervisor implementation of this function must block access to any
2000  * IO address that the guest does not have explicit permission to access.
2001  */
2002 #define HV_FAST_PCI_POKE                0xb7
2003 
2004 /* pci_dma_sync()
2005  * TRAP:        HV_FAST_TRAP
2006  * FUNCTION:    HV_FAST_PCI_DMA_SYNC
2007  * ARG0:        devhandle
2008  * ARG1:        real address
2009  * ARG2:        size
2010  * ARG3:        io_sync_direction
2011  * RET0:        status
2012  * RET1:        #synced
2013  * ERRORS:      EINVAL          Invalid devhandle or io_sync_direction
2014  *              ENORADDR        Bad real address
2015  *
2016  * Synchronize a memory region described by the given real address and size,
2017  * for the device defined by the given devhandle using the direction(s)
2018  * defined by the given io_sync_direction.  The argument size is the size of
2019  * the memory region in bytes.
2020  *
2021  * Return the actual number of bytes synchronized in the return value #synced,
2022  * which may be less than or equal to the argument size.  If the return
2023  * value #synced is less than size, the caller must continue to call this
2024  * function with updated real address and size arguments until the entire
2025  * memory region is synchronized.
2026  */
2027 #define HV_FAST_PCI_DMA_SYNC            0xb8
2028 
2029 /* PCI MSI services.  */
2030 
2031 #define HV_MSITYPE_MSI32                0x00
2032 #define HV_MSITYPE_MSI64                0x01
2033 
2034 #define HV_MSIQSTATE_IDLE               0x00
2035 #define HV_MSIQSTATE_ERROR              0x01
2036 
2037 #define HV_MSIQ_INVALID                 0x00
2038 #define HV_MSIQ_VALID                   0x01
2039 
2040 #define HV_MSISTATE_IDLE                0x00
2041 #define HV_MSISTATE_DELIVERED           0x01
2042 
2043 #define HV_MSIVALID_INVALID             0x00
2044 #define HV_MSIVALID_VALID               0x01
2045 
2046 #define HV_PCIE_MSGTYPE_PME_MSG         0x18
2047 #define HV_PCIE_MSGTYPE_PME_ACK_MSG     0x1b
2048 #define HV_PCIE_MSGTYPE_CORR_MSG        0x30
2049 #define HV_PCIE_MSGTYPE_NONFATAL_MSG    0x31
2050 #define HV_PCIE_MSGTYPE_FATAL_MSG       0x33
2051 
2052 #define HV_MSG_INVALID                  0x00
2053 #define HV_MSG_VALID                    0x01
2054 
2055 /* pci_msiq_conf()
2056  * TRAP:        HV_FAST_TRAP
2057  * FUNCTION:    HV_FAST_PCI_MSIQ_CONF
2058  * ARG0:        devhandle
2059  * ARG1:        msiqid
2060  * ARG2:        real address
2061  * ARG3:        number of entries
2062  * RET0:        status
2063  * ERRORS:      EINVAL          Invalid devhandle, msiqid or nentries
2064  *              EBADALIGN       Improperly aligned real address
2065  *              ENORADDR        Bad real address
2066  *
2067  * Configure the MSI queue given by the devhandle and msiqid arguments,
2068  * and to be placed at the given real address and be of the given
2069  * number of entries.  The real address must be aligned exactly to match
2070  * the queue size.  Each queue entry is 64-bytes long, so f.e. a 32 entry
2071  * queue must be aligned on a 2048 byte real address boundary.  The MSI-EQ
2072  * Head and Tail are initialized so that the MSI-EQ is 'empty'.
2073  *
2074  * Implementation Note: Certain implementations have fixed sized queues.  In
2075  *                      that case, number of entries must contain the correct
2076  *                      value.
2077  */
2078 #define HV_FAST_PCI_MSIQ_CONF           0xc0
2079 
2080 /* pci_msiq_info()
2081  * TRAP:        HV_FAST_TRAP
2082  * FUNCTION:    HV_FAST_PCI_MSIQ_INFO
2083  * ARG0:        devhandle
2084  * ARG1:        msiqid
2085  * RET0:        status
2086  * RET1:        real address
2087  * RET2:        number of entries
2088  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2089  *
2090  * Return the configuration information for the MSI queue described
2091  * by the given devhandle and msiqid.  The base address of the queue
2092  * is returned in ARG1 and the number of entries is returned in ARG2.
2093  * If the queue is unconfigured, the real address is undefined and the
2094  * number of entries will be returned as zero.
2095  */
2096 #define HV_FAST_PCI_MSIQ_INFO           0xc1
2097 
2098 /* pci_msiq_getvalid()
2099  * TRAP:        HV_FAST_TRAP
2100  * FUNCTION:    HV_FAST_PCI_MSIQ_GETVALID
2101  * ARG0:        devhandle
2102  * ARG1:        msiqid
2103  * RET0:        status
2104  * RET1:        msiqvalid       (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2105  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2106  *
2107  * Get the valid state of the MSI-EQ described by the given devhandle and
2108  * msiqid.
2109  */
2110 #define HV_FAST_PCI_MSIQ_GETVALID       0xc2
2111 
2112 /* pci_msiq_setvalid()
2113  * TRAP:        HV_FAST_TRAP
2114  * FUNCTION:    HV_FAST_PCI_MSIQ_SETVALID
2115  * ARG0:        devhandle
2116  * ARG1:        msiqid
2117  * ARG2:        msiqvalid       (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2118  * RET0:        status
2119  * ERRORS:      EINVAL          Invalid devhandle or msiqid or msiqvalid
2120  *                              value or MSI EQ is uninitialized
2121  *
2122  * Set the valid state of the MSI-EQ described by the given devhandle and
2123  * msiqid to the given msiqvalid.
2124  */
2125 #define HV_FAST_PCI_MSIQ_SETVALID       0xc3
2126 
2127 /* pci_msiq_getstate()
2128  * TRAP:        HV_FAST_TRAP
2129  * FUNCTION:    HV_FAST_PCI_MSIQ_GETSTATE
2130  * ARG0:        devhandle
2131  * ARG1:        msiqid
2132  * RET0:        status
2133  * RET1:        msiqstate       (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2134  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2135  *
2136  * Get the state of the MSI-EQ described by the given devhandle and
2137  * msiqid.
2138  */
2139 #define HV_FAST_PCI_MSIQ_GETSTATE       0xc4
2140 
2141 /* pci_msiq_getvalid()
2142  * TRAP:        HV_FAST_TRAP
2143  * FUNCTION:    HV_FAST_PCI_MSIQ_GETVALID
2144  * ARG0:        devhandle
2145  * ARG1:        msiqid
2146  * ARG2:        msiqstate       (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2147  * RET0:        status
2148  * ERRORS:      EINVAL          Invalid devhandle or msiqid or msiqstate
2149  *                              value or MSI EQ is uninitialized
2150  *
2151  * Set the state of the MSI-EQ described by the given devhandle and
2152  * msiqid to the given msiqvalid.
2153  */
2154 #define HV_FAST_PCI_MSIQ_SETSTATE       0xc5
2155 
2156 /* pci_msiq_gethead()
2157  * TRAP:        HV_FAST_TRAP
2158  * FUNCTION:    HV_FAST_PCI_MSIQ_GETHEAD
2159  * ARG0:        devhandle
2160  * ARG1:        msiqid
2161  * RET0:        status
2162  * RET1:        msiqhead
2163  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2164  *
2165  * Get the current MSI EQ queue head for the MSI-EQ described by the
2166  * given devhandle and msiqid.
2167  */
2168 #define HV_FAST_PCI_MSIQ_GETHEAD        0xc6
2169 
2170 /* pci_msiq_sethead()
2171  * TRAP:        HV_FAST_TRAP
2172  * FUNCTION:    HV_FAST_PCI_MSIQ_SETHEAD
2173  * ARG0:        devhandle
2174  * ARG1:        msiqid
2175  * ARG2:        msiqhead
2176  * RET0:        status
2177  * ERRORS:      EINVAL          Invalid devhandle or msiqid or msiqhead,
2178  *                              or MSI EQ is uninitialized
2179  *
2180  * Set the current MSI EQ queue head for the MSI-EQ described by the
2181  * given devhandle and msiqid.
2182  */
2183 #define HV_FAST_PCI_MSIQ_SETHEAD        0xc7
2184 
2185 /* pci_msiq_gettail()
2186  * TRAP:        HV_FAST_TRAP
2187  * FUNCTION:    HV_FAST_PCI_MSIQ_GETTAIL
2188  * ARG0:        devhandle
2189  * ARG1:        msiqid
2190  * RET0:        status
2191  * RET1:        msiqtail
2192  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2193  *
2194  * Get the current MSI EQ queue tail for the MSI-EQ described by the
2195  * given devhandle and msiqid.
2196  */
2197 #define HV_FAST_PCI_MSIQ_GETTAIL        0xc8
2198 
2199 /* pci_msi_getvalid()
2200  * TRAP:        HV_FAST_TRAP
2201  * FUNCTION:    HV_FAST_PCI_MSI_GETVALID
2202  * ARG0:        devhandle
2203  * ARG1:        msinum
2204  * RET0:        status
2205  * RET1:        msivalidstate
2206  * ERRORS:      EINVAL          Invalid devhandle or msinum
2207  *
2208  * Get the current valid/enabled state for the MSI defined by the
2209  * given devhandle and msinum.
2210  */
2211 #define HV_FAST_PCI_MSI_GETVALID        0xc9
2212 
2213 /* pci_msi_setvalid()
2214  * TRAP:        HV_FAST_TRAP
2215  * FUNCTION:    HV_FAST_PCI_MSI_SETVALID
2216  * ARG0:        devhandle
2217  * ARG1:        msinum
2218  * ARG2:        msivalidstate
2219  * RET0:        status
2220  * ERRORS:      EINVAL          Invalid devhandle or msinum or msivalidstate
2221  *
2222  * Set the current valid/enabled state for the MSI defined by the
2223  * given devhandle and msinum.
2224  */
2225 #define HV_FAST_PCI_MSI_SETVALID        0xca
2226 
2227 /* pci_msi_getmsiq()
2228  * TRAP:        HV_FAST_TRAP
2229  * FUNCTION:    HV_FAST_PCI_MSI_GETMSIQ
2230  * ARG0:        devhandle
2231  * ARG1:        msinum
2232  * RET0:        status
2233  * RET1:        msiqid
2234  * ERRORS:      EINVAL          Invalid devhandle or msinum or MSI is unbound
2235  *
2236  * Get the MSI EQ that the MSI defined by the given devhandle and
2237  * msinum is bound to.
2238  */
2239 #define HV_FAST_PCI_MSI_GETMSIQ         0xcb
2240 
2241 /* pci_msi_setmsiq()
2242  * TRAP:        HV_FAST_TRAP
2243  * FUNCTION:    HV_FAST_PCI_MSI_SETMSIQ
2244  * ARG0:        devhandle
2245  * ARG1:        msinum
2246  * ARG2:        msitype
2247  * ARG3:        msiqid
2248  * RET0:        status
2249  * ERRORS:      EINVAL          Invalid devhandle or msinum or msiqid
2250  *
2251  * Set the MSI EQ that the MSI defined by the given devhandle and
2252  * msinum is bound to.
2253  */
2254 #define HV_FAST_PCI_MSI_SETMSIQ         0xcc
2255 
2256 /* pci_msi_getstate()
2257  * TRAP:        HV_FAST_TRAP
2258  * FUNCTION:    HV_FAST_PCI_MSI_GETSTATE
2259  * ARG0:        devhandle
2260  * ARG1:        msinum
2261  * RET0:        status
2262  * RET1:        msistate
2263  * ERRORS:      EINVAL          Invalid devhandle or msinum
2264  *
2265  * Get the state of the MSI defined by the given devhandle and msinum.
2266  * If not initialized, return HV_MSISTATE_IDLE.
2267  */
2268 #define HV_FAST_PCI_MSI_GETSTATE        0xcd
2269 
2270 /* pci_msi_setstate()
2271  * TRAP:        HV_FAST_TRAP
2272  * FUNCTION:    HV_FAST_PCI_MSI_SETSTATE
2273  * ARG0:        devhandle
2274  * ARG1:        msinum
2275  * ARG2:        msistate
2276  * RET0:        status
2277  * ERRORS:      EINVAL          Invalid devhandle or msinum or msistate
2278  *
2279  * Set the state of the MSI defined by the given devhandle and msinum.
2280  */
2281 #define HV_FAST_PCI_MSI_SETSTATE        0xce
2282 
2283 /* pci_msg_getmsiq()
2284  * TRAP:        HV_FAST_TRAP
2285  * FUNCTION:    HV_FAST_PCI_MSG_GETMSIQ
2286  * ARG0:        devhandle
2287  * ARG1:        msgtype
2288  * RET0:        status
2289  * RET1:        msiqid
2290  * ERRORS:      EINVAL          Invalid devhandle or msgtype
2291  *
2292  * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2293  */
2294 #define HV_FAST_PCI_MSG_GETMSIQ         0xd0
2295 
2296 /* pci_msg_setmsiq()
2297  * TRAP:        HV_FAST_TRAP
2298  * FUNCTION:    HV_FAST_PCI_MSG_SETMSIQ
2299  * ARG0:        devhandle
2300  * ARG1:        msgtype
2301  * ARG2:        msiqid
2302  * RET0:        status
2303  * ERRORS:      EINVAL          Invalid devhandle, msgtype, or msiqid
2304  *
2305  * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2306  */
2307 #define HV_FAST_PCI_MSG_SETMSIQ         0xd1
2308 
2309 /* pci_msg_getvalid()
2310  * TRAP:        HV_FAST_TRAP
2311  * FUNCTION:    HV_FAST_PCI_MSG_GETVALID
2312  * ARG0:        devhandle
2313  * ARG1:        msgtype
2314  * RET0:        status
2315  * RET1:        msgvalidstate
2316  * ERRORS:      EINVAL          Invalid devhandle or msgtype
2317  *
2318  * Get the valid/enabled state of the MSG defined by the given
2319  * devhandle and msgtype.
2320  */
2321 #define HV_FAST_PCI_MSG_GETVALID        0xd2
2322 
2323 /* pci_msg_setvalid()
2324  * TRAP:        HV_FAST_TRAP
2325  * FUNCTION:    HV_FAST_PCI_MSG_SETVALID
2326  * ARG0:        devhandle
2327  * ARG1:        msgtype
2328  * ARG2:        msgvalidstate
2329  * RET0:        status
2330  * ERRORS:      EINVAL          Invalid devhandle or msgtype or msgvalidstate
2331  *
2332  * Set the valid/enabled state of the MSG defined by the given
2333  * devhandle and msgtype.
2334  */
2335 #define HV_FAST_PCI_MSG_SETVALID        0xd3
2336 
2337 /* Logical Domain Channel services.  */
2338 
2339 #define LDC_CHANNEL_DOWN                0
2340 #define LDC_CHANNEL_UP                  1
2341 #define LDC_CHANNEL_RESETTING           2
2342 
2343 /* ldc_tx_qconf()
2344  * TRAP:        HV_FAST_TRAP
2345  * FUNCTION:    HV_FAST_LDC_TX_QCONF
2346  * ARG0:        channel ID
2347  * ARG1:        real address base of queue
2348  * ARG2:        num entries in queue
2349  * RET0:        status
2350  *
2351  * Configure transmit queue for the LDC endpoint specified by the
2352  * given channel ID, to be placed at the given real address, and
2353  * be of the given num entries.  Num entries must be a power of two.
2354  * The real address base of the queue must be aligned on the queue
2355  * size.  Each queue entry is 64-bytes, so for example, a 32 entry
2356  * queue must be aligned on a 2048 byte real address boundary.
2357  *
2358  * Upon configuration of a valid transmit queue the head and tail
2359  * pointers are set to a hypervisor specific identical value indicating
2360  * that the queue initially is empty.
2361  *
2362  * The endpoint's transmit queue is un-configured if num entries is zero.
2363  *
2364  * The maximum number of entries for each queue for a specific cpu may be
2365  * determined from the machine description.  A transmit queue may be
2366  * specified even in the event that the LDC is down (peer endpoint has no
2367  * receive queue specified).  Transmission will begin as soon as the peer
2368  * endpoint defines a receive queue.
2369  *
2370  * It is recommended that a guest wait for a transmit queue to empty prior
2371  * to reconfiguring it, or un-configuring it.  Re or un-configuring of a
2372  * non-empty transmit queue behaves exactly as defined above, however it
2373  * is undefined as to how many of the pending entries in the original queue
2374  * will be delivered prior to the re-configuration taking effect.
2375  * Furthermore, as the queue configuration causes a reset of the head and
2376  * tail pointers there is no way for a guest to determine how many entries
2377  * have been sent after the configuration operation.
2378  */
2379 #define HV_FAST_LDC_TX_QCONF            0xe0
2380 
2381 /* ldc_tx_qinfo()
2382  * TRAP:        HV_FAST_TRAP
2383  * FUNCTION:    HV_FAST_LDC_TX_QINFO
2384  * ARG0:        channel ID
2385  * RET0:        status
2386  * RET1:        real address base of queue
2387  * RET2:        num entries in queue
2388  *
2389  * Return the configuration info for the transmit queue of LDC endpoint
2390  * defined by the given channel ID.  The real address is the currently
2391  * defined real address base of the defined queue, and num entries is the
2392  * size of the queue in terms of number of entries.
2393  *
2394  * If the specified channel ID is a valid endpoint number, but no transmit
2395  * queue has been defined this service will return success, but with num
2396  * entries set to zero and the real address will have an undefined value.
2397  */
2398 #define HV_FAST_LDC_TX_QINFO            0xe1
2399 
2400 /* ldc_tx_get_state()
2401  * TRAP:        HV_FAST_TRAP
2402  * FUNCTION:    HV_FAST_LDC_TX_GET_STATE
2403  * ARG0:        channel ID
2404  * RET0:        status
2405  * RET1:        head offset
2406  * RET2:        tail offset
2407  * RET3:        channel state
2408  *
2409  * Return the transmit state, and the head and tail queue pointers, for
2410  * the transmit queue of the LDC endpoint defined by the given channel ID.
2411  * The head and tail values are the byte offset of the head and tail
2412  * positions of the transmit queue for the specified endpoint.
2413  */
2414 #define HV_FAST_LDC_TX_GET_STATE        0xe2
2415 
2416 /* ldc_tx_set_qtail()
2417  * TRAP:        HV_FAST_TRAP
2418  * FUNCTION:    HV_FAST_LDC_TX_SET_QTAIL
2419  * ARG0:        channel ID
2420  * ARG1:        tail offset
2421  * RET0:        status
2422  *
2423  * Update the tail pointer for the transmit queue associated with the LDC
2424  * endpoint defined by the given channel ID.  The tail offset specified
2425  * must be aligned on a 64 byte boundary, and calculated so as to increase
2426  * the number of pending entries on the transmit queue.  Any attempt to
2427  * decrease the number of pending transmit queue entires is considered
2428  * an invalid tail offset and will result in an EINVAL error.
2429  *
2430  * Since the tail of the transmit queue may not be moved backwards, the
2431  * transmit queue may be flushed by configuring a new transmit queue,
2432  * whereupon the hypervisor will configure the initial transmit head and
2433  * tail pointers to be equal.
2434  */
2435 #define HV_FAST_LDC_TX_SET_QTAIL        0xe3
2436 
2437 /* ldc_rx_qconf()
2438  * TRAP:        HV_FAST_TRAP
2439  * FUNCTION:    HV_FAST_LDC_RX_QCONF
2440  * ARG0:        channel ID
2441  * ARG1:        real address base of queue
2442  * ARG2:        num entries in queue
2443  * RET0:        status
2444  *
2445  * Configure receive queue for the LDC endpoint specified by the
2446  * given channel ID, to be placed at the given real address, and
2447  * be of the given num entries.  Num entries must be a power of two.
2448  * The real address base of the queue must be aligned on the queue
2449  * size.  Each queue entry is 64-bytes, so for example, a 32 entry
2450  * queue must be aligned on a 2048 byte real address boundary.
2451  *
2452  * The endpoint's transmit queue is un-configured if num entries is zero.
2453  *
2454  * If a valid receive queue is specified for a local endpoint the LDC is
2455  * in the up state for the purpose of transmission to this endpoint.
2456  *
2457  * The maximum number of entries for each queue for a specific cpu may be
2458  * determined from the machine description.
2459  *
2460  * As receive queue configuration causes a reset of the queue's head and
2461  * tail pointers there is no way for a gues to determine how many entries
2462  * have been received between a preceding ldc_get_rx_state() API call
2463  * and the completion of the configuration operation.  It should be noted
2464  * that datagram delivery is not guaranteed via domain channels anyway,
2465  * and therefore any higher protocol should be resilient to datagram
2466  * loss if necessary.  However, to overcome this specific race potential
2467  * it is recommended, for example, that a higher level protocol be employed
2468  * to ensure either retransmission, or ensure that no datagrams are pending
2469  * on the peer endpoint's transmit queue prior to the configuration process.
2470  */
2471 #define HV_FAST_LDC_RX_QCONF            0xe4
2472 
2473 /* ldc_rx_qinfo()
2474  * TRAP:        HV_FAST_TRAP
2475  * FUNCTION:    HV_FAST_LDC_RX_QINFO
2476  * ARG0:        channel ID
2477  * RET0:        status
2478  * RET1:        real address base of queue
2479  * RET2:        num entries in queue
2480  *
2481  * Return the configuration info for the receive queue of LDC endpoint
2482  * defined by the given channel ID.  The real address is the currently
2483  * defined real address base of the defined queue, and num entries is the
2484  * size of the queue in terms of number of entries.
2485  *
2486  * If the specified channel ID is a valid endpoint number, but no receive
2487  * queue has been defined this service will return success, but with num
2488  * entries set to zero and the real address will have an undefined value.
2489  */
2490 #define HV_FAST_LDC_RX_QINFO            0xe5
2491 
2492 /* ldc_rx_get_state()
2493  * TRAP:        HV_FAST_TRAP
2494  * FUNCTION:    HV_FAST_LDC_RX_GET_STATE
2495  * ARG0:        channel ID
2496  * RET0:        status
2497  * RET1:        head offset
2498  * RET2:        tail offset
2499  * RET3:        channel state
2500  *
2501  * Return the receive state, and the head and tail queue pointers, for
2502  * the receive queue of the LDC endpoint defined by the given channel ID.
2503  * The head and tail values are the byte offset of the head and tail
2504  * positions of the receive queue for the specified endpoint.
2505  */
2506 #define HV_FAST_LDC_RX_GET_STATE        0xe6
2507 
2508 /* ldc_rx_set_qhead()
2509  * TRAP:        HV_FAST_TRAP
2510  * FUNCTION:    HV_FAST_LDC_RX_SET_QHEAD
2511  * ARG0:        channel ID
2512  * ARG1:        head offset
2513  * RET0:        status
2514  *
2515  * Update the head pointer for the receive queue associated with the LDC
2516  * endpoint defined by the given channel ID.  The head offset specified
2517  * must be aligned on a 64 byte boundary, and calculated so as to decrease
2518  * the number of pending entries on the receive queue.  Any attempt to
2519  * increase the number of pending receive queue entires is considered
2520  * an invalid head offset and will result in an EINVAL error.
2521  *
2522  * The receive queue may be flushed by setting the head offset equal
2523  * to the current tail offset.
2524  */
2525 #define HV_FAST_LDC_RX_SET_QHEAD        0xe7
2526 
2527 /* LDC Map Table Entry.  Each slot is defined by a translation table
2528  * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
2529  * hypervisor invalidation cookie.
2530  */
2531 #define LDC_MTE_PADDR   0x0fffffffffffe000 /* pa[55:13]          */
2532 #define LDC_MTE_COPY_W  0x0000000000000400 /* copy write access  */
2533 #define LDC_MTE_COPY_R  0x0000000000000200 /* copy read access   */
2534 #define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
2535 #define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access  */
2536 #define LDC_MTE_EXEC    0x0000000000000040 /* execute            */
2537 #define LDC_MTE_WRITE   0x0000000000000020 /* read               */
2538 #define LDC_MTE_READ    0x0000000000000010 /* write              */
2539 #define LDC_MTE_SZALL   0x000000000000000f /* page size bits     */
2540 #define LDC_MTE_SZ16GB  0x0000000000000007 /* 16GB page          */
2541 #define LDC_MTE_SZ2GB   0x0000000000000006 /* 2GB page           */
2542 #define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page         */
2543 #define LDC_MTE_SZ32MB  0x0000000000000004 /* 32MB page          */
2544 #define LDC_MTE_SZ4MB   0x0000000000000003 /* 4MB page           */
2545 #define LDC_MTE_SZ512K  0x0000000000000002 /* 512K page          */
2546 #define LDC_MTE_SZ64K   0x0000000000000001 /* 64K page           */
2547 #define LDC_MTE_SZ8K    0x0000000000000000 /* 8K page            */
2548 
2549 #ifndef __ASSEMBLY__
2550 struct ldc_mtable_entry {
2551         unsigned long   mte;
2552         unsigned long   cookie;
2553 };
2554 #endif
2555 
2556 /* ldc_set_map_table()
2557  * TRAP:        HV_FAST_TRAP
2558  * FUNCTION:    HV_FAST_LDC_SET_MAP_TABLE
2559  * ARG0:        channel ID
2560  * ARG1:        table real address
2561  * ARG2:        num entries
2562  * RET0:        status
2563  *
2564  * Register the MTE table at the given table real address, with the
2565  * specified num entries, for the LDC indicated by the given channel
2566  * ID.
2567  */
2568 #define HV_FAST_LDC_SET_MAP_TABLE       0xea
2569 
2570 /* ldc_get_map_table()
2571  * TRAP:        HV_FAST_TRAP
2572  * FUNCTION:    HV_FAST_LDC_GET_MAP_TABLE
2573  * ARG0:        channel ID
2574  * RET0:        status
2575  * RET1:        table real address
2576  * RET2:        num entries
2577  *
2578  * Return the configuration of the current mapping table registered
2579  * for the given channel ID.
2580  */
2581 #define HV_FAST_LDC_GET_MAP_TABLE       0xeb
2582 
2583 #define LDC_COPY_IN     0
2584 #define LDC_COPY_OUT    1
2585 
2586 /* ldc_copy()
2587  * TRAP:        HV_FAST_TRAP
2588  * FUNCTION:    HV_FAST_LDC_COPY
2589  * ARG0:        channel ID
2590  * ARG1:        LDC_COPY_* direction code
2591  * ARG2:        target real address
2592  * ARG3:        local real address
2593  * ARG4:        length in bytes
2594  * RET0:        status
2595  * RET1:        actual length in bytes
2596  */
2597 #define HV_FAST_LDC_COPY                0xec
2598 
2599 #define LDC_MEM_READ    1
2600 #define LDC_MEM_WRITE   2
2601 #define LDC_MEM_EXEC    4
2602 
2603 /* ldc_mapin()
2604  * TRAP:        HV_FAST_TRAP
2605  * FUNCTION:    HV_FAST_LDC_MAPIN
2606  * ARG0:        channel ID
2607  * ARG1:        cookie
2608  * RET0:        status
2609  * RET1:        real address
2610  * RET2:        LDC_MEM_* permissions
2611  */
2612 #define HV_FAST_LDC_MAPIN               0xed
2613 
2614 /* ldc_unmap()
2615  * TRAP:        HV_FAST_TRAP
2616  * FUNCTION:    HV_FAST_LDC_UNMAP
2617  * ARG0:        real address
2618  * RET0:        status
2619  */
2620 #define HV_FAST_LDC_UNMAP               0xee
2621 
2622 /* ldc_revoke()
2623  * TRAP:        HV_FAST_TRAP
2624  * FUNCTION:    HV_FAST_LDC_REVOKE
2625  * ARG0:        channel ID
2626  * ARG1:        cookie
2627  * ARG2:        ldc_mtable_entry cookie
2628  * RET0:        status
2629  */
2630 #define HV_FAST_LDC_REVOKE              0xef
2631 
2632 #ifndef __ASSEMBLY__
2633 unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
2634                                  unsigned long ra,
2635                                  unsigned long num_entries);
2636 unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
2637                                  unsigned long *ra,
2638                                  unsigned long *num_entries);
2639 unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
2640                                      unsigned long *head_off,
2641                                      unsigned long *tail_off,
2642                                      unsigned long *chan_state);
2643 unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
2644                                      unsigned long tail_off);
2645 unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
2646                                  unsigned long ra,
2647                                  unsigned long num_entries);
2648 unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
2649                                  unsigned long *ra,
2650                                  unsigned long *num_entries);
2651 unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
2652                                      unsigned long *head_off,
2653                                      unsigned long *tail_off,
2654                                      unsigned long *chan_state);
2655 unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
2656                                      unsigned long head_off);
2657 unsigned long sun4v_ldc_set_map_table(unsigned long channel,
2658                                       unsigned long ra,
2659                                       unsigned long num_entries);
2660 unsigned long sun4v_ldc_get_map_table(unsigned long channel,
2661                                       unsigned long *ra,
2662                                       unsigned long *num_entries);
2663 unsigned long sun4v_ldc_copy(unsigned long channel,
2664                              unsigned long dir_code,
2665                              unsigned long tgt_raddr,
2666                              unsigned long lcl_raddr,
2667                              unsigned long len,
2668                              unsigned long *actual_len);
2669 unsigned long sun4v_ldc_mapin(unsigned long channel,
2670                               unsigned long cookie,
2671                               unsigned long *ra,
2672                               unsigned long *perm);
2673 unsigned long sun4v_ldc_unmap(unsigned long ra);
2674 unsigned long sun4v_ldc_revoke(unsigned long channel,
2675                                unsigned long cookie,
2676                                unsigned long mte_cookie);
2677 #endif
2678 
2679 /* Performance counter services.  */
2680 
2681 #define HV_PERF_JBUS_PERF_CTRL_REG      0x00
2682 #define HV_PERF_JBUS_PERF_CNT_REG       0x01
2683 #define HV_PERF_DRAM_PERF_CTRL_REG_0    0x02
2684 #define HV_PERF_DRAM_PERF_CNT_REG_0     0x03
2685 #define HV_PERF_DRAM_PERF_CTRL_REG_1    0x04
2686 #define HV_PERF_DRAM_PERF_CNT_REG_1     0x05
2687 #define HV_PERF_DRAM_PERF_CTRL_REG_2    0x06
2688 #define HV_PERF_DRAM_PERF_CNT_REG_2     0x07
2689 #define HV_PERF_DRAM_PERF_CTRL_REG_3    0x08
2690 #define HV_PERF_DRAM_PERF_CNT_REG_3     0x09
2691 
2692 /* get_perfreg()
2693  * TRAP:        HV_FAST_TRAP
2694  * FUNCTION:    HV_FAST_GET_PERFREG
2695  * ARG0:        performance reg number
2696  * RET0:        status
2697  * RET1:        performance reg value
2698  * ERRORS:      EINVAL          Invalid performance register number
2699  *              ENOACCESS       No access allowed to performance counters
2700  *
2701  * Read the value of the given DRAM/JBUS performance counter/control register.
2702  */
2703 #define HV_FAST_GET_PERFREG             0x100
2704 
2705 /* set_perfreg()
2706  * TRAP:        HV_FAST_TRAP
2707  * FUNCTION:    HV_FAST_SET_PERFREG
2708  * ARG0:        performance reg number
2709  * ARG1:        performance reg value
2710  * RET0:        status
2711  * ERRORS:      EINVAL          Invalid performance register number
2712  *              ENOACCESS       No access allowed to performance counters
2713  *
2714  * Write the given performance reg value to the given DRAM/JBUS
2715  * performance counter/control register.
2716  */
2717 #define HV_FAST_SET_PERFREG             0x101
2718 
2719 #define HV_N2_PERF_SPARC_CTL            0x0
2720 #define HV_N2_PERF_DRAM_CTL0            0x1
2721 #define HV_N2_PERF_DRAM_CNT0            0x2
2722 #define HV_N2_PERF_DRAM_CTL1            0x3
2723 #define HV_N2_PERF_DRAM_CNT1            0x4
2724 #define HV_N2_PERF_DRAM_CTL2            0x5
2725 #define HV_N2_PERF_DRAM_CNT2            0x6
2726 #define HV_N2_PERF_DRAM_CTL3            0x7
2727 #define HV_N2_PERF_DRAM_CNT3            0x8
2728 
2729 #define HV_FAST_N2_GET_PERFREG          0x104
2730 #define HV_FAST_N2_SET_PERFREG          0x105
2731 
2732 #ifndef __ASSEMBLY__
2733 unsigned long sun4v_niagara_getperf(unsigned long reg,
2734                                     unsigned long *val);
2735 unsigned long sun4v_niagara_setperf(unsigned long reg,
2736                                     unsigned long val);
2737 unsigned long sun4v_niagara2_getperf(unsigned long reg,
2738                                      unsigned long *val);
2739 unsigned long sun4v_niagara2_setperf(unsigned long reg,
2740                                      unsigned long val);
2741 #endif
2742 
2743 /* MMU statistics services.
2744  *
2745  * The hypervisor maintains MMU statistics and privileged code provides
2746  * a buffer where these statistics can be collected.  It is continually
2747  * updated once configured.  The layout is as follows:
2748  */
2749 #ifndef __ASSEMBLY__
2750 struct hv_mmu_statistics {
2751         unsigned long immu_tsb_hits_ctx0_8k_tte;
2752         unsigned long immu_tsb_ticks_ctx0_8k_tte;
2753         unsigned long immu_tsb_hits_ctx0_64k_tte;
2754         unsigned long immu_tsb_ticks_ctx0_64k_tte;
2755         unsigned long __reserved1[2];
2756         unsigned long immu_tsb_hits_ctx0_4mb_tte;
2757         unsigned long immu_tsb_ticks_ctx0_4mb_tte;
2758         unsigned long __reserved2[2];
2759         unsigned long immu_tsb_hits_ctx0_256mb_tte;
2760         unsigned long immu_tsb_ticks_ctx0_256mb_tte;
2761         unsigned long __reserved3[4];
2762         unsigned long immu_tsb_hits_ctxnon0_8k_tte;
2763         unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
2764         unsigned long immu_tsb_hits_ctxnon0_64k_tte;
2765         unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
2766         unsigned long __reserved4[2];
2767         unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
2768         unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
2769         unsigned long __reserved5[2];
2770         unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
2771         unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
2772         unsigned long __reserved6[4];
2773         unsigned long dmmu_tsb_hits_ctx0_8k_tte;
2774         unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
2775         unsigned long dmmu_tsb_hits_ctx0_64k_tte;
2776         unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
2777         unsigned long __reserved7[2];
2778         unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
2779         unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
2780         unsigned long __reserved8[2];
2781         unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
2782         unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
2783         unsigned long __reserved9[4];
2784         unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
2785         unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
2786         unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
2787         unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
2788         unsigned long __reserved10[2];
2789         unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
2790         unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
2791         unsigned long __reserved11[2];
2792         unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
2793         unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
2794         unsigned long __reserved12[4];
2795 };
2796 #endif
2797 
2798 /* mmustat_conf()
2799  * TRAP:        HV_FAST_TRAP
2800  * FUNCTION:    HV_FAST_MMUSTAT_CONF
2801  * ARG0:        real address
2802  * RET0:        status
2803  * RET1:        real address
2804  * ERRORS:      ENORADDR        Invalid real address
2805  *              EBADALIGN       Real address not aligned on 64-byte boundary
2806  *              EBADTRAP        API not supported on this processor
2807  *
2808  * Enable MMU statistic gathering using the buffer at the given real
2809  * address on the current virtual CPU.  The new buffer real address
2810  * is given in ARG1, and the previously specified buffer real address
2811  * is returned in RET1, or is returned as zero for the first invocation.
2812  *
2813  * If the passed in real address argument is zero, this will disable
2814  * MMU statistic collection on the current virtual CPU.  If an error is
2815  * returned then no statistics are collected.
2816  *
2817  * The buffer contents should be initialized to all zeros before being
2818  * given to the hypervisor or else the statistics will be meaningless.
2819  */
2820 #define HV_FAST_MMUSTAT_CONF            0x102
2821 
2822 /* mmustat_info()
2823  * TRAP:        HV_FAST_TRAP
2824  * FUNCTION:    HV_FAST_MMUSTAT_INFO
2825  * RET0:        status
2826  * RET1:        real address
2827  * ERRORS:      EBADTRAP        API not supported on this processor
2828  *
2829  * Return the current state and real address of the currently configured
2830  * MMU statistics buffer on the current virtual CPU.
2831  */
2832 #define HV_FAST_MMUSTAT_INFO            0x103
2833 
2834 #ifndef __ASSEMBLY__
2835 unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
2836 unsigned long sun4v_mmustat_info(unsigned long *ra);
2837 #endif
2838 
2839 /* NCS crypto services  */
2840 
2841 /* ncs_request() sub-function numbers */
2842 #define HV_NCS_QCONF                    0x01
2843 #define HV_NCS_QTAIL_UPDATE             0x02
2844 
2845 #ifndef __ASSEMBLY__
2846 struct hv_ncs_queue_entry {
2847         /* MAU Control Register */
2848         unsigned long   mau_control;
2849 #define MAU_CONTROL_INV_PARITY  0x0000000000002000
2850 #define MAU_CONTROL_STRAND      0x0000000000001800
2851 #define MAU_CONTROL_BUSY        0x0000000000000400
2852 #define MAU_CONTROL_INT         0x0000000000000200
2853 #define MAU_CONTROL_OP          0x00000000000001c0
2854 #define MAU_CONTROL_OP_SHIFT    6
2855 #define MAU_OP_LOAD_MA_MEMORY   0x0
2856 #define MAU_OP_STORE_MA_MEMORY  0x1
2857 #define MAU_OP_MODULAR_MULT     0x2
2858 #define MAU_OP_MODULAR_REDUCE   0x3
2859 #define MAU_OP_MODULAR_EXP_LOOP 0x4
2860 #define MAU_CONTROL_LEN         0x000000000000003f
2861 #define MAU_CONTROL_LEN_SHIFT   0
2862 
2863         /* Real address of bytes to load or store bytes
2864          * into/out-of the MAU.
2865          */
2866         unsigned long   mau_mpa;
2867 
2868         /* Modular Arithmetic MA Offset Register.  */
2869         unsigned long   mau_ma;
2870 
2871         /* Modular Arithmetic N Prime Register.  */
2872         unsigned long   mau_np;
2873 };
2874 
2875 struct hv_ncs_qconf_arg {
2876         unsigned long   mid;      /* MAU ID, 1 per core on Niagara */
2877         unsigned long   base;     /* Real address base of queue */
2878         unsigned long   end;      /* Real address end of queue */
2879         unsigned long   num_ents; /* Number of entries in queue */
2880 };
2881 
2882 struct hv_ncs_qtail_update_arg {
2883         unsigned long   mid;      /* MAU ID, 1 per core on Niagara */
2884         unsigned long   tail;     /* New tail index to use */
2885         unsigned long   syncflag; /* only SYNCFLAG_SYNC is implemented */
2886 #define HV_NCS_SYNCFLAG_SYNC    0x00
2887 #define HV_NCS_SYNCFLAG_ASYNC   0x01
2888 };
2889 #endif
2890 
2891 /* ncs_request()
2892  * TRAP:        HV_FAST_TRAP
2893  * FUNCTION:    HV_FAST_NCS_REQUEST
2894  * ARG0:        NCS sub-function
2895  * ARG1:        sub-function argument real address
2896  * ARG2:        size in bytes of sub-function argument
2897  * RET0:        status
2898  *
2899  * The MAU chip of the Niagara processor is not directly accessible
2900  * to privileged code, instead it is programmed indirectly via this
2901  * hypervisor API.
2902  *
2903  * The interfaces defines a queue of MAU operations to perform.
2904  * Privileged code registers a queue with the hypervisor by invoking
2905  * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
2906  * base, end, and number of entries of the queue.  Each queue entry
2907  * contains a MAU register struct block.
2908  *
2909  * The privileged code then proceeds to add entries to the queue and
2910  * then invoke the HV_NCS_QTAIL_UPDATE sub-function.  Since only
2911  * synchronous operations are supported by the current hypervisor,
2912  * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
2913  * completion and return HV_EOK, or return an error code.
2914  *
2915  * The real address of the sub-function argument must be aligned on at
2916  * least an 8-byte boundary.
2917  *
2918  * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
2919  * offset, into the queue and must be less than or equal the 'num_ents'
2920  * argument given in the HV_NCS_QCONF call.
2921  */
2922 #define HV_FAST_NCS_REQUEST             0x110
2923 
2924 #ifndef __ASSEMBLY__
2925 unsigned long sun4v_ncs_request(unsigned long request,
2926                                 unsigned long arg_ra,
2927                                 unsigned long arg_size);
2928 #endif
2929 
2930 #define HV_FAST_FIRE_GET_PERFREG        0x120
2931 #define HV_FAST_FIRE_SET_PERFREG        0x121
2932 
2933 #define HV_FAST_REBOOT_DATA_SET         0x172
2934 
2935 #ifndef __ASSEMBLY__
2936 unsigned long sun4v_reboot_data_set(unsigned long ra,
2937                                     unsigned long len);
2938 #endif
2939 
2940 #define HV_FAST_VT_GET_PERFREG          0x184
2941 #define HV_FAST_VT_SET_PERFREG          0x185
2942 
2943 #ifndef __ASSEMBLY__
2944 unsigned long sun4v_vt_get_perfreg(unsigned long reg_num,
2945                                    unsigned long *reg_val);
2946 unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
2947                                    unsigned long reg_val);
2948 #endif
2949 
2950 #define HV_FAST_T5_GET_PERFREG          0x1a8
2951 #define HV_FAST_T5_SET_PERFREG          0x1a9
2952 
2953 #ifndef __ASSEMBLY__
2954 unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,
2955                                    unsigned long *reg_val);
2956 unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,
2957                                    unsigned long reg_val);
2958 #endif
2959 
2960 
2961 #define HV_FAST_M7_GET_PERFREG  0x43
2962 #define HV_FAST_M7_SET_PERFREG  0x44
2963 
2964 #ifndef __ASSEMBLY__
2965 unsigned long sun4v_m7_get_perfreg(unsigned long reg_num,
2966                                       unsigned long *reg_val);
2967 unsigned long sun4v_m7_set_perfreg(unsigned long reg_num,
2968                                       unsigned long reg_val);
2969 #endif
2970 
2971 /* Function numbers for HV_CORE_TRAP.  */
2972 #define HV_CORE_SET_VER                 0x00
2973 #define HV_CORE_PUTCHAR                 0x01
2974 #define HV_CORE_EXIT                    0x02
2975 #define HV_CORE_GET_VER                 0x03
2976 
2977 /* Hypervisor API groups for use with HV_CORE_SET_VER and
2978  * HV_CORE_GET_VER.
2979  */
2980 #define HV_GRP_SUN4V                    0x0000
2981 #define HV_GRP_CORE                     0x0001
2982 #define HV_GRP_INTR                     0x0002
2983 #define HV_GRP_SOFT_STATE               0x0003
2984 #define HV_GRP_TM                       0x0080
2985 #define HV_GRP_PCI                      0x0100
2986 #define HV_GRP_LDOM                     0x0101
2987 #define HV_GRP_SVC_CHAN                 0x0102
2988 #define HV_GRP_NCS                      0x0103
2989 #define HV_GRP_RNG                      0x0104
2990 #define HV_GRP_PBOOT                    0x0105
2991 #define HV_GRP_TPM                      0x0107
2992 #define HV_GRP_SDIO                     0x0108
2993 #define HV_GRP_SDIO_ERR                 0x0109
2994 #define HV_GRP_REBOOT_DATA              0x0110
2995 #define HV_GRP_M7_PERF                  0x0114
2996 #define HV_GRP_NIAG_PERF                0x0200
2997 #define HV_GRP_FIRE_PERF                0x0201
2998 #define HV_GRP_N2_CPU                   0x0202
2999 #define HV_GRP_NIU                      0x0204
3000 #define HV_GRP_VF_CPU                   0x0205
3001 #define HV_GRP_KT_CPU                   0x0209
3002 #define HV_GRP_VT_CPU                   0x020c
3003 #define HV_GRP_T5_CPU                   0x0211
3004 #define HV_GRP_DIAG                     0x0300
3005 
3006 #ifndef __ASSEMBLY__
3007 unsigned long sun4v_get_version(unsigned long group,
3008                                 unsigned long *major,
3009                                 unsigned long *minor);
3010 unsigned long sun4v_set_version(unsigned long group,
3011                                 unsigned long major,
3012                                 unsigned long minor,
3013                                 unsigned long *actual_minor);
3014 
3015 int sun4v_hvapi_register(unsigned long group, unsigned long major,
3016                          unsigned long *minor);
3017 void sun4v_hvapi_unregister(unsigned long group);
3018 int sun4v_hvapi_get(unsigned long group,
3019                     unsigned long *major,
3020                     unsigned long *minor);
3021 void sun4v_hvapi_init(void);
3022 #endif
3023 
3024 #endif /* !(_SPARC64_HYPERVISOR_H) */
3025 

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