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Linux/arch/tile/kernel/pci.c

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  1 /*
  2  * Copyright 2011 Tilera Corporation. All Rights Reserved.
  3  *
  4  *   This program is free software; you can redistribute it and/or
  5  *   modify it under the terms of the GNU General Public License
  6  *   as published by the Free Software Foundation, version 2.
  7  *
  8  *   This program is distributed in the hope that it will be useful, but
  9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
 10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 11  *   NON INFRINGEMENT.  See the GNU General Public License for
 12  *   more details.
 13  */
 14 
 15 #include <linux/kernel.h>
 16 #include <linux/pci.h>
 17 #include <linux/delay.h>
 18 #include <linux/string.h>
 19 #include <linux/init.h>
 20 #include <linux/capability.h>
 21 #include <linux/sched.h>
 22 #include <linux/errno.h>
 23 #include <linux/irq.h>
 24 #include <linux/io.h>
 25 #include <linux/uaccess.h>
 26 #include <linux/export.h>
 27 
 28 #include <asm/processor.h>
 29 #include <asm/sections.h>
 30 #include <asm/byteorder.h>
 31 #include <asm/hv_driver.h>
 32 #include <hv/drv_pcie_rc_intf.h>
 33 
 34 
 35 /*
 36  * Initialization flow and process
 37  * -------------------------------
 38  *
 39  * This files contains the routines to search for PCI buses,
 40  * enumerate the buses, and configure any attached devices.
 41  *
 42  * There are two entry points here:
 43  * 1) tile_pci_init
 44  *    This sets up the pci_controller structs, and opens the
 45  *    FDs to the hypervisor.  This is called from setup_arch() early
 46  *    in the boot process.
 47  * 2) pcibios_init
 48  *    This probes the PCI bus(es) for any attached hardware.  It's
 49  *    called by subsys_initcall.  All of the real work is done by the
 50  *    generic Linux PCI layer.
 51  *
 52  */
 53 
 54 static int pci_probe = 1;
 55 
 56 /*
 57  * This flag tells if the platform is TILEmpower that needs
 58  * special configuration for the PLX switch chip.
 59  */
 60 int __ro_after_init tile_plx_gen1;
 61 
 62 static struct pci_controller controllers[TILE_NUM_PCIE];
 63 static int num_controllers;
 64 static int pci_scan_flags[TILE_NUM_PCIE];
 65 
 66 static struct pci_ops tile_cfg_ops;
 67 
 68 
 69 /*
 70  * Open a FD to the hypervisor PCI device.
 71  *
 72  * controller_id is the controller number, config type is 0 or 1 for
 73  * config0 or config1 operations.
 74  */
 75 static int tile_pcie_open(int controller_id, int config_type)
 76 {
 77         char filename[32];
 78         int fd;
 79 
 80         sprintf(filename, "pcie/%d/config%d", controller_id, config_type);
 81 
 82         fd = hv_dev_open((HV_VirtAddr)filename, 0);
 83 
 84         return fd;
 85 }
 86 
 87 
 88 /*
 89  * Get the IRQ numbers from the HV and set up the handlers for them.
 90  */
 91 static int tile_init_irqs(int controller_id, struct pci_controller *controller)
 92 {
 93         char filename[32];
 94         int fd;
 95         int ret;
 96         int x;
 97         struct pcie_rc_config rc_config;
 98 
 99         sprintf(filename, "pcie/%d/ctl", controller_id);
100         fd = hv_dev_open((HV_VirtAddr)filename, 0);
101         if (fd < 0) {
102                 pr_err("PCI: hv_dev_open(%s) failed\n", filename);
103                 return -1;
104         }
105         ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config),
106                            sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF);
107         hv_dev_close(fd);
108         if (ret != sizeof(rc_config)) {
109                 pr_err("PCI: wanted %zd bytes, got %d\n",
110                        sizeof(rc_config), ret);
111                 return -1;
112         }
113         /* Record irq_base so that we can map INTx to IRQ # later. */
114         controller->irq_base = rc_config.intr;
115 
116         for (x = 0; x < 4; x++)
117                 tile_irq_activate(rc_config.intr + x,
118                                   TILE_IRQ_HW_CLEAR);
119 
120         if (rc_config.plx_gen1)
121                 controller->plx_gen1 = 1;
122 
123         return 0;
124 }
125 
126 /*
127  * First initialization entry point, called from setup_arch().
128  *
129  * Find valid controllers and fill in pci_controller structs for each
130  * of them.
131  *
132  * Returns the number of controllers discovered.
133  */
134 int __init tile_pci_init(void)
135 {
136         int i;
137 
138         if (!pci_probe) {
139                 pr_info("PCI: disabled by boot argument\n");
140                 return 0;
141         }
142 
143         pr_info("PCI: Searching for controllers...\n");
144 
145         /* Re-init number of PCIe controllers to support hot-plug feature. */
146         num_controllers = 0;
147 
148         /* Do any configuration we need before using the PCIe */
149 
150         for (i = 0; i < TILE_NUM_PCIE; i++) {
151                 /*
152                  * To see whether we need a real config op based on
153                  * the results of pcibios_init(), to support PCIe hot-plug.
154                  */
155                 if (pci_scan_flags[i] == 0) {
156                         int hv_cfg_fd0 = -1;
157                         int hv_cfg_fd1 = -1;
158                         int hv_mem_fd = -1;
159                         char name[32];
160                         struct pci_controller *controller;
161 
162                         /*
163                          * Open the fd to the HV.  If it fails then this
164                          * device doesn't exist.
165                          */
166                         hv_cfg_fd0 = tile_pcie_open(i, 0);
167                         if (hv_cfg_fd0 < 0)
168                                 continue;
169                         hv_cfg_fd1 = tile_pcie_open(i, 1);
170                         if (hv_cfg_fd1 < 0) {
171                                 pr_err("PCI: Couldn't open config fd to HV for controller %d\n",
172                                        i);
173                                 goto err_cont;
174                         }
175 
176                         sprintf(name, "pcie/%d/mem", i);
177                         hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
178                         if (hv_mem_fd < 0) {
179                                 pr_err("PCI: Could not open mem fd to HV!\n");
180                                 goto err_cont;
181                         }
182 
183                         pr_info("PCI: Found PCI controller #%d\n", i);
184 
185                         controller = &controllers[i];
186 
187                         controller->index = i;
188                         controller->hv_cfg_fd[0] = hv_cfg_fd0;
189                         controller->hv_cfg_fd[1] = hv_cfg_fd1;
190                         controller->hv_mem_fd = hv_mem_fd;
191                         controller->last_busno = 0xff;
192                         controller->ops = &tile_cfg_ops;
193 
194                         num_controllers++;
195                         continue;
196 
197 err_cont:
198                         if (hv_cfg_fd0 >= 0)
199                                 hv_dev_close(hv_cfg_fd0);
200                         if (hv_cfg_fd1 >= 0)
201                                 hv_dev_close(hv_cfg_fd1);
202                         if (hv_mem_fd >= 0)
203                                 hv_dev_close(hv_mem_fd);
204                         continue;
205                 }
206         }
207 
208         /*
209          * Before using the PCIe, see if we need to do any platform-specific
210          * configuration, such as the PLX switch Gen 1 issue on TILEmpower.
211          */
212         for (i = 0; i < num_controllers; i++) {
213                 struct pci_controller *controller = &controllers[i];
214 
215                 if (controller->plx_gen1)
216                         tile_plx_gen1 = 1;
217         }
218 
219         return num_controllers;
220 }
221 
222 /*
223  * (pin - 1) converts from the PCI standard's [1:4] convention to
224  * a normal [0:3] range.
225  */
226 static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
227 {
228         struct pci_controller *controller =
229                 (struct pci_controller *)dev->sysdata;
230         return (pin - 1) + controller->irq_base;
231 }
232 
233 
234 static void fixup_read_and_payload_sizes(void)
235 {
236         struct pci_dev *dev = NULL;
237         int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
238         int max_read_size = PCI_EXP_DEVCTL_READRQ_512B;
239         u16 new_values;
240 
241         /* Scan for the smallest maximum payload size. */
242         for_each_pci_dev(dev) {
243                 if (!pci_is_pcie(dev))
244                         continue;
245 
246                 if (dev->pcie_mpss < smallest_max_payload)
247                         smallest_max_payload = dev->pcie_mpss;
248         }
249 
250         /* Now, set the max_payload_size for all devices to that value. */
251         new_values = max_read_size | (smallest_max_payload << 5);
252         for_each_pci_dev(dev)
253                 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
254                                 PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,
255                                 new_values);
256 }
257 
258 
259 /*
260  * Second PCI initialization entry point, called by subsys_initcall.
261  *
262  * The controllers have been set up by the time we get here, by a call to
263  * tile_pci_init.
264  */
265 int __init pcibios_init(void)
266 {
267         struct pci_host_bridge *bridge;
268         int i;
269 
270         pr_info("PCI: Probing PCI hardware\n");
271 
272         /*
273          * Delay a bit in case devices aren't ready.  Some devices are
274          * known to require at least 20ms here, but we use a more
275          * conservative value.
276          */
277         msleep(250);
278 
279         /* Scan all of the recorded PCI controllers.  */
280         for (i = 0; i < TILE_NUM_PCIE; i++) {
281                 /*
282                  * Do real pcibios init ops if the controller is initialized
283                  * by tile_pci_init() successfully and not initialized by
284                  * pcibios_init() yet to support PCIe hot-plug.
285                  */
286                 if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
287                         struct pci_controller *controller = &controllers[i];
288                         struct pci_bus *bus;
289                         LIST_HEAD(resources);
290 
291                         if (tile_init_irqs(i, controller)) {
292                                 pr_err("PCI: Could not initialize IRQs\n");
293                                 continue;
294                         }
295 
296                         pr_info("PCI: initializing controller #%d\n", i);
297 
298                         pci_add_resource(&resources, &ioport_resource);
299                         pci_add_resource(&resources, &iomem_resource);
300 
301                         bridge = pci_alloc_host_bridge(0);
302                         if (!bridge)
303                                 break;
304 
305                         list_splice_init(&resources, &bridge->windows);
306                         bridge->dev.parent = NULL;
307                         bridge->sysdata = controller;
308                         bridge->busnr = 0;
309                         bridge->ops = controller->ops;
310                         bridge->swizzle_irq = pci_common_swizzle;
311                         bridge->map_irq = tile_map_irq;
312 
313                         pci_scan_root_bus_bridge(bridge);
314                         bus = bridge->bus;
315                         controller->root_bus = bus;
316                         controller->last_busno = bus->busn_res.end;
317                 }
318         }
319 
320         /*
321          * This comes from the generic Linux PCI driver.
322          *
323          * It allocates all of the resources (I/O memory, etc)
324          * associated with the devices read in above.
325          */
326         pci_assign_unassigned_resources();
327 
328         /* Configure the max_read_size and max_payload_size values. */
329         fixup_read_and_payload_sizes();
330 
331         /* Record the I/O resources in the PCI controller structure. */
332         for (i = 0; i < TILE_NUM_PCIE; i++) {
333                 /*
334                  * Do real pcibios init ops if the controller is initialized
335                  * by tile_pci_init() successfully and not initialized by
336                  * pcibios_init() yet to support PCIe hot-plug.
337                  */
338                 if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
339                         struct pci_bus *root_bus = controllers[i].root_bus;
340                         struct pci_bus *next_bus;
341                         struct pci_dev *dev;
342 
343                         pci_bus_add_devices(root_bus);
344 
345                         list_for_each_entry(dev, &root_bus->devices, bus_list) {
346                                 /*
347                                  * Find the PCI host controller, ie. the 1st
348                                  * bridge.
349                                  */
350                                 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
351                                         (PCI_SLOT(dev->devfn) == 0)) {
352                                         next_bus = dev->subordinate;
353                                         controllers[i].mem_resources[0] =
354                                                 *next_bus->resource[0];
355                                         controllers[i].mem_resources[1] =
356                                                  *next_bus->resource[1];
357                                         controllers[i].mem_resources[2] =
358                                                  *next_bus->resource[2];
359 
360                                         /* Setup flags. */
361                                         pci_scan_flags[i] = 1;
362 
363                                         break;
364                                 }
365                         }
366                 }
367         }
368 
369         return 0;
370 }
371 subsys_initcall(pcibios_init);
372 
373 void pcibios_set_master(struct pci_dev *dev)
374 {
375         /* No special bus mastering setup handling. */
376 }
377 
378 /* Process any "pci=" kernel boot arguments. */
379 char *__init pcibios_setup(char *str)
380 {
381         if (!strcmp(str, "off")) {
382                 pci_probe = 0;
383                 return NULL;
384         }
385         return str;
386 }
387 
388 /*
389  * Enable memory and/or address decoding, as appropriate, for the
390  * device described by the 'dev' struct.
391  *
392  * This is called from the generic PCI layer, and can be called
393  * for bridges or endpoints.
394  */
395 int pcibios_enable_device(struct pci_dev *dev, int mask)
396 {
397         u16 cmd, old_cmd;
398         u8 header_type;
399         int i;
400         struct resource *r;
401 
402         pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
403 
404         pci_read_config_word(dev, PCI_COMMAND, &cmd);
405         old_cmd = cmd;
406         if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
407                 /*
408                  * For bridges, we enable both memory and I/O decoding
409                  * in call cases.
410                  */
411                 cmd |= PCI_COMMAND_IO;
412                 cmd |= PCI_COMMAND_MEMORY;
413         } else {
414                 /*
415                  * For endpoints, we enable memory and/or I/O decoding
416                  * only if they have a memory resource of that type.
417                  */
418                 for (i = 0; i < 6; i++) {
419                         r = &dev->resource[i];
420                         if (r->flags & IORESOURCE_UNSET) {
421                                 pr_err("PCI: Device %s not available because of resource collisions\n",
422                                        pci_name(dev));
423                                 return -EINVAL;
424                         }
425                         if (r->flags & IORESOURCE_IO)
426                                 cmd |= PCI_COMMAND_IO;
427                         if (r->flags & IORESOURCE_MEM)
428                                 cmd |= PCI_COMMAND_MEMORY;
429                 }
430         }
431 
432         /*
433          * We only write the command if it changed.
434          */
435         if (cmd != old_cmd)
436                 pci_write_config_word(dev, PCI_COMMAND, cmd);
437         return 0;
438 }
439 
440 /****************************************************************
441  *
442  * Tile PCI config space read/write routines
443  *
444  ****************************************************************/
445 
446 /*
447  * These are the normal read and write ops
448  * These are expanded with macros from  pci_bus_read_config_byte() etc.
449  *
450  * devfn is the combined PCI slot & function.
451  *
452  * offset is in bytes, from the start of config space for the
453  * specified bus & slot.
454  */
455 
456 static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
457                          int size, u32 *val)
458 {
459         struct pci_controller *controller = bus->sysdata;
460         int busnum = bus->number & 0xff;
461         int slot = (devfn >> 3) & 0x1f;
462         int function = devfn & 0x7;
463         u32 addr;
464         int config_mode = 1;
465 
466         /*
467          * There is no bridge between the Tile and bus 0, so we
468          * use config0 to talk to bus 0.
469          *
470          * If we're talking to a bus other than zero then we
471          * must have found a bridge.
472          */
473         if (busnum == 0) {
474                 /*
475                  * We fake an empty slot for (busnum == 0) && (slot > 0),
476                  * since there is only one slot on bus 0.
477                  */
478                 if (slot) {
479                         *val = 0xFFFFFFFF;
480                         return 0;
481                 }
482                 config_mode = 0;
483         }
484 
485         addr = busnum << 20;            /* Bus in 27:20 */
486         addr |= slot << 15;             /* Slot (device) in 19:15 */
487         addr |= function << 12;         /* Function is in 14:12 */
488         addr |= (offset & 0xFFF);       /* byte address in 0:11 */
489 
490         return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,
491                             (HV_VirtAddr)(val), size, addr);
492 }
493 
494 
495 /*
496  * See tile_cfg_read() for relevant comments.
497  * Note that "val" is the value to write, not a pointer to that value.
498  */
499 static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
500                           int size, u32 val)
501 {
502         struct pci_controller *controller = bus->sysdata;
503         int busnum = bus->number & 0xff;
504         int slot = (devfn >> 3) & 0x1f;
505         int function = devfn & 0x7;
506         u32 addr;
507         int config_mode = 1;
508         HV_VirtAddr valp = (HV_VirtAddr)&val;
509 
510         /*
511          * For bus 0 slot 0 we use config 0 accesses.
512          */
513         if (busnum == 0) {
514                 /*
515                  * We fake an empty slot for (busnum == 0) && (slot > 0),
516                  * since there is only one slot on bus 0.
517                  */
518                 if (slot)
519                         return 0;
520                 config_mode = 0;
521         }
522 
523         addr = busnum << 20;            /* Bus in 27:20 */
524         addr |= slot << 15;             /* Slot (device) in 19:15 */
525         addr |= function << 12;         /* Function is in 14:12 */
526         addr |= (offset & 0xFFF);       /* byte address in 0:11 */
527 
528 #ifdef __BIG_ENDIAN
529         /* Point to the correct part of the 32-bit "val". */
530         valp += 4 - size;
531 #endif
532 
533         return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,
534                              valp, size, addr);
535 }
536 
537 
538 static struct pci_ops tile_cfg_ops = {
539         .read =         tile_cfg_read,
540         .write =        tile_cfg_write,
541 };
542 
543 
544 /*
545  * In the following, each PCI controller's mem_resources[1]
546  * represents its (non-prefetchable) PCI memory resource.
547  * mem_resources[0] and mem_resources[2] refer to its PCI I/O and
548  * prefetchable PCI memory resources, respectively.
549  * For more details, see pci_setup_bridge() in setup-bus.c.
550  * By comparing the target PCI memory address against the
551  * end address of controller 0, we can determine the controller
552  * that should accept the PCI memory access.
553  */
554 #define TILE_READ(size, type)                                           \
555 type _tile_read##size(unsigned long addr)                               \
556 {                                                                       \
557         type val;                                                       \
558         int idx = 0;                                                    \
559         if (addr > controllers[0].mem_resources[1].end &&               \
560             addr > controllers[0].mem_resources[2].end)                 \
561                 idx = 1;                                                \
562         if (hv_dev_pread(controllers[idx].hv_mem_fd, 0,                 \
563                          (HV_VirtAddr)(&val), sizeof(type), addr))      \
564                 pr_err("PCI: read %zd bytes at 0x%lX failed\n",         \
565                        sizeof(type), addr);                             \
566         return val;                                                     \
567 }                                                                       \
568 EXPORT_SYMBOL(_tile_read##size)
569 
570 TILE_READ(b, u8);
571 TILE_READ(w, u16);
572 TILE_READ(l, u32);
573 TILE_READ(q, u64);
574 
575 #define TILE_WRITE(size, type)                                          \
576 void _tile_write##size(type val, unsigned long addr)                    \
577 {                                                                       \
578         int idx = 0;                                                    \
579         if (addr > controllers[0].mem_resources[1].end &&               \
580             addr > controllers[0].mem_resources[2].end)                 \
581                 idx = 1;                                                \
582         if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0,                \
583                           (HV_VirtAddr)(&val), sizeof(type), addr))     \
584                 pr_err("PCI: write %zd bytes at 0x%lX failed\n",        \
585                        sizeof(type), addr);                             \
586 }                                                                       \
587 EXPORT_SYMBOL(_tile_write##size)
588 
589 TILE_WRITE(b, u8);
590 TILE_WRITE(w, u16);
591 TILE_WRITE(l, u32);
592 TILE_WRITE(q, u64);
593 

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