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Linux/arch/x86/kernel/apic/io_apic.c

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  1 /*
  2  *      Intel IO-APIC support for multi-Pentium hosts.
  3  *
  4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
  5  *
  6  *      Many thanks to Stig Venaas for trying out countless experimental
  7  *      patches and reporting/debugging problems patiently!
  8  *
  9  *      (c) 1999, Multiple IO-APIC support, developed by
 10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
 11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
 12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
 13  *      and Ingo Molnar <mingo@redhat.com>
 14  *
 15  *      Fixes
 16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
 17  *                                      thanks to Eric Gilmore
 18  *                                      and Rolf G. Tews
 19  *                                      for testing these extensively
 20  *      Paul Diefenbaugh        :       Added full ACPI support
 21  */
 22 
 23 #include <linux/mm.h>
 24 #include <linux/interrupt.h>
 25 #include <linux/init.h>
 26 #include <linux/delay.h>
 27 #include <linux/sched.h>
 28 #include <linux/pci.h>
 29 #include <linux/mc146818rtc.h>
 30 #include <linux/compiler.h>
 31 #include <linux/acpi.h>
 32 #include <linux/module.h>
 33 #include <linux/syscore_ops.h>
 34 #include <linux/msi.h>
 35 #include <linux/htirq.h>
 36 #include <linux/freezer.h>
 37 #include <linux/kthread.h>
 38 #include <linux/jiffies.h>      /* time_after() */
 39 #include <linux/slab.h>
 40 #include <linux/bootmem.h>
 41 #include <linux/dmar.h>
 42 #include <linux/hpet.h>
 43 
 44 #include <asm/idle.h>
 45 #include <asm/io.h>
 46 #include <asm/smp.h>
 47 #include <asm/cpu.h>
 48 #include <asm/desc.h>
 49 #include <asm/proto.h>
 50 #include <asm/acpi.h>
 51 #include <asm/dma.h>
 52 #include <asm/timer.h>
 53 #include <asm/i8259.h>
 54 #include <asm/msidef.h>
 55 #include <asm/hypertransport.h>
 56 #include <asm/setup.h>
 57 #include <asm/irq_remapping.h>
 58 #include <asm/hpet.h>
 59 #include <asm/hw_irq.h>
 60 
 61 #include <asm/apic.h>
 62 
 63 #define __apicdebuginit(type) static type __init
 64 
 65 #define for_each_irq_pin(entry, head) \
 66         for (entry = head; entry; entry = entry->next)
 67 
 68 /*
 69  *      Is the SiS APIC rmw bug present ?
 70  *      -1 = don't know, 0 = no, 1 = yes
 71  */
 72 int sis_apic_bug = -1;
 73 
 74 static DEFINE_RAW_SPINLOCK(ioapic_lock);
 75 static DEFINE_RAW_SPINLOCK(vector_lock);
 76 
 77 static struct ioapic {
 78         /*
 79          * # of IRQ routing registers
 80          */
 81         int nr_registers;
 82         /*
 83          * Saved state during suspend/resume, or while enabling intr-remap.
 84          */
 85         struct IO_APIC_route_entry *saved_registers;
 86         /* I/O APIC config */
 87         struct mpc_ioapic mp_config;
 88         /* IO APIC gsi routing info */
 89         struct mp_ioapic_gsi  gsi_config;
 90         DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
 91 } ioapics[MAX_IO_APICS];
 92 
 93 #define mpc_ioapic_ver(ioapic_idx)      ioapics[ioapic_idx].mp_config.apicver
 94 
 95 int mpc_ioapic_id(int ioapic_idx)
 96 {
 97         return ioapics[ioapic_idx].mp_config.apicid;
 98 }
 99 
100 unsigned int mpc_ioapic_addr(int ioapic_idx)
101 {
102         return ioapics[ioapic_idx].mp_config.apicaddr;
103 }
104 
105 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
106 {
107         return &ioapics[ioapic_idx].gsi_config;
108 }
109 
110 int nr_ioapics;
111 
112 /* The one past the highest gsi number used */
113 u32 gsi_top;
114 
115 /* MP IRQ source entries */
116 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
117 
118 /* # of MP IRQ source entries */
119 int mp_irq_entries;
120 
121 /* GSI interrupts */
122 static int nr_irqs_gsi = NR_IRQS_LEGACY;
123 
124 #ifdef CONFIG_EISA
125 int mp_bus_id_to_type[MAX_MP_BUSSES];
126 #endif
127 
128 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
129 
130 int skip_ioapic_setup;
131 
132 /**
133  * disable_ioapic_support() - disables ioapic support at runtime
134  */
135 void disable_ioapic_support(void)
136 {
137 #ifdef CONFIG_PCI
138         noioapicquirk = 1;
139         noioapicreroute = -1;
140 #endif
141         skip_ioapic_setup = 1;
142 }
143 
144 static int __init parse_noapic(char *str)
145 {
146         /* disable IO-APIC */
147         disable_ioapic_support();
148         return 0;
149 }
150 early_param("noapic", parse_noapic);
151 
152 static int io_apic_setup_irq_pin(unsigned int irq, int node,
153                                  struct io_apic_irq_attr *attr);
154 
155 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
156 void mp_save_irq(struct mpc_intsrc *m)
157 {
158         int i;
159 
160         apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
161                 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
162                 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
163                 m->srcbusirq, m->dstapic, m->dstirq);
164 
165         for (i = 0; i < mp_irq_entries; i++) {
166                 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
167                         return;
168         }
169 
170         memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
171         if (++mp_irq_entries == MAX_IRQ_SOURCES)
172                 panic("Max # of irq sources exceeded!!\n");
173 }
174 
175 struct irq_pin_list {
176         int apic, pin;
177         struct irq_pin_list *next;
178 };
179 
180 static struct irq_pin_list *alloc_irq_pin_list(int node)
181 {
182         return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
183 }
184 
185 
186 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
187 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
188 
189 int __init arch_early_irq_init(void)
190 {
191         struct irq_cfg *cfg;
192         int count, node, i;
193 
194         if (!legacy_pic->nr_legacy_irqs)
195                 io_apic_irqs = ~0UL;
196 
197         for (i = 0; i < nr_ioapics; i++) {
198                 ioapics[i].saved_registers =
199                         kzalloc(sizeof(struct IO_APIC_route_entry) *
200                                 ioapics[i].nr_registers, GFP_KERNEL);
201                 if (!ioapics[i].saved_registers)
202                         pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
203         }
204 
205         cfg = irq_cfgx;
206         count = ARRAY_SIZE(irq_cfgx);
207         node = cpu_to_node(0);
208 
209         /* Make sure the legacy interrupts are marked in the bitmap */
210         irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
211 
212         for (i = 0; i < count; i++) {
213                 irq_set_chip_data(i, &cfg[i]);
214                 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
215                 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
216                 /*
217                  * For legacy IRQ's, start with assigning irq0 to irq15 to
218                  * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
219                  */
220                 if (i < legacy_pic->nr_legacy_irqs) {
221                         cfg[i].vector = IRQ0_VECTOR + i;
222                         cpumask_setall(cfg[i].domain);
223                 }
224         }
225 
226         return 0;
227 }
228 
229 static struct irq_cfg *irq_cfg(unsigned int irq)
230 {
231         return irq_get_chip_data(irq);
232 }
233 
234 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
235 {
236         struct irq_cfg *cfg;
237 
238         cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
239         if (!cfg)
240                 return NULL;
241         if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
242                 goto out_cfg;
243         if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
244                 goto out_domain;
245         return cfg;
246 out_domain:
247         free_cpumask_var(cfg->domain);
248 out_cfg:
249         kfree(cfg);
250         return NULL;
251 }
252 
253 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
254 {
255         if (!cfg)
256                 return;
257         irq_set_chip_data(at, NULL);
258         free_cpumask_var(cfg->domain);
259         free_cpumask_var(cfg->old_domain);
260         kfree(cfg);
261 }
262 
263 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
264 {
265         int res = irq_alloc_desc_at(at, node);
266         struct irq_cfg *cfg;
267 
268         if (res < 0) {
269                 if (res != -EEXIST)
270                         return NULL;
271                 cfg = irq_get_chip_data(at);
272                 if (cfg)
273                         return cfg;
274         }
275 
276         cfg = alloc_irq_cfg(at, node);
277         if (cfg)
278                 irq_set_chip_data(at, cfg);
279         else
280                 irq_free_desc(at);
281         return cfg;
282 }
283 
284 static int alloc_irqs_from(unsigned int from, unsigned int count, int node)
285 {
286         return irq_alloc_descs_from(from, count, node);
287 }
288 
289 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
290 {
291         free_irq_cfg(at, cfg);
292         irq_free_desc(at);
293 }
294 
295 
296 struct io_apic {
297         unsigned int index;
298         unsigned int unused[3];
299         unsigned int data;
300         unsigned int unused2[11];
301         unsigned int eoi;
302 };
303 
304 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
305 {
306         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
307                 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
308 }
309 
310 void io_apic_eoi(unsigned int apic, unsigned int vector)
311 {
312         struct io_apic __iomem *io_apic = io_apic_base(apic);
313         writel(vector, &io_apic->eoi);
314 }
315 
316 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
317 {
318         struct io_apic __iomem *io_apic = io_apic_base(apic);
319         writel(reg, &io_apic->index);
320         return readl(&io_apic->data);
321 }
322 
323 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
324 {
325         struct io_apic __iomem *io_apic = io_apic_base(apic);
326 
327         writel(reg, &io_apic->index);
328         writel(value, &io_apic->data);
329 }
330 
331 /*
332  * Re-write a value: to be used for read-modify-write
333  * cycles where the read already set up the index register.
334  *
335  * Older SiS APIC requires we rewrite the index register
336  */
337 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
338 {
339         struct io_apic __iomem *io_apic = io_apic_base(apic);
340 
341         if (sis_apic_bug)
342                 writel(reg, &io_apic->index);
343         writel(value, &io_apic->data);
344 }
345 
346 union entry_union {
347         struct { u32 w1, w2; };
348         struct IO_APIC_route_entry entry;
349 };
350 
351 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
352 {
353         union entry_union eu;
354 
355         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
356         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
357 
358         return eu.entry;
359 }
360 
361 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
362 {
363         union entry_union eu;
364         unsigned long flags;
365 
366         raw_spin_lock_irqsave(&ioapic_lock, flags);
367         eu.entry = __ioapic_read_entry(apic, pin);
368         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
369 
370         return eu.entry;
371 }
372 
373 /*
374  * When we write a new IO APIC routing entry, we need to write the high
375  * word first! If the mask bit in the low word is clear, we will enable
376  * the interrupt, and we need to make sure the entry is fully populated
377  * before that happens.
378  */
379 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
380 {
381         union entry_union eu = {{0, 0}};
382 
383         eu.entry = e;
384         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
385         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
386 }
387 
388 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
389 {
390         unsigned long flags;
391 
392         raw_spin_lock_irqsave(&ioapic_lock, flags);
393         __ioapic_write_entry(apic, pin, e);
394         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
395 }
396 
397 /*
398  * When we mask an IO APIC routing entry, we need to write the low
399  * word first, in order to set the mask bit before we change the
400  * high bits!
401  */
402 static void ioapic_mask_entry(int apic, int pin)
403 {
404         unsigned long flags;
405         union entry_union eu = { .entry.mask = 1 };
406 
407         raw_spin_lock_irqsave(&ioapic_lock, flags);
408         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
409         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
410         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
411 }
412 
413 /*
414  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
415  * shared ISA-space IRQs, so we have to support them. We are super
416  * fast in the common case, and fast for shared ISA-space IRQs.
417  */
418 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
419 {
420         struct irq_pin_list **last, *entry;
421 
422         /* don't allow duplicates */
423         last = &cfg->irq_2_pin;
424         for_each_irq_pin(entry, cfg->irq_2_pin) {
425                 if (entry->apic == apic && entry->pin == pin)
426                         return 0;
427                 last = &entry->next;
428         }
429 
430         entry = alloc_irq_pin_list(node);
431         if (!entry) {
432                 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
433                        node, apic, pin);
434                 return -ENOMEM;
435         }
436         entry->apic = apic;
437         entry->pin = pin;
438 
439         *last = entry;
440         return 0;
441 }
442 
443 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
444 {
445         if (__add_pin_to_irq_node(cfg, node, apic, pin))
446                 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
447 }
448 
449 /*
450  * Reroute an IRQ to a different pin.
451  */
452 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
453                                            int oldapic, int oldpin,
454                                            int newapic, int newpin)
455 {
456         struct irq_pin_list *entry;
457 
458         for_each_irq_pin(entry, cfg->irq_2_pin) {
459                 if (entry->apic == oldapic && entry->pin == oldpin) {
460                         entry->apic = newapic;
461                         entry->pin = newpin;
462                         /* every one is different, right? */
463                         return;
464                 }
465         }
466 
467         /* old apic/pin didn't exist, so just add new ones */
468         add_pin_to_irq_node(cfg, node, newapic, newpin);
469 }
470 
471 static void __io_apic_modify_irq(struct irq_pin_list *entry,
472                                  int mask_and, int mask_or,
473                                  void (*final)(struct irq_pin_list *entry))
474 {
475         unsigned int reg, pin;
476 
477         pin = entry->pin;
478         reg = io_apic_read(entry->apic, 0x10 + pin * 2);
479         reg &= mask_and;
480         reg |= mask_or;
481         io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
482         if (final)
483                 final(entry);
484 }
485 
486 static void io_apic_modify_irq(struct irq_cfg *cfg,
487                                int mask_and, int mask_or,
488                                void (*final)(struct irq_pin_list *entry))
489 {
490         struct irq_pin_list *entry;
491 
492         for_each_irq_pin(entry, cfg->irq_2_pin)
493                 __io_apic_modify_irq(entry, mask_and, mask_or, final);
494 }
495 
496 static void io_apic_sync(struct irq_pin_list *entry)
497 {
498         /*
499          * Synchronize the IO-APIC and the CPU by doing
500          * a dummy read from the IO-APIC
501          */
502         struct io_apic __iomem *io_apic;
503 
504         io_apic = io_apic_base(entry->apic);
505         readl(&io_apic->data);
506 }
507 
508 static void mask_ioapic(struct irq_cfg *cfg)
509 {
510         unsigned long flags;
511 
512         raw_spin_lock_irqsave(&ioapic_lock, flags);
513         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
514         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
515 }
516 
517 static void mask_ioapic_irq(struct irq_data *data)
518 {
519         mask_ioapic(data->chip_data);
520 }
521 
522 static void __unmask_ioapic(struct irq_cfg *cfg)
523 {
524         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
525 }
526 
527 static void unmask_ioapic(struct irq_cfg *cfg)
528 {
529         unsigned long flags;
530 
531         raw_spin_lock_irqsave(&ioapic_lock, flags);
532         __unmask_ioapic(cfg);
533         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
534 }
535 
536 static void unmask_ioapic_irq(struct irq_data *data)
537 {
538         unmask_ioapic(data->chip_data);
539 }
540 
541 /*
542  * IO-APIC versions below 0x20 don't support EOI register.
543  * For the record, here is the information about various versions:
544  *     0Xh     82489DX
545  *     1Xh     I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
546  *     2Xh     I/O(x)APIC which is PCI 2.2 Compliant
547  *     30h-FFh Reserved
548  *
549  * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
550  * version as 0x2. This is an error with documentation and these ICH chips
551  * use io-apic's of version 0x20.
552  *
553  * For IO-APIC's with EOI register, we use that to do an explicit EOI.
554  * Otherwise, we simulate the EOI message manually by changing the trigger
555  * mode to edge and then back to level, with RTE being masked during this.
556  */
557 void native_eoi_ioapic_pin(int apic, int pin, int vector)
558 {
559         if (mpc_ioapic_ver(apic) >= 0x20) {
560                 io_apic_eoi(apic, vector);
561         } else {
562                 struct IO_APIC_route_entry entry, entry1;
563 
564                 entry = entry1 = __ioapic_read_entry(apic, pin);
565 
566                 /*
567                  * Mask the entry and change the trigger mode to edge.
568                  */
569                 entry1.mask = 1;
570                 entry1.trigger = IOAPIC_EDGE;
571 
572                 __ioapic_write_entry(apic, pin, entry1);
573 
574                 /*
575                  * Restore the previous level triggered entry.
576                  */
577                 __ioapic_write_entry(apic, pin, entry);
578         }
579 }
580 
581 void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
582 {
583         struct irq_pin_list *entry;
584         unsigned long flags;
585 
586         raw_spin_lock_irqsave(&ioapic_lock, flags);
587         for_each_irq_pin(entry, cfg->irq_2_pin)
588                 x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin,
589                                                cfg->vector);
590         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
591 }
592 
593 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
594 {
595         struct IO_APIC_route_entry entry;
596 
597         /* Check delivery_mode to be sure we're not clearing an SMI pin */
598         entry = ioapic_read_entry(apic, pin);
599         if (entry.delivery_mode == dest_SMI)
600                 return;
601 
602         /*
603          * Make sure the entry is masked and re-read the contents to check
604          * if it is a level triggered pin and if the remote-IRR is set.
605          */
606         if (!entry.mask) {
607                 entry.mask = 1;
608                 ioapic_write_entry(apic, pin, entry);
609                 entry = ioapic_read_entry(apic, pin);
610         }
611 
612         if (entry.irr) {
613                 unsigned long flags;
614 
615                 /*
616                  * Make sure the trigger mode is set to level. Explicit EOI
617                  * doesn't clear the remote-IRR if the trigger mode is not
618                  * set to level.
619                  */
620                 if (!entry.trigger) {
621                         entry.trigger = IOAPIC_LEVEL;
622                         ioapic_write_entry(apic, pin, entry);
623                 }
624 
625                 raw_spin_lock_irqsave(&ioapic_lock, flags);
626                 x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector);
627                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
628         }
629 
630         /*
631          * Clear the rest of the bits in the IO-APIC RTE except for the mask
632          * bit.
633          */
634         ioapic_mask_entry(apic, pin);
635         entry = ioapic_read_entry(apic, pin);
636         if (entry.irr)
637                 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
638                        mpc_ioapic_id(apic), pin);
639 }
640 
641 static void clear_IO_APIC (void)
642 {
643         int apic, pin;
644 
645         for (apic = 0; apic < nr_ioapics; apic++)
646                 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
647                         clear_IO_APIC_pin(apic, pin);
648 }
649 
650 #ifdef CONFIG_X86_32
651 /*
652  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
653  * specific CPU-side IRQs.
654  */
655 
656 #define MAX_PIRQS 8
657 static int pirq_entries[MAX_PIRQS] = {
658         [0 ... MAX_PIRQS - 1] = -1
659 };
660 
661 static int __init ioapic_pirq_setup(char *str)
662 {
663         int i, max;
664         int ints[MAX_PIRQS+1];
665 
666         get_options(str, ARRAY_SIZE(ints), ints);
667 
668         apic_printk(APIC_VERBOSE, KERN_INFO
669                         "PIRQ redirection, working around broken MP-BIOS.\n");
670         max = MAX_PIRQS;
671         if (ints[0] < MAX_PIRQS)
672                 max = ints[0];
673 
674         for (i = 0; i < max; i++) {
675                 apic_printk(APIC_VERBOSE, KERN_DEBUG
676                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
677                 /*
678                  * PIRQs are mapped upside down, usually.
679                  */
680                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
681         }
682         return 1;
683 }
684 
685 __setup("pirq=", ioapic_pirq_setup);
686 #endif /* CONFIG_X86_32 */
687 
688 /*
689  * Saves all the IO-APIC RTE's
690  */
691 int save_ioapic_entries(void)
692 {
693         int apic, pin;
694         int err = 0;
695 
696         for (apic = 0; apic < nr_ioapics; apic++) {
697                 if (!ioapics[apic].saved_registers) {
698                         err = -ENOMEM;
699                         continue;
700                 }
701 
702                 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
703                         ioapics[apic].saved_registers[pin] =
704                                 ioapic_read_entry(apic, pin);
705         }
706 
707         return err;
708 }
709 
710 /*
711  * Mask all IO APIC entries.
712  */
713 void mask_ioapic_entries(void)
714 {
715         int apic, pin;
716 
717         for (apic = 0; apic < nr_ioapics; apic++) {
718                 if (!ioapics[apic].saved_registers)
719                         continue;
720 
721                 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
722                         struct IO_APIC_route_entry entry;
723 
724                         entry = ioapics[apic].saved_registers[pin];
725                         if (!entry.mask) {
726                                 entry.mask = 1;
727                                 ioapic_write_entry(apic, pin, entry);
728                         }
729                 }
730         }
731 }
732 
733 /*
734  * Restore IO APIC entries which was saved in the ioapic structure.
735  */
736 int restore_ioapic_entries(void)
737 {
738         int apic, pin;
739 
740         for (apic = 0; apic < nr_ioapics; apic++) {
741                 if (!ioapics[apic].saved_registers)
742                         continue;
743 
744                 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
745                         ioapic_write_entry(apic, pin,
746                                            ioapics[apic].saved_registers[pin]);
747         }
748         return 0;
749 }
750 
751 /*
752  * Find the IRQ entry number of a certain pin.
753  */
754 static int find_irq_entry(int ioapic_idx, int pin, int type)
755 {
756         int i;
757 
758         for (i = 0; i < mp_irq_entries; i++)
759                 if (mp_irqs[i].irqtype == type &&
760                     (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
761                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
762                     mp_irqs[i].dstirq == pin)
763                         return i;
764 
765         return -1;
766 }
767 
768 /*
769  * Find the pin to which IRQ[irq] (ISA) is connected
770  */
771 static int __init find_isa_irq_pin(int irq, int type)
772 {
773         int i;
774 
775         for (i = 0; i < mp_irq_entries; i++) {
776                 int lbus = mp_irqs[i].srcbus;
777 
778                 if (test_bit(lbus, mp_bus_not_pci) &&
779                     (mp_irqs[i].irqtype == type) &&
780                     (mp_irqs[i].srcbusirq == irq))
781 
782                         return mp_irqs[i].dstirq;
783         }
784         return -1;
785 }
786 
787 static int __init find_isa_irq_apic(int irq, int type)
788 {
789         int i;
790 
791         for (i = 0; i < mp_irq_entries; i++) {
792                 int lbus = mp_irqs[i].srcbus;
793 
794                 if (test_bit(lbus, mp_bus_not_pci) &&
795                     (mp_irqs[i].irqtype == type) &&
796                     (mp_irqs[i].srcbusirq == irq))
797                         break;
798         }
799 
800         if (i < mp_irq_entries) {
801                 int ioapic_idx;
802 
803                 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
804                         if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
805                                 return ioapic_idx;
806         }
807 
808         return -1;
809 }
810 
811 #ifdef CONFIG_EISA
812 /*
813  * EISA Edge/Level control register, ELCR
814  */
815 static int EISA_ELCR(unsigned int irq)
816 {
817         if (irq < legacy_pic->nr_legacy_irqs) {
818                 unsigned int port = 0x4d0 + (irq >> 3);
819                 return (inb(port) >> (irq & 7)) & 1;
820         }
821         apic_printk(APIC_VERBOSE, KERN_INFO
822                         "Broken MPtable reports ISA irq %d\n", irq);
823         return 0;
824 }
825 
826 #endif
827 
828 /* ISA interrupts are always polarity zero edge triggered,
829  * when listed as conforming in the MP table. */
830 
831 #define default_ISA_trigger(idx)        (0)
832 #define default_ISA_polarity(idx)       (0)
833 
834 /* EISA interrupts are always polarity zero and can be edge or level
835  * trigger depending on the ELCR value.  If an interrupt is listed as
836  * EISA conforming in the MP table, that means its trigger type must
837  * be read in from the ELCR */
838 
839 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
840 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
841 
842 /* PCI interrupts are always polarity one level triggered,
843  * when listed as conforming in the MP table. */
844 
845 #define default_PCI_trigger(idx)        (1)
846 #define default_PCI_polarity(idx)       (1)
847 
848 static int irq_polarity(int idx)
849 {
850         int bus = mp_irqs[idx].srcbus;
851         int polarity;
852 
853         /*
854          * Determine IRQ line polarity (high active or low active):
855          */
856         switch (mp_irqs[idx].irqflag & 3)
857         {
858                 case 0: /* conforms, ie. bus-type dependent polarity */
859                         if (test_bit(bus, mp_bus_not_pci))
860                                 polarity = default_ISA_polarity(idx);
861                         else
862                                 polarity = default_PCI_polarity(idx);
863                         break;
864                 case 1: /* high active */
865                 {
866                         polarity = 0;
867                         break;
868                 }
869                 case 2: /* reserved */
870                 {
871                         pr_warn("broken BIOS!!\n");
872                         polarity = 1;
873                         break;
874                 }
875                 case 3: /* low active */
876                 {
877                         polarity = 1;
878                         break;
879                 }
880                 default: /* invalid */
881                 {
882                         pr_warn("broken BIOS!!\n");
883                         polarity = 1;
884                         break;
885                 }
886         }
887         return polarity;
888 }
889 
890 static int irq_trigger(int idx)
891 {
892         int bus = mp_irqs[idx].srcbus;
893         int trigger;
894 
895         /*
896          * Determine IRQ trigger mode (edge or level sensitive):
897          */
898         switch ((mp_irqs[idx].irqflag>>2) & 3)
899         {
900                 case 0: /* conforms, ie. bus-type dependent */
901                         if (test_bit(bus, mp_bus_not_pci))
902                                 trigger = default_ISA_trigger(idx);
903                         else
904                                 trigger = default_PCI_trigger(idx);
905 #ifdef CONFIG_EISA
906                         switch (mp_bus_id_to_type[bus]) {
907                                 case MP_BUS_ISA: /* ISA pin */
908                                 {
909                                         /* set before the switch */
910                                         break;
911                                 }
912                                 case MP_BUS_EISA: /* EISA pin */
913                                 {
914                                         trigger = default_EISA_trigger(idx);
915                                         break;
916                                 }
917                                 case MP_BUS_PCI: /* PCI pin */
918                                 {
919                                         /* set before the switch */
920                                         break;
921                                 }
922                                 default:
923                                 {
924                                         pr_warn("broken BIOS!!\n");
925                                         trigger = 1;
926                                         break;
927                                 }
928                         }
929 #endif
930                         break;
931                 case 1: /* edge */
932                 {
933                         trigger = 0;
934                         break;
935                 }
936                 case 2: /* reserved */
937                 {
938                         pr_warn("broken BIOS!!\n");
939                         trigger = 1;
940                         break;
941                 }
942                 case 3: /* level */
943                 {
944                         trigger = 1;
945                         break;
946                 }
947                 default: /* invalid */
948                 {
949                         pr_warn("broken BIOS!!\n");
950                         trigger = 0;
951                         break;
952                 }
953         }
954         return trigger;
955 }
956 
957 static int pin_2_irq(int idx, int apic, int pin)
958 {
959         int irq;
960         int bus = mp_irqs[idx].srcbus;
961         struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
962 
963         /*
964          * Debugging check, we are in big trouble if this message pops up!
965          */
966         if (mp_irqs[idx].dstirq != pin)
967                 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
968 
969         if (test_bit(bus, mp_bus_not_pci)) {
970                 irq = mp_irqs[idx].srcbusirq;
971         } else {
972                 u32 gsi = gsi_cfg->gsi_base + pin;
973 
974                 if (gsi >= NR_IRQS_LEGACY)
975                         irq = gsi;
976                 else
977                         irq = gsi_top + gsi;
978         }
979 
980 #ifdef CONFIG_X86_32
981         /*
982          * PCI IRQ command line redirection. Yes, limits are hardcoded.
983          */
984         if ((pin >= 16) && (pin <= 23)) {
985                 if (pirq_entries[pin-16] != -1) {
986                         if (!pirq_entries[pin-16]) {
987                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
988                                                 "disabling PIRQ%d\n", pin-16);
989                         } else {
990                                 irq = pirq_entries[pin-16];
991                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
992                                                 "using PIRQ%d -> IRQ %d\n",
993                                                 pin-16, irq);
994                         }
995                 }
996         }
997 #endif
998 
999         return irq;
1000 }
1001 
1002 /*
1003  * Find a specific PCI IRQ entry.
1004  * Not an __init, possibly needed by modules
1005  */
1006 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1007                                 struct io_apic_irq_attr *irq_attr)
1008 {
1009         int ioapic_idx, i, best_guess = -1;
1010 
1011         apic_printk(APIC_DEBUG,
1012                     "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1013                     bus, slot, pin);
1014         if (test_bit(bus, mp_bus_not_pci)) {
1015                 apic_printk(APIC_VERBOSE,
1016                             "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1017                 return -1;
1018         }
1019         for (i = 0; i < mp_irq_entries; i++) {
1020                 int lbus = mp_irqs[i].srcbus;
1021 
1022                 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1023                         if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1024                             mp_irqs[i].dstapic == MP_APIC_ALL)
1025                                 break;
1026 
1027                 if (!test_bit(lbus, mp_bus_not_pci) &&
1028                     !mp_irqs[i].irqtype &&
1029                     (bus == lbus) &&
1030                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1031                         int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1032 
1033                         if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1034                                 continue;
1035 
1036                         if (pin == (mp_irqs[i].srcbusirq & 3)) {
1037                                 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1038                                                      mp_irqs[i].dstirq,
1039                                                      irq_trigger(i),
1040                                                      irq_polarity(i));
1041                                 return irq;
1042                         }
1043                         /*
1044                          * Use the first all-but-pin matching entry as a
1045                          * best-guess fuzzy result for broken mptables.
1046                          */
1047                         if (best_guess < 0) {
1048                                 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1049                                                      mp_irqs[i].dstirq,
1050                                                      irq_trigger(i),
1051                                                      irq_polarity(i));
1052                                 best_guess = irq;
1053                         }
1054                 }
1055         }
1056         return best_guess;
1057 }
1058 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1059 
1060 void lock_vector_lock(void)
1061 {
1062         /* Used to the online set of cpus does not change
1063          * during assign_irq_vector.
1064          */
1065         raw_spin_lock(&vector_lock);
1066 }
1067 
1068 void unlock_vector_lock(void)
1069 {
1070         raw_spin_unlock(&vector_lock);
1071 }
1072 
1073 static int
1074 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1075 {
1076         /*
1077          * NOTE! The local APIC isn't very good at handling
1078          * multiple interrupts at the same interrupt level.
1079          * As the interrupt level is determined by taking the
1080          * vector number and shifting that right by 4, we
1081          * want to spread these out a bit so that they don't
1082          * all fall in the same interrupt level.
1083          *
1084          * Also, we've got to be careful not to trash gate
1085          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1086          */
1087         static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1088         static int current_offset = VECTOR_OFFSET_START % 16;
1089         int cpu, err;
1090         cpumask_var_t tmp_mask;
1091 
1092         if (cfg->move_in_progress)
1093                 return -EBUSY;
1094 
1095         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1096                 return -ENOMEM;
1097 
1098         /* Only try and allocate irqs on cpus that are present */
1099         err = -ENOSPC;
1100         cpumask_clear(cfg->old_domain);
1101         cpu = cpumask_first_and(mask, cpu_online_mask);
1102         while (cpu < nr_cpu_ids) {
1103                 int new_cpu, vector, offset;
1104 
1105                 apic->vector_allocation_domain(cpu, tmp_mask, mask);
1106 
1107                 if (cpumask_subset(tmp_mask, cfg->domain)) {
1108                         err = 0;
1109                         if (cpumask_equal(tmp_mask, cfg->domain))
1110                                 break;
1111                         /*
1112                          * New cpumask using the vector is a proper subset of
1113                          * the current in use mask. So cleanup the vector
1114                          * allocation for the members that are not used anymore.
1115                          */
1116                         cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask);
1117                         cfg->move_in_progress =
1118                            cpumask_intersects(cfg->old_domain, cpu_online_mask);
1119                         cpumask_and(cfg->domain, cfg->domain, tmp_mask);
1120                         break;
1121                 }
1122 
1123                 vector = current_vector;
1124                 offset = current_offset;
1125 next:
1126                 vector += 16;
1127                 if (vector >= first_system_vector) {
1128                         offset = (offset + 1) % 16;
1129                         vector = FIRST_EXTERNAL_VECTOR + offset;
1130                 }
1131 
1132                 if (unlikely(current_vector == vector)) {
1133                         cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask);
1134                         cpumask_andnot(tmp_mask, mask, cfg->old_domain);
1135                         cpu = cpumask_first_and(tmp_mask, cpu_online_mask);
1136                         continue;
1137                 }
1138 
1139                 if (test_bit(vector, used_vectors))
1140                         goto next;
1141 
1142                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) {
1143                         if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNDEFINED)
1144                                 goto next;
1145                 }
1146                 /* Found one! */
1147                 current_vector = vector;
1148                 current_offset = offset;
1149                 if (cfg->vector) {
1150                         cpumask_copy(cfg->old_domain, cfg->domain);
1151                         cfg->move_in_progress =
1152                            cpumask_intersects(cfg->old_domain, cpu_online_mask);
1153                 }
1154                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1155                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1156                 cfg->vector = vector;
1157                 cpumask_copy(cfg->domain, tmp_mask);
1158                 err = 0;
1159                 break;
1160         }
1161         free_cpumask_var(tmp_mask);
1162         return err;
1163 }
1164 
1165 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1166 {
1167         int err;
1168         unsigned long flags;
1169 
1170         raw_spin_lock_irqsave(&vector_lock, flags);
1171         err = __assign_irq_vector(irq, cfg, mask);
1172         raw_spin_unlock_irqrestore(&vector_lock, flags);
1173         return err;
1174 }
1175 
1176 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1177 {
1178         int cpu, vector;
1179 
1180         BUG_ON(!cfg->vector);
1181 
1182         vector = cfg->vector;
1183         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1184                 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
1185 
1186         cfg->vector = 0;
1187         cpumask_clear(cfg->domain);
1188 
1189         if (likely(!cfg->move_in_progress))
1190                 return;
1191         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1192                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1193                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1194                                 continue;
1195                         per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
1196                         break;
1197                 }
1198         }
1199         cfg->move_in_progress = 0;
1200 }
1201 
1202 void __setup_vector_irq(int cpu)
1203 {
1204         /* Initialize vector_irq on a new cpu */
1205         int irq, vector;
1206         struct irq_cfg *cfg;
1207 
1208         /*
1209          * vector_lock will make sure that we don't run into irq vector
1210          * assignments that might be happening on another cpu in parallel,
1211          * while we setup our initial vector to irq mappings.
1212          */
1213         raw_spin_lock(&vector_lock);
1214         /* Mark the inuse vectors */
1215         for_each_active_irq(irq) {
1216                 cfg = irq_get_chip_data(irq);
1217                 if (!cfg)
1218                         continue;
1219 
1220                 if (!cpumask_test_cpu(cpu, cfg->domain))
1221                         continue;
1222                 vector = cfg->vector;
1223                 per_cpu(vector_irq, cpu)[vector] = irq;
1224         }
1225         /* Mark the free vectors */
1226         for (vector = 0; vector < NR_VECTORS; ++vector) {
1227                 irq = per_cpu(vector_irq, cpu)[vector];
1228                 if (irq <= VECTOR_UNDEFINED)
1229                         continue;
1230 
1231                 cfg = irq_cfg(irq);
1232                 if (!cpumask_test_cpu(cpu, cfg->domain))
1233                         per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED;
1234         }
1235         raw_spin_unlock(&vector_lock);
1236 }
1237 
1238 static struct irq_chip ioapic_chip;
1239 
1240 #ifdef CONFIG_X86_32
1241 static inline int IO_APIC_irq_trigger(int irq)
1242 {
1243         int apic, idx, pin;
1244 
1245         for (apic = 0; apic < nr_ioapics; apic++) {
1246                 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1247                         idx = find_irq_entry(apic, pin, mp_INT);
1248                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1249                                 return irq_trigger(idx);
1250                 }
1251         }
1252         /*
1253          * nonexistent IRQs are edge default
1254          */
1255         return 0;
1256 }
1257 #else
1258 static inline int IO_APIC_irq_trigger(int irq)
1259 {
1260         return 1;
1261 }
1262 #endif
1263 
1264 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1265                                  unsigned long trigger)
1266 {
1267         struct irq_chip *chip = &ioapic_chip;
1268         irq_flow_handler_t hdl;
1269         bool fasteoi;
1270 
1271         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1272             trigger == IOAPIC_LEVEL) {
1273                 irq_set_status_flags(irq, IRQ_LEVEL);
1274                 fasteoi = true;
1275         } else {
1276                 irq_clear_status_flags(irq, IRQ_LEVEL);
1277                 fasteoi = false;
1278         }
1279 
1280         if (setup_remapped_irq(irq, cfg, chip))
1281                 fasteoi = trigger != 0;
1282 
1283         hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1284         irq_set_chip_and_handler_name(irq, chip, hdl,
1285                                       fasteoi ? "fasteoi" : "edge");
1286 }
1287 
1288 int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1289                               unsigned int destination, int vector,
1290                               struct io_apic_irq_attr *attr)
1291 {
1292         memset(entry, 0, sizeof(*entry));
1293 
1294         entry->delivery_mode = apic->irq_delivery_mode;
1295         entry->dest_mode     = apic->irq_dest_mode;
1296         entry->dest          = destination;
1297         entry->vector        = vector;
1298         entry->mask          = 0;                       /* enable IRQ */
1299         entry->trigger       = attr->trigger;
1300         entry->polarity      = attr->polarity;
1301 
1302         /*
1303          * Mask level triggered irqs.
1304          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1305          */
1306         if (attr->trigger)
1307                 entry->mask = 1;
1308 
1309         return 0;
1310 }
1311 
1312 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1313                                 struct io_apic_irq_attr *attr)
1314 {
1315         struct IO_APIC_route_entry entry;
1316         unsigned int dest;
1317 
1318         if (!IO_APIC_IRQ(irq))
1319                 return;
1320 
1321         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1322                 return;
1323 
1324         if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(),
1325                                          &dest)) {
1326                 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1327                         mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1328                 __clear_irq_vector(irq, cfg);
1329 
1330                 return;
1331         }
1332 
1333         apic_printk(APIC_VERBOSE,KERN_DEBUG
1334                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1335                     "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1336                     attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1337                     cfg->vector, irq, attr->trigger, attr->polarity, dest);
1338 
1339         if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) {
1340                 pr_warn("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1341                         mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1342                 __clear_irq_vector(irq, cfg);
1343 
1344                 return;
1345         }
1346 
1347         ioapic_register_intr(irq, cfg, attr->trigger);
1348         if (irq < legacy_pic->nr_legacy_irqs)
1349                 legacy_pic->mask(irq);
1350 
1351         ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1352 }
1353 
1354 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1355 {
1356         if (idx != -1)
1357                 return false;
1358 
1359         apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1360                     mpc_ioapic_id(ioapic_idx), pin);
1361         return true;
1362 }
1363 
1364 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1365 {
1366         int idx, node = cpu_to_node(0);
1367         struct io_apic_irq_attr attr;
1368         unsigned int pin, irq;
1369 
1370         for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1371                 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1372                 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1373                         continue;
1374 
1375                 irq = pin_2_irq(idx, ioapic_idx, pin);
1376 
1377                 if ((ioapic_idx > 0) && (irq > 16))
1378                         continue;
1379 
1380                 /*
1381                  * Skip the timer IRQ if there's a quirk handler
1382                  * installed and if it returns 1:
1383                  */
1384                 if (apic->multi_timer_check &&
1385                     apic->multi_timer_check(ioapic_idx, irq))
1386                         continue;
1387 
1388                 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1389                                      irq_polarity(idx));
1390 
1391                 io_apic_setup_irq_pin(irq, node, &attr);
1392         }
1393 }
1394 
1395 static void __init setup_IO_APIC_irqs(void)
1396 {
1397         unsigned int ioapic_idx;
1398 
1399         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1400 
1401         for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1402                 __io_apic_setup_irqs(ioapic_idx);
1403 }
1404 
1405 /*
1406  * for the gsit that is not in first ioapic
1407  * but could not use acpi_register_gsi()
1408  * like some special sci in IBM x3330
1409  */
1410 void setup_IO_APIC_irq_extra(u32 gsi)
1411 {
1412         int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1413         struct io_apic_irq_attr attr;
1414 
1415         /*
1416          * Convert 'gsi' to 'ioapic.pin'.
1417          */
1418         ioapic_idx = mp_find_ioapic(gsi);
1419         if (ioapic_idx < 0)
1420                 return;
1421 
1422         pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1423         idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1424         if (idx == -1)
1425                 return;
1426 
1427         irq = pin_2_irq(idx, ioapic_idx, pin);
1428 
1429         /* Only handle the non legacy irqs on secondary ioapics */
1430         if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1431                 return;
1432 
1433         set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1434                              irq_polarity(idx));
1435 
1436         io_apic_setup_irq_pin_once(irq, node, &attr);
1437 }
1438 
1439 /*
1440  * Set up the timer pin, possibly with the 8259A-master behind.
1441  */
1442 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1443                                         unsigned int pin, int vector)
1444 {
1445         struct IO_APIC_route_entry entry;
1446         unsigned int dest;
1447 
1448         memset(&entry, 0, sizeof(entry));
1449 
1450         /*
1451          * We use logical delivery to get the timer IRQ
1452          * to the first CPU.
1453          */
1454         if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(),
1455                                                   apic->target_cpus(), &dest)))
1456                 dest = BAD_APICID;
1457 
1458         entry.dest_mode = apic->irq_dest_mode;
1459         entry.mask = 0;                 /* don't mask IRQ for edge */
1460         entry.dest = dest;
1461         entry.delivery_mode = apic->irq_delivery_mode;
1462         entry.polarity = 0;
1463         entry.trigger = 0;
1464         entry.vector = vector;
1465 
1466         /*
1467          * The timer IRQ doesn't have to know that behind the
1468          * scene we may have a 8259A-master in AEOI mode ...
1469          */
1470         irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1471                                       "edge");
1472 
1473         /*
1474          * Add it to the IO-APIC irq-routing table:
1475          */
1476         ioapic_write_entry(ioapic_idx, pin, entry);
1477 }
1478 
1479 void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1480 {
1481         int i;
1482 
1483         pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1484 
1485         for (i = 0; i <= nr_entries; i++) {
1486                 struct IO_APIC_route_entry entry;
1487 
1488                 entry = ioapic_read_entry(apic, i);
1489 
1490                 pr_debug(" %02x %02X  ", i, entry.dest);
1491                 pr_cont("%1d    %1d    %1d   %1d   %1d    "
1492                         "%1d    %1d    %02X\n",
1493                         entry.mask,
1494                         entry.trigger,
1495                         entry.irr,
1496                         entry.polarity,
1497                         entry.delivery_status,
1498                         entry.dest_mode,
1499                         entry.delivery_mode,
1500                         entry.vector);
1501         }
1502 }
1503 
1504 void intel_ir_io_apic_print_entries(unsigned int apic,
1505                                     unsigned int nr_entries)
1506 {
1507         int i;
1508 
1509         pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1510 
1511         for (i = 0; i <= nr_entries; i++) {
1512                 struct IR_IO_APIC_route_entry *ir_entry;
1513                 struct IO_APIC_route_entry entry;
1514 
1515                 entry = ioapic_read_entry(apic, i);
1516 
1517                 ir_entry = (struct IR_IO_APIC_route_entry *)&entry;
1518 
1519                 pr_debug(" %02x %04X ", i, ir_entry->index);
1520                 pr_cont("%1d   %1d    %1d    %1d   %1d   "
1521                         "%1d    %1d     %X    %02X\n",
1522                         ir_entry->format,
1523                         ir_entry->mask,
1524                         ir_entry->trigger,
1525                         ir_entry->irr,
1526                         ir_entry->polarity,
1527                         ir_entry->delivery_status,
1528                         ir_entry->index2,
1529                         ir_entry->zero,
1530                         ir_entry->vector);
1531         }
1532 }
1533 
1534 void ioapic_zap_locks(void)
1535 {
1536         raw_spin_lock_init(&ioapic_lock);
1537 }
1538 
1539 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1540 {
1541         union IO_APIC_reg_00 reg_00;
1542         union IO_APIC_reg_01 reg_01;
1543         union IO_APIC_reg_02 reg_02;
1544         union IO_APIC_reg_03 reg_03;
1545         unsigned long flags;
1546 
1547         raw_spin_lock_irqsave(&ioapic_lock, flags);
1548         reg_00.raw = io_apic_read(ioapic_idx, 0);
1549         reg_01.raw = io_apic_read(ioapic_idx, 1);
1550         if (reg_01.bits.version >= 0x10)
1551                 reg_02.raw = io_apic_read(ioapic_idx, 2);
1552         if (reg_01.bits.version >= 0x20)
1553                 reg_03.raw = io_apic_read(ioapic_idx, 3);
1554         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1555 
1556         printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1557         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1558         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1559         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1560         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1561 
1562         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1563         printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
1564                 reg_01.bits.entries);
1565 
1566         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1567         printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
1568                 reg_01.bits.version);
1569 
1570         /*
1571          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1572          * but the value of reg_02 is read as the previous read register
1573          * value, so ignore it if reg_02 == reg_01.
1574          */
1575         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1576                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1577                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1578         }
1579 
1580         /*
1581          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1582          * or reg_03, but the value of reg_0[23] is read as the previous read
1583          * register value, so ignore it if reg_03 == reg_0[12].
1584          */
1585         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1586             reg_03.raw != reg_01.raw) {
1587                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1588                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1589         }
1590 
1591         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1592 
1593         x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries);
1594 }
1595 
1596 __apicdebuginit(void) print_IO_APICs(void)
1597 {
1598         int ioapic_idx;
1599         struct irq_cfg *cfg;
1600         unsigned int irq;
1601         struct irq_chip *chip;
1602 
1603         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1604         for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1605                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1606                        mpc_ioapic_id(ioapic_idx),
1607                        ioapics[ioapic_idx].nr_registers);
1608 
1609         /*
1610          * We are a bit conservative about what we expect.  We have to
1611          * know about every hardware change ASAP.
1612          */
1613         printk(KERN_INFO "testing the IO APIC.......................\n");
1614 
1615         for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1616                 print_IO_APIC(ioapic_idx);
1617 
1618         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1619         for_each_active_irq(irq) {
1620                 struct irq_pin_list *entry;
1621 
1622                 chip = irq_get_chip(irq);
1623                 if (chip != &ioapic_chip)
1624                         continue;
1625 
1626                 cfg = irq_get_chip_data(irq);
1627                 if (!cfg)
1628                         continue;
1629                 entry = cfg->irq_2_pin;
1630                 if (!entry)
1631                         continue;
1632                 printk(KERN_DEBUG "IRQ%d ", irq);
1633                 for_each_irq_pin(entry, cfg->irq_2_pin)
1634                         pr_cont("-> %d:%d", entry->apic, entry->pin);
1635                 pr_cont("\n");
1636         }
1637 
1638         printk(KERN_INFO ".................................... done.\n");
1639 }
1640 
1641 __apicdebuginit(void) print_APIC_field(int base)
1642 {
1643         int i;
1644 
1645         printk(KERN_DEBUG);
1646 
1647         for (i = 0; i < 8; i++)
1648                 pr_cont("%08x", apic_read(base + i*0x10));
1649 
1650         pr_cont("\n");
1651 }
1652 
1653 __apicdebuginit(void) print_local_APIC(void *dummy)
1654 {
1655         unsigned int i, v, ver, maxlvt;
1656         u64 icr;
1657 
1658         printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1659                 smp_processor_id(), hard_smp_processor_id());
1660         v = apic_read(APIC_ID);
1661         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1662         v = apic_read(APIC_LVR);
1663         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1664         ver = GET_APIC_VERSION(v);
1665         maxlvt = lapic_get_maxlvt();
1666 
1667         v = apic_read(APIC_TASKPRI);
1668         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1669 
1670         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1671                 if (!APIC_XAPIC(ver)) {
1672                         v = apic_read(APIC_ARBPRI);
1673                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1674                                v & APIC_ARBPRI_MASK);
1675                 }
1676                 v = apic_read(APIC_PROCPRI);
1677                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1678         }
1679 
1680         /*
1681          * Remote read supported only in the 82489DX and local APIC for
1682          * Pentium processors.
1683          */
1684         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1685                 v = apic_read(APIC_RRR);
1686                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1687         }
1688 
1689         v = apic_read(APIC_LDR);
1690         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1691         if (!x2apic_enabled()) {
1692                 v = apic_read(APIC_DFR);
1693                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1694         }
1695         v = apic_read(APIC_SPIV);
1696         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1697 
1698         printk(KERN_DEBUG "... APIC ISR field:\n");
1699         print_APIC_field(APIC_ISR);
1700         printk(KERN_DEBUG "... APIC TMR field:\n");
1701         print_APIC_field(APIC_TMR);
1702         printk(KERN_DEBUG "... APIC IRR field:\n");
1703         print_APIC_field(APIC_IRR);
1704 
1705         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1706                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1707                         apic_write(APIC_ESR, 0);
1708 
1709                 v = apic_read(APIC_ESR);
1710                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1711         }
1712 
1713         icr = apic_icr_read();
1714         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1715         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1716 
1717         v = apic_read(APIC_LVTT);
1718         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1719 
1720         if (maxlvt > 3) {                       /* PC is LVT#4. */
1721                 v = apic_read(APIC_LVTPC);
1722                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1723         }
1724         v = apic_read(APIC_LVT0);
1725         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1726         v = apic_read(APIC_LVT1);
1727         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1728 
1729         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1730                 v = apic_read(APIC_LVTERR);
1731                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1732         }
1733 
1734         v = apic_read(APIC_TMICT);
1735         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1736         v = apic_read(APIC_TMCCT);
1737         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1738         v = apic_read(APIC_TDCR);
1739         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1740 
1741         if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1742                 v = apic_read(APIC_EFEAT);
1743                 maxlvt = (v >> 16) & 0xff;
1744                 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1745                 v = apic_read(APIC_ECTRL);
1746                 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1747                 for (i = 0; i < maxlvt; i++) {
1748                         v = apic_read(APIC_EILVTn(i));
1749                         printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1750                 }
1751         }
1752         pr_cont("\n");
1753 }
1754 
1755 __apicdebuginit(void) print_local_APICs(int maxcpu)
1756 {
1757         int cpu;
1758 
1759         if (!maxcpu)
1760                 return;
1761 
1762         preempt_disable();
1763         for_each_online_cpu(cpu) {
1764                 if (cpu >= maxcpu)
1765                         break;
1766                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1767         }
1768         preempt_enable();
1769 }
1770 
1771 __apicdebuginit(void) print_PIC(void)
1772 {
1773         unsigned int v;
1774         unsigned long flags;
1775 
1776         if (!legacy_pic->nr_legacy_irqs)
1777                 return;
1778 
1779         printk(KERN_DEBUG "\nprinting PIC contents\n");
1780 
1781         raw_spin_lock_irqsave(&i8259A_lock, flags);
1782 
1783         v = inb(0xa1) << 8 | inb(0x21);
1784         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1785 
1786         v = inb(0xa0) << 8 | inb(0x20);
1787         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1788 
1789         outb(0x0b,0xa0);
1790         outb(0x0b,0x20);
1791         v = inb(0xa0) << 8 | inb(0x20);
1792         outb(0x0a,0xa0);
1793         outb(0x0a,0x20);
1794 
1795         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1796 
1797         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1798 
1799         v = inb(0x4d1) << 8 | inb(0x4d0);
1800         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1801 }
1802 
1803 static int __initdata show_lapic = 1;
1804 static __init int setup_show_lapic(char *arg)
1805 {
1806         int num = -1;
1807 
1808         if (strcmp(arg, "all") == 0) {
1809                 show_lapic = CONFIG_NR_CPUS;
1810         } else {
1811                 get_option(&arg, &num);
1812                 if (num >= 0)
1813                         show_lapic = num;
1814         }
1815 
1816         return 1;
1817 }
1818 __setup("show_lapic=", setup_show_lapic);
1819 
1820 __apicdebuginit(int) print_ICs(void)
1821 {
1822         if (apic_verbosity == APIC_QUIET)
1823                 return 0;
1824 
1825         print_PIC();
1826 
1827         /* don't print out if apic is not there */
1828         if (!cpu_has_apic && !apic_from_smp_config())
1829                 return 0;
1830 
1831         print_local_APICs(show_lapic);
1832         print_IO_APICs();
1833 
1834         return 0;
1835 }
1836 
1837 late_initcall(print_ICs);
1838 
1839 
1840 /* Where if anywhere is the i8259 connect in external int mode */
1841 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1842 
1843 void __init enable_IO_APIC(void)
1844 {
1845         int i8259_apic, i8259_pin;
1846         int apic;
1847 
1848         if (!legacy_pic->nr_legacy_irqs)
1849                 return;
1850 
1851         for(apic = 0; apic < nr_ioapics; apic++) {
1852                 int pin;
1853                 /* See if any of the pins is in ExtINT mode */
1854                 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1855                         struct IO_APIC_route_entry entry;
1856                         entry = ioapic_read_entry(apic, pin);
1857 
1858                         /* If the interrupt line is enabled and in ExtInt mode
1859                          * I have found the pin where the i8259 is connected.
1860                          */
1861                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1862                                 ioapic_i8259.apic = apic;
1863                                 ioapic_i8259.pin  = pin;
1864                                 goto found_i8259;
1865                         }
1866                 }
1867         }
1868  found_i8259:
1869         /* Look to see what if the MP table has reported the ExtINT */
1870         /* If we could not find the appropriate pin by looking at the ioapic
1871          * the i8259 probably is not connected the ioapic but give the
1872          * mptable a chance anyway.
1873          */
1874         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1875         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1876         /* Trust the MP table if nothing is setup in the hardware */
1877         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1878                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1879                 ioapic_i8259.pin  = i8259_pin;
1880                 ioapic_i8259.apic = i8259_apic;
1881         }
1882         /* Complain if the MP table and the hardware disagree */
1883         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1884                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1885         {
1886                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1887         }
1888 
1889         /*
1890          * Do not trust the IO-APIC being empty at bootup
1891          */
1892         clear_IO_APIC();
1893 }
1894 
1895 void native_disable_io_apic(void)
1896 {
1897         /*
1898          * If the i8259 is routed through an IOAPIC
1899          * Put that IOAPIC in virtual wire mode
1900          * so legacy interrupts can be delivered.
1901          */
1902         if (ioapic_i8259.pin != -1) {
1903                 struct IO_APIC_route_entry entry;
1904 
1905                 memset(&entry, 0, sizeof(entry));
1906                 entry.mask            = 0; /* Enabled */
1907                 entry.trigger         = 0; /* Edge */
1908                 entry.irr             = 0;
1909                 entry.polarity        = 0; /* High */
1910                 entry.delivery_status = 0;
1911                 entry.dest_mode       = 0; /* Physical */
1912                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1913                 entry.vector          = 0;
1914                 entry.dest            = read_apic_id();
1915 
1916                 /*
1917                  * Add it to the IO-APIC irq-routing table:
1918                  */
1919                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1920         }
1921 
1922         if (cpu_has_apic || apic_from_smp_config())
1923                 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1924 
1925 }
1926 
1927 /*
1928  * Not an __init, needed by the reboot code
1929  */
1930 void disable_IO_APIC(void)
1931 {
1932         /*
1933          * Clear the IO-APIC before rebooting:
1934          */
1935         clear_IO_APIC();
1936 
1937         if (!legacy_pic->nr_legacy_irqs)
1938                 return;
1939 
1940         x86_io_apic_ops.disable();
1941 }
1942 
1943 #ifdef CONFIG_X86_32
1944 /*
1945  * function to set the IO-APIC physical IDs based on the
1946  * values stored in the MPC table.
1947  *
1948  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1949  */
1950 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1951 {
1952         union IO_APIC_reg_00 reg_00;
1953         physid_mask_t phys_id_present_map;
1954         int ioapic_idx;
1955         int i;
1956         unsigned char old_id;
1957         unsigned long flags;
1958 
1959         /*
1960          * This is broken; anything with a real cpu count has to
1961          * circumvent this idiocy regardless.
1962          */
1963         apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1964 
1965         /*
1966          * Set the IOAPIC ID to the value stored in the MPC table.
1967          */
1968         for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1969                 /* Read the register 0 value */
1970                 raw_spin_lock_irqsave(&ioapic_lock, flags);
1971                 reg_00.raw = io_apic_read(ioapic_idx, 0);
1972                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1973 
1974                 old_id = mpc_ioapic_id(ioapic_idx);
1975 
1976                 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1977                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1978                                 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1979                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1980                                 reg_00.bits.ID);
1981                         ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1982                 }
1983 
1984                 /*
1985                  * Sanity check, is the ID really free? Every APIC in a
1986                  * system must have a unique ID or we get lots of nice
1987                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1988                  */
1989                 if (apic->check_apicid_used(&phys_id_present_map,
1990                                             mpc_ioapic_id(ioapic_idx))) {
1991                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1992                                 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1993                         for (i = 0; i < get_physical_broadcast(); i++)
1994                                 if (!physid_isset(i, phys_id_present_map))
1995                                         break;
1996                         if (i >= get_physical_broadcast())
1997                                 panic("Max APIC ID exceeded!\n");
1998                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1999                                 i);
2000                         physid_set(i, phys_id_present_map);
2001                         ioapics[ioapic_idx].mp_config.apicid = i;
2002                 } else {
2003                         physid_mask_t tmp;
2004                         apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2005                                                     &tmp);
2006                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2007                                         "phys_id_present_map\n",
2008                                         mpc_ioapic_id(ioapic_idx));
2009                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2010                 }
2011 
2012                 /*
2013                  * We need to adjust the IRQ routing table
2014                  * if the ID changed.
2015                  */
2016                 if (old_id != mpc_ioapic_id(ioapic_idx))
2017                         for (i = 0; i < mp_irq_entries; i++)
2018                                 if (mp_irqs[i].dstapic == old_id)
2019                                         mp_irqs[i].dstapic
2020                                                 = mpc_ioapic_id(ioapic_idx);
2021 
2022                 /*
2023                  * Update the ID register according to the right value
2024                  * from the MPC table if they are different.
2025                  */
2026                 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2027                         continue;
2028 
2029                 apic_printk(APIC_VERBOSE, KERN_INFO
2030                         "...changing IO-APIC physical APIC ID to %d ...",
2031                         mpc_ioapic_id(ioapic_idx));
2032 
2033                 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2034                 raw_spin_lock_irqsave(&ioapic_lock, flags);
2035                 io_apic_write(ioapic_idx, 0, reg_00.raw);
2036                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2037 
2038                 /*
2039                  * Sanity check
2040                  */
2041                 raw_spin_lock_irqsave(&ioapic_lock, flags);
2042                 reg_00.raw = io_apic_read(ioapic_idx, 0);
2043                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2044                 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2045                         pr_cont("could not set ID!\n");
2046                 else
2047                         apic_printk(APIC_VERBOSE, " ok.\n");
2048         }
2049 }
2050 
2051 void __init setup_ioapic_ids_from_mpc(void)
2052 {
2053 
2054         if (acpi_ioapic)
2055                 return;
2056         /*
2057          * Don't check I/O APIC IDs for xAPIC systems.  They have
2058          * no meaning without the serial APIC bus.
2059          */
2060         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2061                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2062                 return;
2063         setup_ioapic_ids_from_mpc_nocheck();
2064 }
2065 #endif
2066 
2067 int no_timer_check __initdata;
2068 
2069 static int __init notimercheck(char *s)
2070 {
2071         no_timer_check = 1;
2072         return 1;
2073 }
2074 __setup("no_timer_check", notimercheck);
2075 
2076 /*
2077  * There is a nasty bug in some older SMP boards, their mptable lies
2078  * about the timer IRQ. We do the following to work around the situation:
2079  *
2080  *      - timer IRQ defaults to IO-APIC IRQ
2081  *      - if this function detects that timer IRQs are defunct, then we fall
2082  *        back to ISA timer IRQs
2083  */
2084 static int __init timer_irq_works(void)
2085 {
2086         unsigned long t1 = jiffies;
2087         unsigned long flags;
2088 
2089         if (no_timer_check)
2090                 return 1;
2091 
2092         local_save_flags(flags);
2093         local_irq_enable();
2094         /* Let ten ticks pass... */
2095         mdelay((10 * 1000) / HZ);
2096         local_irq_restore(flags);
2097 
2098         /*
2099          * Expect a few ticks at least, to be sure some possible
2100          * glue logic does not lock up after one or two first
2101          * ticks in a non-ExtINT mode.  Also the local APIC
2102          * might have cached one ExtINT interrupt.  Finally, at
2103          * least one tick may be lost due to delays.
2104          */
2105 
2106         /* jiffies wrap? */
2107         if (time_after(jiffies, t1 + 4))
2108                 return 1;
2109         return 0;
2110 }
2111 
2112 /*
2113  * In the SMP+IOAPIC case it might happen that there are an unspecified
2114  * number of pending IRQ events unhandled. These cases are very rare,
2115  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2116  * better to do it this way as thus we do not have to be aware of
2117  * 'pending' interrupts in the IRQ path, except at this point.
2118  */
2119 /*
2120  * Edge triggered needs to resend any interrupt
2121  * that was delayed but this is now handled in the device
2122  * independent code.
2123  */
2124 
2125 /*
2126  * Starting up a edge-triggered IO-APIC interrupt is
2127  * nasty - we need to make sure that we get the edge.
2128  * If it is already asserted for some reason, we need
2129  * return 1 to indicate that is was pending.
2130  *
2131  * This is not complete - we should be able to fake
2132  * an edge even if it isn't on the 8259A...
2133  */
2134 
2135 static unsigned int startup_ioapic_irq(struct irq_data *data)
2136 {
2137         int was_pending = 0, irq = data->irq;
2138         unsigned long flags;
2139 
2140         raw_spin_lock_irqsave(&ioapic_lock, flags);
2141         if (irq < legacy_pic->nr_legacy_irqs) {
2142                 legacy_pic->mask(irq);
2143                 if (legacy_pic->irq_pending(irq))
2144                         was_pending = 1;
2145         }
2146         __unmask_ioapic(data->chip_data);
2147         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2148 
2149         return was_pending;
2150 }
2151 
2152 static int ioapic_retrigger_irq(struct irq_data *data)
2153 {
2154         struct irq_cfg *cfg = data->chip_data;
2155         unsigned long flags;
2156         int cpu;
2157 
2158         raw_spin_lock_irqsave(&vector_lock, flags);
2159         cpu = cpumask_first_and(cfg->domain, cpu_online_mask);
2160         apic->send_IPI_mask(cpumask_of(cpu), cfg->vector);
2161         raw_spin_unlock_irqrestore(&vector_lock, flags);
2162 
2163         return 1;
2164 }
2165 
2166 /*
2167  * Level and edge triggered IO-APIC interrupts need different handling,
2168  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2169  * handled with the level-triggered descriptor, but that one has slightly
2170  * more overhead. Level-triggered interrupts cannot be handled with the
2171  * edge-triggered handler, without risking IRQ storms and other ugly
2172  * races.
2173  */
2174 
2175 #ifdef CONFIG_SMP
2176 void send_cleanup_vector(struct irq_cfg *cfg)
2177 {
2178         cpumask_var_t cleanup_mask;
2179 
2180         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2181                 unsigned int i;
2182                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2183                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2184         } else {
2185                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2186                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2187                 free_cpumask_var(cleanup_mask);
2188         }
2189         cfg->move_in_progress = 0;
2190 }
2191 
2192 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2193 {
2194         unsigned vector, me;
2195 
2196         ack_APIC_irq();
2197         irq_enter();
2198         exit_idle();
2199 
2200         me = smp_processor_id();
2201         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2202                 int irq;
2203                 unsigned int irr;
2204                 struct irq_desc *desc;
2205                 struct irq_cfg *cfg;
2206                 irq = __this_cpu_read(vector_irq[vector]);
2207 
2208                 if (irq <= VECTOR_UNDEFINED)
2209                         continue;
2210 
2211                 desc = irq_to_desc(irq);
2212                 if (!desc)
2213                         continue;
2214 
2215                 cfg = irq_cfg(irq);
2216                 if (!cfg)
2217                         continue;
2218 
2219                 raw_spin_lock(&desc->lock);
2220 
2221                 /*
2222                  * Check if the irq migration is in progress. If so, we
2223                  * haven't received the cleanup request yet for this irq.
2224                  */
2225                 if (cfg->move_in_progress)
2226                         goto unlock;
2227 
2228                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2229                         goto unlock;
2230 
2231                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2232                 /*
2233                  * Check if the vector that needs to be cleanedup is
2234                  * registered at the cpu's IRR. If so, then this is not
2235                  * the best time to clean it up. Lets clean it up in the
2236                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2237                  * to myself.
2238                  */
2239                 if (irr  & (1 << (vector % 32))) {
2240                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2241                         goto unlock;
2242                 }
2243                 __this_cpu_write(vector_irq[vector], -1);
2244 unlock:
2245                 raw_spin_unlock(&desc->lock);
2246         }
2247 
2248         irq_exit();
2249 }
2250 
2251 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2252 {
2253         unsigned me;
2254 
2255         if (likely(!cfg->move_in_progress))
2256                 return;
2257 
2258         me = smp_processor_id();
2259 
2260         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2261                 send_cleanup_vector(cfg);
2262 }
2263 
2264 static void irq_complete_move(struct irq_cfg *cfg)
2265 {
2266         __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2267 }
2268 
2269 void irq_force_complete_move(int irq)
2270 {
2271         struct irq_cfg *cfg = irq_get_chip_data(irq);
2272 
2273         if (!cfg)
2274                 return;
2275 
2276         __irq_complete_move(cfg, cfg->vector);
2277 }
2278 #else
2279 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2280 #endif
2281 
2282 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2283 {
2284         int apic, pin;
2285         struct irq_pin_list *entry;
2286         u8 vector = cfg->vector;
2287 
2288         for_each_irq_pin(entry, cfg->irq_2_pin) {
2289                 unsigned int reg;
2290 
2291                 apic = entry->apic;
2292                 pin = entry->pin;
2293 
2294                 io_apic_write(apic, 0x11 + pin*2, dest);
2295                 reg = io_apic_read(apic, 0x10 + pin*2);
2296                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2297                 reg |= vector;
2298                 io_apic_modify(apic, 0x10 + pin*2, reg);
2299         }
2300 }
2301 
2302 /*
2303  * Either sets data->affinity to a valid value, and returns
2304  * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2305  * leaves data->affinity untouched.
2306  */
2307 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2308                           unsigned int *dest_id)
2309 {
2310         struct irq_cfg *cfg = data->chip_data;
2311         unsigned int irq = data->irq;
2312         int err;
2313 
2314         if (!config_enabled(CONFIG_SMP))
2315                 return -1;
2316 
2317         if (!cpumask_intersects(mask, cpu_online_mask))
2318                 return -EINVAL;
2319 
2320         err = assign_irq_vector(irq, cfg, mask);
2321         if (err)
2322                 return err;
2323 
2324         err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id);
2325         if (err) {
2326                 if (assign_irq_vector(irq, cfg, data->affinity))
2327                         pr_err("Failed to recover vector for irq %d\n", irq);
2328                 return err;
2329         }
2330 
2331         cpumask_copy(data->affinity, mask);
2332 
2333         return 0;
2334 }
2335 
2336 
2337 int native_ioapic_set_affinity(struct irq_data *data,
2338                                const struct cpumask *mask,
2339                                bool force)
2340 {
2341         unsigned int dest, irq = data->irq;
2342         unsigned long flags;
2343         int ret;
2344 
2345         if (!config_enabled(CONFIG_SMP))
2346                 return -1;
2347 
2348         raw_spin_lock_irqsave(&ioapic_lock, flags);
2349         ret = __ioapic_set_affinity(data, mask, &dest);
2350         if (!ret) {
2351                 /* Only the high 8 bits are valid. */
2352                 dest = SET_APIC_LOGICAL_ID(dest);
2353                 __target_IO_APIC_irq(irq, dest, data->chip_data);
2354                 ret = IRQ_SET_MASK_OK_NOCOPY;
2355         }
2356         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2357         return ret;
2358 }
2359 
2360 static void ack_apic_edge(struct irq_data *data)
2361 {
2362         irq_complete_move(data->chip_data);
2363         irq_move_irq(data);
2364         ack_APIC_irq();
2365 }
2366 
2367 atomic_t irq_mis_count;
2368 
2369 #ifdef CONFIG_GENERIC_PENDING_IRQ
2370 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
2371 {
2372         struct irq_pin_list *entry;
2373         unsigned long flags;
2374 
2375         raw_spin_lock_irqsave(&ioapic_lock, flags);
2376         for_each_irq_pin(entry, cfg->irq_2_pin) {
2377                 unsigned int reg;
2378                 int pin;
2379 
2380                 pin = entry->pin;
2381                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
2382                 /* Is the remote IRR bit set? */
2383                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
2384                         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2385                         return true;
2386                 }
2387         }
2388         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2389 
2390         return false;
2391 }
2392 
2393 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2394 {
2395         /* If we are moving the irq we need to mask it */
2396         if (unlikely(irqd_is_setaffinity_pending(data))) {
2397                 mask_ioapic(cfg);
2398                 return true;
2399         }
2400         return false;
2401 }
2402 
2403 static inline void ioapic_irqd_unmask(struct irq_data *data,
2404                                       struct irq_cfg *cfg, bool masked)
2405 {
2406         if (unlikely(masked)) {
2407                 /* Only migrate the irq if the ack has been received.
2408                  *
2409                  * On rare occasions the broadcast level triggered ack gets
2410                  * delayed going to ioapics, and if we reprogram the
2411                  * vector while Remote IRR is still set the irq will never
2412                  * fire again.
2413                  *
2414                  * To prevent this scenario we read the Remote IRR bit
2415                  * of the ioapic.  This has two effects.
2416                  * - On any sane system the read of the ioapic will
2417                  *   flush writes (and acks) going to the ioapic from
2418                  *   this cpu.
2419                  * - We get to see if the ACK has actually been delivered.
2420                  *
2421                  * Based on failed experiments of reprogramming the
2422                  * ioapic entry from outside of irq context starting
2423                  * with masking the ioapic entry and then polling until
2424                  * Remote IRR was clear before reprogramming the
2425                  * ioapic I don't trust the Remote IRR bit to be
2426                  * completey accurate.
2427                  *
2428                  * However there appears to be no other way to plug
2429                  * this race, so if the Remote IRR bit is not
2430                  * accurate and is causing problems then it is a hardware bug
2431                  * and you can go talk to the chipset vendor about it.
2432                  */
2433                 if (!io_apic_level_ack_pending(cfg))
2434                         irq_move_masked_irq(data);
2435                 unmask_ioapic(cfg);
2436         }
2437 }
2438 #else
2439 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2440 {
2441         return false;
2442 }
2443 static inline void ioapic_irqd_unmask(struct irq_data *data,
2444                                       struct irq_cfg *cfg, bool masked)
2445 {
2446 }
2447 #endif
2448 
2449 static void ack_apic_level(struct irq_data *data)
2450 {
2451         struct irq_cfg *cfg = data->chip_data;
2452         int i, irq = data->irq;
2453         unsigned long v;
2454         bool masked;
2455 
2456         irq_complete_move(cfg);
2457         masked = ioapic_irqd_mask(data, cfg);
2458 
2459         /*
2460          * It appears there is an erratum which affects at least version 0x11
2461          * of I/O APIC (that's the 82093AA and cores integrated into various
2462          * chipsets).  Under certain conditions a level-triggered interrupt is
2463          * erroneously delivered as edge-triggered one but the respective IRR
2464          * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2465          * message but it will never arrive and further interrupts are blocked
2466          * from the source.  The exact reason is so far unknown, but the
2467          * phenomenon was observed when two consecutive interrupt requests
2468          * from a given source get delivered to the same CPU and the source is
2469          * temporarily disabled in between.
2470          *
2471          * A workaround is to simulate an EOI message manually.  We achieve it
2472          * by setting the trigger mode to edge and then to level when the edge
2473          * trigger mode gets detected in the TMR of a local APIC for a
2474          * level-triggered interrupt.  We mask the source for the time of the
2475          * operation to prevent an edge-triggered interrupt escaping meanwhile.
2476          * The idea is from Manfred Spraul.  --macro
2477          *
2478          * Also in the case when cpu goes offline, fixup_irqs() will forward
2479          * any unhandled interrupt on the offlined cpu to the new cpu
2480          * destination that is handling the corresponding interrupt. This
2481          * interrupt forwarding is done via IPI's. Hence, in this case also
2482          * level-triggered io-apic interrupt will be seen as an edge
2483          * interrupt in the IRR. And we can't rely on the cpu's EOI
2484          * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2485          * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2486          * supporting EOI register, we do an explicit EOI to clear the
2487          * remote IRR and on IO-APIC's which don't have an EOI register,
2488          * we use the above logic (mask+edge followed by unmask+level) from
2489          * Manfred Spraul to clear the remote IRR.
2490          */
2491         i = cfg->vector;
2492         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2493 
2494         /*
2495          * We must acknowledge the irq before we move it or the acknowledge will
2496          * not propagate properly.
2497          */
2498         ack_APIC_irq();
2499 
2500         /*
2501          * Tail end of clearing remote IRR bit (either by delivering the EOI
2502          * message via io-apic EOI register write or simulating it using
2503          * mask+edge followed by unnask+level logic) manually when the
2504          * level triggered interrupt is seen as the edge triggered interrupt
2505          * at the cpu.
2506          */
2507         if (!(v & (1 << (i & 0x1f)))) {
2508                 atomic_inc(&irq_mis_count);
2509 
2510                 eoi_ioapic_irq(irq, cfg);
2511         }
2512 
2513         ioapic_irqd_unmask(data, cfg, masked);
2514 }
2515 
2516 static struct irq_chip ioapic_chip __read_mostly = {
2517         .name                   = "IO-APIC",
2518         .irq_startup            = startup_ioapic_irq,
2519         .irq_mask               = mask_ioapic_irq,
2520         .irq_unmask             = unmask_ioapic_irq,
2521         .irq_ack                = ack_apic_edge,
2522         .irq_eoi                = ack_apic_level,
2523         .irq_set_affinity       = native_ioapic_set_affinity,
2524         .irq_retrigger          = ioapic_retrigger_irq,
2525 };
2526 
2527 static inline void init_IO_APIC_traps(void)
2528 {
2529         struct irq_cfg *cfg;
2530         unsigned int irq;
2531 
2532         /*
2533          * NOTE! The local APIC isn't very good at handling
2534          * multiple interrupts at the same interrupt level.
2535          * As the interrupt level is determined by taking the
2536          * vector number and shifting that right by 4, we
2537          * want to spread these out a bit so that they don't
2538          * all fall in the same interrupt level.
2539          *
2540          * Also, we've got to be careful not to trash gate
2541          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2542          */
2543         for_each_active_irq(irq) {
2544                 cfg = irq_get_chip_data(irq);
2545                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2546                         /*
2547                          * Hmm.. We don't have an entry for this,
2548                          * so default to an old-fashioned 8259
2549                          * interrupt if we can..
2550                          */
2551                         if (irq < legacy_pic->nr_legacy_irqs)
2552                                 legacy_pic->make_irq(irq);
2553                         else
2554                                 /* Strange. Oh, well.. */
2555                                 irq_set_chip(irq, &no_irq_chip);
2556                 }
2557         }
2558 }
2559 
2560 /*
2561  * The local APIC irq-chip implementation:
2562  */
2563 
2564 static void mask_lapic_irq(struct irq_data *data)
2565 {
2566         unsigned long v;
2567 
2568         v = apic_read(APIC_LVT0);
2569         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2570 }
2571 
2572 static void unmask_lapic_irq(struct irq_data *data)
2573 {
2574         unsigned long v;
2575 
2576         v = apic_read(APIC_LVT0);
2577         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2578 }
2579 
2580 static void ack_lapic_irq(struct irq_data *data)
2581 {
2582         ack_APIC_irq();
2583 }
2584 
2585 static struct irq_chip lapic_chip __read_mostly = {
2586         .name           = "local-APIC",
2587         .irq_mask       = mask_lapic_irq,
2588         .irq_unmask     = unmask_lapic_irq,
2589         .irq_ack        = ack_lapic_irq,
2590 };
2591 
2592 static void lapic_register_intr(int irq)
2593 {
2594         irq_clear_status_flags(irq, IRQ_LEVEL);
2595         irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2596                                       "edge");
2597 }
2598 
2599 /*
2600  * This looks a bit hackish but it's about the only one way of sending
2601  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2602  * not support the ExtINT mode, unfortunately.  We need to send these
2603  * cycles as some i82489DX-based boards have glue logic that keeps the
2604  * 8259A interrupt line asserted until INTA.  --macro
2605  */
2606 static inline void __init unlock_ExtINT_logic(void)
2607 {
2608         int apic, pin, i;
2609         struct IO_APIC_route_entry entry0, entry1;
2610         unsigned char save_control, save_freq_select;
2611 
2612         pin  = find_isa_irq_pin(8, mp_INT);
2613         if (pin == -1) {
2614                 WARN_ON_ONCE(1);
2615                 return;
2616         }
2617         apic = find_isa_irq_apic(8, mp_INT);
2618         if (apic == -1) {
2619                 WARN_ON_ONCE(1);
2620                 return;
2621         }
2622 
2623         entry0 = ioapic_read_entry(apic, pin);
2624         clear_IO_APIC_pin(apic, pin);
2625 
2626         memset(&entry1, 0, sizeof(entry1));
2627 
2628         entry1.dest_mode = 0;                   /* physical delivery */
2629         entry1.mask = 0;                        /* unmask IRQ now */
2630         entry1.dest = hard_smp_processor_id();
2631         entry1.delivery_mode = dest_ExtINT;
2632         entry1.polarity = entry0.polarity;
2633         entry1.trigger = 0;
2634         entry1.vector = 0;
2635 
2636         ioapic_write_entry(apic, pin, entry1);
2637 
2638         save_control = CMOS_READ(RTC_CONTROL);
2639         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2640         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2641                    RTC_FREQ_SELECT);
2642         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2643 
2644         i = 100;
2645         while (i-- > 0) {
2646                 mdelay(10);
2647                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2648                         i -= 10;
2649         }
2650 
2651         CMOS_WRITE(save_control, RTC_CONTROL);
2652         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2653         clear_IO_APIC_pin(apic, pin);
2654 
2655         ioapic_write_entry(apic, pin, entry0);
2656 }
2657 
2658 static int disable_timer_pin_1 __initdata;
2659 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2660 static int __init disable_timer_pin_setup(char *arg)
2661 {
2662         disable_timer_pin_1 = 1;
2663         return 0;
2664 }
2665 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2666 
2667 int timer_through_8259 __initdata;
2668 
2669 /*
2670  * This code may look a bit paranoid, but it's supposed to cooperate with
2671  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2672  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2673  * fanatically on his truly buggy board.
2674  *
2675  * FIXME: really need to revamp this for all platforms.
2676  */
2677 static inline void __init check_timer(void)
2678 {
2679         struct irq_cfg *cfg = irq_get_chip_data(0);
2680         int node = cpu_to_node(0);
2681         int apic1, pin1, apic2, pin2;
2682         unsigned long flags;
2683         int no_pin1 = 0;
2684 
2685         local_irq_save(flags);
2686 
2687         /*
2688          * get/set the timer IRQ vector:
2689          */
2690         legacy_pic->mask(0);
2691         assign_irq_vector(0, cfg, apic->target_cpus());
2692 
2693         /*
2694          * As IRQ0 is to be enabled in the 8259A, the virtual
2695          * wire has to be disabled in the local APIC.  Also
2696          * timer interrupts need to be acknowledged manually in
2697          * the 8259A for the i82489DX when using the NMI
2698          * watchdog as that APIC treats NMIs as level-triggered.
2699          * The AEOI mode will finish them in the 8259A
2700          * automatically.
2701          */
2702         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2703         legacy_pic->init(1);
2704 
2705         pin1  = find_isa_irq_pin(0, mp_INT);
2706         apic1 = find_isa_irq_apic(0, mp_INT);
2707         pin2  = ioapic_i8259.pin;
2708         apic2 = ioapic_i8259.apic;
2709 
2710         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2711                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2712                     cfg->vector, apic1, pin1, apic2, pin2);
2713 
2714         /*
2715          * Some BIOS writers are clueless and report the ExtINTA
2716          * I/O APIC input from the cascaded 8259A as the timer
2717          * interrupt input.  So just in case, if only one pin
2718          * was found above, try it both directly and through the
2719          * 8259A.
2720          */
2721         if (pin1 == -1) {
2722                 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2723                 pin1 = pin2;
2724                 apic1 = apic2;
2725                 no_pin1 = 1;
2726         } else if (pin2 == -1) {
2727                 pin2 = pin1;
2728                 apic2 = apic1;
2729         }
2730 
2731         if (pin1 != -1) {
2732                 /*
2733                  * Ok, does IRQ0 through the IOAPIC work?
2734                  */
2735                 if (no_pin1) {
2736                         add_pin_to_irq_node(cfg, node, apic1, pin1);
2737                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2738                 } else {
2739                         /* for edge trigger, setup_ioapic_irq already
2740                          * leave it unmasked.
2741                          * so only need to unmask if it is level-trigger
2742                          * do we really have level trigger timer?
2743                          */
2744                         int idx;
2745                         idx = find_irq_entry(apic1, pin1, mp_INT);
2746                         if (idx != -1 && irq_trigger(idx))
2747                                 unmask_ioapic(cfg);
2748                 }
2749                 if (timer_irq_works()) {
2750                         if (disable_timer_pin_1 > 0)
2751                                 clear_IO_APIC_pin(0, pin1);
2752                         goto out;
2753                 }
2754                 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2755                 local_irq_disable();
2756                 clear_IO_APIC_pin(apic1, pin1);
2757                 if (!no_pin1)
2758                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2759                                     "8254 timer not connected to IO-APIC\n");
2760 
2761                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2762                             "(IRQ0) through the 8259A ...\n");
2763                 apic_printk(APIC_QUIET, KERN_INFO
2764                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2765                 /*
2766                  * legacy devices should be connected to IO APIC #0
2767                  */
2768                 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2769                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2770                 legacy_pic->unmask(0);
2771                 if (timer_irq_works()) {
2772                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2773                         timer_through_8259 = 1;
2774                         goto out;
2775                 }
2776                 /*
2777                  * Cleanup, just in case ...
2778                  */
2779                 local_irq_disable();
2780                 legacy_pic->mask(0);
2781                 clear_IO_APIC_pin(apic2, pin2);
2782                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2783         }
2784 
2785         apic_printk(APIC_QUIET, KERN_INFO
2786                     "...trying to set up timer as Virtual Wire IRQ...\n");
2787 
2788         lapic_register_intr(0);
2789         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2790         legacy_pic->unmask(0);
2791 
2792         if (timer_irq_works()) {
2793                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2794                 goto out;
2795         }
2796         local_irq_disable();
2797         legacy_pic->mask(0);
2798         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2799         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2800 
2801         apic_printk(APIC_QUIET, KERN_INFO
2802                     "...trying to set up timer as ExtINT IRQ...\n");
2803 
2804         legacy_pic->init(0);
2805         legacy_pic->make_irq(0);
2806         apic_write(APIC_LVT0, APIC_DM_EXTINT);
2807 
2808         unlock_ExtINT_logic();
2809 
2810         if (timer_irq_works()) {
2811                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2812                 goto out;
2813         }
2814         local_irq_disable();
2815         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2816         if (x2apic_preenabled)
2817                 apic_printk(APIC_QUIET, KERN_INFO
2818                             "Perhaps problem with the pre-enabled x2apic mode\n"
2819                             "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2820         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2821                 "report.  Then try booting with the 'noapic' option.\n");
2822 out:
2823         local_irq_restore(flags);
2824 }
2825 
2826 /*
2827  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2828  * to devices.  However there may be an I/O APIC pin available for
2829  * this interrupt regardless.  The pin may be left unconnected, but
2830  * typically it will be reused as an ExtINT cascade interrupt for
2831  * the master 8259A.  In the MPS case such a pin will normally be
2832  * reported as an ExtINT interrupt in the MP table.  With ACPI
2833  * there is no provision for ExtINT interrupts, and in the absence
2834  * of an override it would be treated as an ordinary ISA I/O APIC
2835  * interrupt, that is edge-triggered and unmasked by default.  We
2836  * used to do this, but it caused problems on some systems because
2837  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2838  * the same ExtINT cascade interrupt to drive the local APIC of the
2839  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
2840  * the I/O APIC in all cases now.  No actual device should request
2841  * it anyway.  --macro
2842  */
2843 #define PIC_IRQS        (1UL << PIC_CASCADE_IR)
2844 
2845 void __init setup_IO_APIC(void)
2846 {
2847 
2848         /*
2849          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2850          */
2851         io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2852 
2853         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2854         /*
2855          * Set up IO-APIC IRQ routing.
2856          */
2857         x86_init.mpparse.setup_ioapic_ids();
2858 
2859         sync_Arb_IDs();
2860         setup_IO_APIC_irqs();
2861         init_IO_APIC_traps();
2862         if (legacy_pic->nr_legacy_irqs)
2863                 check_timer();
2864 }
2865 
2866 /*
2867  *      Called after all the initialization is done. If we didn't find any
2868  *      APIC bugs then we can allow the modify fast path
2869  */
2870 
2871 static int __init io_apic_bug_finalize(void)
2872 {
2873         if (sis_apic_bug == -1)
2874                 sis_apic_bug = 0;
2875         return 0;
2876 }
2877 
2878 late_initcall(io_apic_bug_finalize);
2879 
2880 static void resume_ioapic_id(int ioapic_idx)
2881 {
2882         unsigned long flags;
2883         union IO_APIC_reg_00 reg_00;
2884 
2885         raw_spin_lock_irqsave(&ioapic_lock, flags);
2886         reg_00.raw = io_apic_read(ioapic_idx, 0);
2887         if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2888                 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2889                 io_apic_write(ioapic_idx, 0, reg_00.raw);
2890         }
2891         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2892 }
2893 
2894 static void ioapic_resume(void)
2895 {
2896         int ioapic_idx;
2897 
2898         for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
2899                 resume_ioapic_id(ioapic_idx);
2900 
2901         restore_ioapic_entries();
2902 }
2903 
2904 static struct syscore_ops ioapic_syscore_ops = {
2905         .suspend = save_ioapic_entries,
2906         .resume = ioapic_resume,
2907 };
2908 
2909 static int __init ioapic_init_ops(void)
2910 {
2911         register_syscore_ops(&ioapic_syscore_ops);
2912 
2913         return 0;
2914 }
2915 
2916 device_initcall(ioapic_init_ops);
2917 
2918 /*
2919  * Dynamic irq allocate and deallocation
2920  */
2921 unsigned int __create_irqs(unsigned int from, unsigned int count, int node)
2922 {
2923         struct irq_cfg **cfg;
2924         unsigned long flags;
2925         int irq, i;
2926 
2927         if (from < nr_irqs_gsi)
2928                 from = nr_irqs_gsi;
2929 
2930         cfg = kzalloc_node(count * sizeof(cfg[0]), GFP_KERNEL, node);
2931         if (!cfg)
2932                 return 0;
2933 
2934         irq = alloc_irqs_from(from, count, node);
2935         if (irq < 0)
2936                 goto out_cfgs;
2937 
2938         for (i = 0; i < count; i++) {
2939                 cfg[i] = alloc_irq_cfg(irq + i, node);
2940                 if (!cfg[i])
2941                         goto out_irqs;
2942         }
2943 
2944         raw_spin_lock_irqsave(&vector_lock, flags);
2945         for (i = 0; i < count; i++)
2946                 if (__assign_irq_vector(irq + i, cfg[i], apic->target_cpus()))
2947                         goto out_vecs;
2948         raw_spin_unlock_irqrestore(&vector_lock, flags);
2949 
2950         for (i = 0; i < count; i++) {
2951                 irq_set_chip_data(irq + i, cfg[i]);
2952                 irq_clear_status_flags(irq + i, IRQ_NOREQUEST);
2953         }
2954 
2955         kfree(cfg);
2956         return irq;
2957 
2958 out_vecs:
2959         for (i--; i >= 0; i--)
2960                 __clear_irq_vector(irq + i, cfg[i]);
2961         raw_spin_unlock_irqrestore(&vector_lock, flags);
2962 out_irqs:
2963         for (i = 0; i < count; i++)
2964                 free_irq_at(irq + i, cfg[i]);
2965 out_cfgs:
2966         kfree(cfg);
2967         return 0;
2968 }
2969 
2970 unsigned int create_irq_nr(unsigned int from, int node)
2971 {
2972         return __create_irqs(from, 1, node);
2973 }
2974 
2975 int create_irq(void)
2976 {
2977         int node = cpu_to_node(0);
2978         unsigned int irq_want;
2979         int irq;
2980 
2981         irq_want = nr_irqs_gsi;
2982         irq = create_irq_nr(irq_want, node);
2983 
2984         if (irq == 0)
2985                 irq = -1;
2986 
2987         return irq;
2988 }
2989 
2990 void destroy_irq(unsigned int irq)
2991 {
2992         struct irq_cfg *cfg = irq_get_chip_data(irq);
2993         unsigned long flags;
2994 
2995         irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
2996 
2997         free_remapped_irq(irq);
2998 
2999         raw_spin_lock_irqsave(&vector_lock, flags);
3000         __clear_irq_vector(irq, cfg);
3001         raw_spin_unlock_irqrestore(&vector_lock, flags);
3002         free_irq_at(irq, cfg);
3003 }
3004 
3005 void destroy_irqs(unsigned int irq, unsigned int count)
3006 {
3007         unsigned int i;
3008 
3009         for (i = 0; i < count; i++)
3010                 destroy_irq(irq + i);
3011 }
3012 
3013 /*
3014  * MSI message composition
3015  */
3016 void native_compose_msi_msg(struct pci_dev *pdev,
3017                             unsigned int irq, unsigned int dest,
3018                             struct msi_msg *msg, u8 hpet_id)
3019 {
3020         struct irq_cfg *cfg = irq_cfg(irq);
3021 
3022         msg->address_hi = MSI_ADDR_BASE_HI;
3023 
3024         if (x2apic_enabled())
3025                 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
3026 
3027         msg->address_lo =
3028                 MSI_ADDR_BASE_LO |
3029                 ((apic->irq_dest_mode == 0) ?
3030                         MSI_ADDR_DEST_MODE_PHYSICAL:
3031                         MSI_ADDR_DEST_MODE_LOGICAL) |
3032                 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3033                         MSI_ADDR_REDIRECTION_CPU:
3034                         MSI_ADDR_REDIRECTION_LOWPRI) |
3035                 MSI_ADDR_DEST_ID(dest);
3036 
3037         msg->data =
3038                 MSI_DATA_TRIGGER_EDGE |
3039                 MSI_DATA_LEVEL_ASSERT |
3040                 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3041                         MSI_DATA_DELIVERY_FIXED:
3042                         MSI_DATA_DELIVERY_LOWPRI) |
3043                 MSI_DATA_VECTOR(cfg->vector);
3044 }
3045 
3046 #ifdef CONFIG_PCI_MSI
3047 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3048                            struct msi_msg *msg, u8 hpet_id)
3049 {
3050         struct irq_cfg *cfg;
3051         int err;
3052         unsigned dest;
3053 
3054         if (disable_apic)
3055                 return -ENXIO;
3056 
3057         cfg = irq_cfg(irq);
3058         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3059         if (err)
3060                 return err;
3061 
3062         err = apic->cpu_mask_to_apicid_and(cfg->domain,
3063                                            apic->target_cpus(), &dest);
3064         if (err)
3065                 return err;
3066 
3067         x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
3068 
3069         return 0;
3070 }
3071 
3072 static int
3073 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3074 {
3075         struct irq_cfg *cfg = data->chip_data;
3076         struct msi_msg msg;
3077         unsigned int dest;
3078 
3079         if (__ioapic_set_affinity(data, mask, &dest))
3080                 return -1;
3081 
3082         __get_cached_msi_msg(data->msi_desc, &msg);
3083 
3084         msg.data &= ~MSI_DATA_VECTOR_MASK;
3085         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3086         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3087         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3088 
3089         __write_msi_msg(data->msi_desc, &msg);
3090 
3091         return IRQ_SET_MASK_OK_NOCOPY;
3092 }
3093 
3094 /*
3095  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3096  * which implement the MSI or MSI-X Capability Structure.
3097  */
3098 static struct irq_chip msi_chip = {
3099         .name                   = "PCI-MSI",
3100         .irq_unmask             = unmask_msi_irq,
3101         .irq_mask               = mask_msi_irq,
3102         .irq_ack                = ack_apic_edge,
3103         .irq_set_affinity       = msi_set_affinity,
3104         .irq_retrigger          = ioapic_retrigger_irq,
3105 };
3106 
3107 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
3108                   unsigned int irq_base, unsigned int irq_offset)
3109 {
3110         struct irq_chip *chip = &msi_chip;
3111         struct msi_msg msg;
3112         unsigned int irq = irq_base + irq_offset;
3113         int ret;
3114 
3115         ret = msi_compose_msg(dev, irq, &msg, -1);
3116         if (ret < 0)
3117                 return ret;
3118 
3119         irq_set_msi_desc_off(irq_base, irq_offset, msidesc);
3120 
3121         /*
3122          * MSI-X message is written per-IRQ, the offset is always 0.
3123          * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
3124          */
3125         if (!irq_offset)
3126                 write_msi_msg(irq, &msg);
3127 
3128         setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
3129 
3130         irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3131 
3132         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3133 
3134         return 0;
3135 }
3136 
3137 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3138 {
3139         unsigned int irq, irq_want;
3140         struct msi_desc *msidesc;
3141         int node, ret;
3142 
3143         /* Multiple MSI vectors only supported with interrupt remapping */
3144         if (type == PCI_CAP_ID_MSI && nvec > 1)
3145                 return 1;
3146 
3147         node = dev_to_node(&dev->dev);
3148         irq_want = nr_irqs_gsi;
3149         list_for_each_entry(msidesc, &dev->msi_list, list) {
3150                 irq = create_irq_nr(irq_want, node);
3151                 if (irq == 0)
3152                         return -ENOSPC;
3153 
3154                 irq_want = irq + 1;
3155 
3156                 ret = setup_msi_irq(dev, msidesc, irq, 0);
3157                 if (ret < 0)
3158                         goto error;
3159         }
3160         return 0;
3161 
3162 error:
3163         destroy_irq(irq);
3164         return ret;
3165 }
3166 
3167 void native_teardown_msi_irq(unsigned int irq)
3168 {
3169         destroy_irq(irq);
3170 }
3171 
3172 #ifdef CONFIG_DMAR_TABLE
3173 static int
3174 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3175                       bool force)
3176 {
3177         struct irq_cfg *cfg = data->chip_data;
3178         unsigned int dest, irq = data->irq;
3179         struct msi_msg msg;
3180 
3181         if (__ioapic_set_affinity(data, mask, &dest))
3182                 return -1;
3183 
3184         dmar_msi_read(irq, &msg);
3185 
3186         msg.data &= ~MSI_DATA_VECTOR_MASK;
3187         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3188         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3189         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3190         msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3191 
3192         dmar_msi_write(irq, &msg);
3193 
3194         return IRQ_SET_MASK_OK_NOCOPY;
3195 }
3196 
3197 static struct irq_chip dmar_msi_type = {
3198         .name                   = "DMAR_MSI",
3199         .irq_unmask             = dmar_msi_unmask,
3200         .irq_mask               = dmar_msi_mask,
3201         .irq_ack                = ack_apic_edge,
3202         .irq_set_affinity       = dmar_msi_set_affinity,
3203         .irq_retrigger          = ioapic_retrigger_irq,
3204 };
3205 
3206 int arch_setup_dmar_msi(unsigned int irq)
3207 {
3208         int ret;
3209         struct msi_msg msg;
3210 
3211         ret = msi_compose_msg(NULL, irq, &msg, -1);
3212         if (ret < 0)
3213                 return ret;
3214         dmar_msi_write(irq, &msg);
3215         irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3216                                       "edge");
3217         return 0;
3218 }
3219 #endif
3220 
3221 #ifdef CONFIG_HPET_TIMER
3222 
3223 static int hpet_msi_set_affinity(struct irq_data *data,
3224                                  const struct cpumask *mask, bool force)
3225 {
3226         struct irq_cfg *cfg = data->chip_data;
3227         struct msi_msg msg;
3228         unsigned int dest;
3229 
3230         if (__ioapic_set_affinity(data, mask, &dest))
3231                 return -1;
3232 
3233         hpet_msi_read(data->handler_data, &msg);
3234 
3235         msg.data &= ~MSI_DATA_VECTOR_MASK;
3236         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3237         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3238         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3239 
3240         hpet_msi_write(data->handler_data, &msg);
3241 
3242         return IRQ_SET_MASK_OK_NOCOPY;
3243 }
3244 
3245 static struct irq_chip hpet_msi_type = {
3246         .name = "HPET_MSI",
3247         .irq_unmask = hpet_msi_unmask,
3248         .irq_mask = hpet_msi_mask,
3249         .irq_ack = ack_apic_edge,
3250         .irq_set_affinity = hpet_msi_set_affinity,
3251         .irq_retrigger = ioapic_retrigger_irq,
3252 };
3253 
3254 int default_setup_hpet_msi(unsigned int irq, unsigned int id)
3255 {
3256         struct irq_chip *chip = &hpet_msi_type;
3257         struct msi_msg msg;
3258         int ret;
3259 
3260         ret = msi_compose_msg(NULL, irq, &msg, id);
3261         if (ret < 0)
3262                 return ret;
3263 
3264         hpet_msi_write(irq_get_handler_data(irq), &msg);
3265         irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3266         setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
3267 
3268         irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3269         return 0;
3270 }
3271 #endif
3272 
3273 #endif /* CONFIG_PCI_MSI */
3274 /*
3275  * Hypertransport interrupt support
3276  */
3277 #ifdef CONFIG_HT_IRQ
3278 
3279 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3280 {
3281         struct ht_irq_msg msg;
3282         fetch_ht_irq_msg(irq, &msg);
3283 
3284         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3285         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3286 
3287         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3288         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3289 
3290         write_ht_irq_msg(irq, &msg);
3291 }
3292 
3293 static int
3294 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3295 {
3296         struct irq_cfg *cfg = data->chip_data;
3297         unsigned int dest;
3298 
3299         if (__ioapic_set_affinity(data, mask, &dest))
3300                 return -1;
3301 
3302         target_ht_irq(data->irq, dest, cfg->vector);
3303         return IRQ_SET_MASK_OK_NOCOPY;
3304 }
3305 
3306 static struct irq_chip ht_irq_chip = {
3307         .name                   = "PCI-HT",
3308         .irq_mask               = mask_ht_irq,
3309         .irq_unmask             = unmask_ht_irq,
3310         .irq_ack                = ack_apic_edge,
3311         .irq_set_affinity       = ht_set_affinity,
3312         .irq_retrigger          = ioapic_retrigger_irq,
3313 };
3314 
3315 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3316 {
3317         struct irq_cfg *cfg;
3318         struct ht_irq_msg msg;
3319         unsigned dest;
3320         int err;
3321 
3322         if (disable_apic)
3323                 return -ENXIO;
3324 
3325         cfg = irq_cfg(irq);
3326         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3327         if (err)
3328                 return err;
3329 
3330         err = apic->cpu_mask_to_apicid_and(cfg->domain,
3331                                            apic->target_cpus(), &dest);
3332         if (err)
3333                 return err;
3334 
3335         msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3336 
3337         msg.address_lo =
3338                 HT_IRQ_LOW_BASE |
3339                 HT_IRQ_LOW_DEST_ID(dest) |
3340                 HT_IRQ_LOW_VECTOR(cfg->vector) |
3341                 ((apic->irq_dest_mode == 0) ?
3342                         HT_IRQ_LOW_DM_PHYSICAL :
3343                         HT_IRQ_LOW_DM_LOGICAL) |
3344                 HT_IRQ_LOW_RQEOI_EDGE |
3345                 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3346                         HT_IRQ_LOW_MT_FIXED :
3347                         HT_IRQ_LOW_MT_ARBITRATED) |
3348                 HT_IRQ_LOW_IRQ_MASKED;
3349 
3350         write_ht_irq_msg(irq, &msg);
3351 
3352         irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3353                                       handle_edge_irq, "edge");
3354 
3355         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3356 
3357         return 0;
3358 }
3359 #endif /* CONFIG_HT_IRQ */
3360 
3361 static int
3362 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3363 {
3364         struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3365         int ret;
3366 
3367         if (!cfg)
3368                 return -EINVAL;
3369         ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3370         if (!ret)
3371                 setup_ioapic_irq(irq, cfg, attr);
3372         return ret;
3373 }
3374 
3375 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3376                                struct io_apic_irq_attr *attr)
3377 {
3378         unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3379         int ret;
3380         struct IO_APIC_route_entry orig_entry;
3381 
3382         /* Avoid redundant programming */
3383         if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3384                 pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx), pin);
3385                 orig_entry = ioapic_read_entry(attr->ioapic, pin);
3386                 if (attr->trigger == orig_entry.trigger && attr->polarity == orig_entry.polarity)
3387                         return 0;
3388                 return -EBUSY;
3389         }
3390         ret = io_apic_setup_irq_pin(irq, node, attr);
3391         if (!ret)
3392                 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3393         return ret;
3394 }
3395 
3396 static int __init io_apic_get_redir_entries(int ioapic)
3397 {
3398         union IO_APIC_reg_01    reg_01;
3399         unsigned long flags;
3400 
3401         raw_spin_lock_irqsave(&ioapic_lock, flags);
3402         reg_01.raw = io_apic_read(ioapic, 1);
3403         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3404 
3405         /* The register returns the maximum index redir index
3406          * supported, which is one less than the total number of redir
3407          * entries.
3408          */
3409         return reg_01.bits.entries + 1;
3410 }
3411 
3412 static void __init probe_nr_irqs_gsi(void)
3413 {
3414         int nr;
3415 
3416         nr = gsi_top + NR_IRQS_LEGACY;
3417         if (nr > nr_irqs_gsi)
3418                 nr_irqs_gsi = nr;
3419 
3420         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3421 }
3422 
3423 int get_nr_irqs_gsi(void)
3424 {
3425         return nr_irqs_gsi;
3426 }
3427 
3428 int __init arch_probe_nr_irqs(void)
3429 {
3430         int nr;
3431 
3432         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3433                 nr_irqs = NR_VECTORS * nr_cpu_ids;
3434 
3435         nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3436 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3437         /*
3438          * for MSI and HT dyn irq
3439          */
3440         nr += nr_irqs_gsi * 16;
3441 #endif
3442         if (nr < nr_irqs)
3443                 nr_irqs = nr;
3444 
3445         return NR_IRQS_LEGACY;
3446 }
3447 
3448 int io_apic_set_pci_routing(struct device *dev, int irq,
3449                             struct io_apic_irq_attr *irq_attr)
3450 {
3451         int node;
3452 
3453         if (!IO_APIC_IRQ(irq)) {
3454                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3455                             irq_attr->ioapic);
3456                 return -EINVAL;
3457         }
3458 
3459         node = dev ? dev_to_node(dev) : cpu_to_node(0);
3460 
3461         return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3462 }
3463 
3464 #ifdef CONFIG_X86_32
3465 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3466 {
3467         union IO_APIC_reg_00 reg_00;
3468         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3469         physid_mask_t tmp;
3470         unsigned long flags;
3471         int i = 0;
3472 
3473         /*
3474          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3475          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3476          * supports up to 16 on one shared APIC bus.
3477          *
3478          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3479          *      advantage of new APIC bus architecture.
3480          */
3481 
3482         if (physids_empty(apic_id_map))
3483                 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3484 
3485         raw_spin_lock_irqsave(&ioapic_lock, flags);
3486         reg_00.raw = io_apic_read(ioapic, 0);
3487         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3488 
3489         if (apic_id >= get_physical_broadcast()) {
3490                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3491                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3492                 apic_id = reg_00.bits.ID;
3493         }
3494 
3495         /*
3496          * Every APIC in a system must have a unique ID or we get lots of nice
3497          * 'stuck on smp_invalidate_needed IPI wait' messages.
3498          */
3499         if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3500 
3501                 for (i = 0; i < get_physical_broadcast(); i++) {
3502                         if (!apic->check_apicid_used(&apic_id_map, i))
3503                                 break;
3504                 }
3505 
3506                 if (i == get_physical_broadcast())
3507                         panic("Max apic_id exceeded!\n");
3508 
3509                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3510                         "trying %d\n", ioapic, apic_id, i);
3511 
3512                 apic_id = i;
3513         }
3514 
3515         apic->apicid_to_cpu_present(apic_id, &tmp);
3516         physids_or(apic_id_map, apic_id_map, tmp);
3517 
3518         if (reg_00.bits.ID != apic_id) {
3519                 reg_00.bits.ID = apic_id;
3520 
3521                 raw_spin_lock_irqsave(&ioapic_lock, flags);
3522                 io_apic_write(ioapic, 0, reg_00.raw);
3523                 reg_00.raw = io_apic_read(ioapic, 0);
3524                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3525 
3526                 /* Sanity check */
3527                 if (reg_00.bits.ID != apic_id) {
3528                         pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
3529                                ioapic);
3530                         return -1;
3531                 }
3532         }
3533 
3534         apic_printk(APIC_VERBOSE, KERN_INFO
3535                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3536 
3537         return apic_id;
3538 }
3539 
3540 static u8 __init io_apic_unique_id(u8 id)
3541 {
3542         if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3543             !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3544                 return io_apic_get_unique_id(nr_ioapics, id);
3545         else
3546                 return id;
3547 }
3548 #else
3549 static u8 __init io_apic_unique_id(u8 id)
3550 {
3551         int i;
3552         DECLARE_BITMAP(used, 256);
3553 
3554         bitmap_zero(used, 256);
3555         for (i = 0; i < nr_ioapics; i++) {
3556                 __set_bit(mpc_ioapic_id(i), used);
3557         }
3558         if (!test_bit(id, used))
3559                 return id;
3560         return find_first_zero_bit(used, 256);
3561 }
3562 #endif
3563 
3564 static int __init io_apic_get_version(int ioapic)
3565 {
3566         union IO_APIC_reg_01    reg_01;
3567         unsigned long flags;
3568 
3569         raw_spin_lock_irqsave(&ioapic_lock, flags);
3570         reg_01.raw = io_apic_read(ioapic, 1);
3571         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3572 
3573         return reg_01.bits.version;
3574 }
3575 
3576 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3577 {
3578         int ioapic, pin, idx;
3579 
3580         if (skip_ioapic_setup)
3581                 return -1;
3582 
3583         ioapic = mp_find_ioapic(gsi);
3584         if (ioapic < 0)
3585                 return -1;
3586 
3587         pin = mp_find_ioapic_pin(ioapic, gsi);
3588         if (pin < 0)
3589                 return -1;
3590 
3591         idx = find_irq_entry(ioapic, pin, mp_INT);
3592         if (idx < 0)
3593                 return -1;
3594 
3595         *trigger = irq_trigger(idx);
3596         *polarity = irq_polarity(idx);
3597         return 0;
3598 }
3599 
3600 /*
3601  * This function currently is only a helper for the i386 smp boot process where
3602  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3603  * so mask in all cases should simply be apic->target_cpus()
3604  */
3605 #ifdef CONFIG_SMP
3606 void __init setup_ioapic_dest(void)
3607 {
3608         int pin, ioapic, irq, irq_entry;
3609         const struct cpumask *mask;
3610         struct irq_data *idata;
3611 
3612         if (skip_ioapic_setup == 1)
3613                 return;
3614 
3615         for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3616         for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3617                 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3618                 if (irq_entry == -1)
3619                         continue;
3620                 irq = pin_2_irq(irq_entry, ioapic, pin);
3621 
3622                 if ((ioapic > 0) && (irq > 16))
3623                         continue;
3624 
3625                 idata = irq_get_irq_data(irq);
3626 
3627                 /*
3628                  * Honour affinities which have been set in early boot
3629                  */
3630                 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3631                         mask = idata->affinity;
3632                 else
3633                         mask = apic->target_cpus();
3634 
3635                 x86_io_apic_ops.set_affinity(idata, mask, false);
3636         }
3637 
3638 }
3639 #endif
3640 
3641 #define IOAPIC_RESOURCE_NAME_SIZE 11
3642 
3643 static struct resource *ioapic_resources;
3644 
3645 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3646 {
3647         unsigned long n;
3648         struct resource *res;
3649         char *mem;
3650         int i;
3651 
3652         if (nr_ioapics <= 0)
3653                 return NULL;
3654 
3655         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3656         n *= nr_ioapics;
3657 
3658         mem = alloc_bootmem(n);
3659         res = (void *)mem;
3660 
3661         mem += sizeof(struct resource) * nr_ioapics;
3662 
3663         for (i = 0; i < nr_ioapics; i++) {
3664                 res[i].name = mem;
3665                 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3666                 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3667                 mem += IOAPIC_RESOURCE_NAME_SIZE;
3668         }
3669 
3670         ioapic_resources = res;
3671 
3672         return res;
3673 }
3674 
3675 void __init native_io_apic_init_mappings(void)
3676 {
3677         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3678         struct resource *ioapic_res;
3679         int i;
3680 
3681         ioapic_res = ioapic_setup_resources(nr_ioapics);
3682         for (i = 0; i < nr_ioapics; i++) {
3683                 if (smp_found_config) {
3684                         ioapic_phys = mpc_ioapic_addr(i);
3685 #ifdef CONFIG_X86_32
3686                         if (!ioapic_phys) {
3687                                 printk(KERN_ERR
3688                                        "WARNING: bogus zero IO-APIC "
3689                                        "address found in MPTABLE, "
3690                                        "disabling IO/APIC support!\n");
3691                                 smp_found_config = 0;
3692                                 skip_ioapic_setup = 1;
3693                                 goto fake_ioapic_page;
3694                         }
3695 #endif
3696                 } else {
3697 #ifdef CONFIG_X86_32
3698 fake_ioapic_page:
3699 #endif
3700                         ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3701                         ioapic_phys = __pa(ioapic_phys);
3702                 }
3703                 set_fixmap_nocache(idx, ioapic_phys);
3704                 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3705                         __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3706                         ioapic_phys);
3707                 idx++;
3708 
3709                 ioapic_res->start = ioapic_phys;
3710                 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3711                 ioapic_res++;
3712         }
3713 
3714         probe_nr_irqs_gsi();
3715 }
3716 
3717 void __init ioapic_insert_resources(void)
3718 {
3719         int i;
3720         struct resource *r = ioapic_resources;
3721 
3722         if (!r) {
3723                 if (nr_ioapics > 0)
3724                         printk(KERN_ERR
3725                                 "IO APIC resources couldn't be allocated.\n");
3726                 return;
3727         }
3728 
3729         for (i = 0; i < nr_ioapics; i++) {
3730                 insert_resource(&iomem_resource, r);
3731                 r++;
3732         }
3733 }
3734 
3735 int mp_find_ioapic(u32 gsi)
3736 {
3737         int i = 0;
3738 
3739         if (nr_ioapics == 0)
3740                 return -1;
3741 
3742         /* Find the IOAPIC that manages this GSI. */
3743         for (i = 0; i < nr_ioapics; i++) {
3744                 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3745                 if ((gsi >= gsi_cfg->gsi_base)
3746                     && (gsi <= gsi_cfg->gsi_end))
3747                         return i;
3748         }
3749 
3750         printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3751         return -1;
3752 }
3753 
3754 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3755 {
3756         struct mp_ioapic_gsi *gsi_cfg;
3757 
3758         if (WARN_ON(ioapic == -1))
3759                 return -1;
3760 
3761         gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3762         if (WARN_ON(gsi > gsi_cfg->gsi_end))
3763                 return -1;
3764 
3765         return gsi - gsi_cfg->gsi_base;
3766 }
3767 
3768 static __init int bad_ioapic(unsigned long address)
3769 {
3770         if (nr_ioapics >= MAX_IO_APICS) {
3771                 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3772                         MAX_IO_APICS, nr_ioapics);
3773                 return 1;
3774         }
3775         if (!address) {
3776                 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3777                 return 1;
3778         }
3779         return 0;
3780 }
3781 
3782 static __init int bad_ioapic_register(int idx)
3783 {
3784         union IO_APIC_reg_00 reg_00;
3785         union IO_APIC_reg_01 reg_01;
3786         union IO_APIC_reg_02 reg_02;
3787 
3788         reg_00.raw = io_apic_read(idx, 0);
3789         reg_01.raw = io_apic_read(idx, 1);
3790         reg_02.raw = io_apic_read(idx, 2);
3791 
3792         if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3793                 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3794                         mpc_ioapic_addr(idx));
3795                 return 1;
3796         }
3797 
3798         return 0;
3799 }
3800 
3801 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3802 {
3803         int idx = 0;
3804         int entries;
3805         struct mp_ioapic_gsi *gsi_cfg;
3806 
3807         if (bad_ioapic(address))
3808                 return;
3809 
3810         idx = nr_ioapics;
3811 
3812         ioapics[idx].mp_config.type = MP_IOAPIC;
3813         ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3814         ioapics[idx].mp_config.apicaddr = address;
3815 
3816         set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3817 
3818         if (bad_ioapic_register(idx)) {
3819                 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3820                 return;
3821         }
3822 
3823         ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3824         ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3825 
3826         /*
3827          * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3828          * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3829          */
3830         entries = io_apic_get_redir_entries(idx);
3831         gsi_cfg = mp_ioapic_gsi_routing(idx);
3832         gsi_cfg->gsi_base = gsi_base;
3833         gsi_cfg->gsi_end = gsi_base + entries - 1;
3834 
3835         /*
3836          * The number of IO-APIC IRQ registers (== #pins):
3837          */
3838         ioapics[idx].nr_registers = entries;
3839 
3840         if (gsi_cfg->gsi_end >= gsi_top)
3841                 gsi_top = gsi_cfg->gsi_end + 1;
3842 
3843         pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3844                 idx, mpc_ioapic_id(idx),
3845                 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3846                 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3847 
3848         nr_ioapics++;
3849 }
3850 
3851 /* Enable IOAPIC early just for system timer */
3852 void __init pre_init_apic_IRQ0(void)
3853 {
3854         struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3855 
3856         printk(KERN_INFO "Early APIC setup for system timer0\n");
3857 #ifndef CONFIG_SMP
3858         physid_set_mask_of_physid(boot_cpu_physical_apicid,
3859                                          &phys_cpu_present_map);
3860 #endif
3861         setup_local_APIC();
3862 
3863         io_apic_setup_irq_pin(0, 0, &attr);
3864         irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
3865                                       "edge");
3866 }
3867 

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