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Linux/arch/x86/kernel/cpu/mcheck/mce_amd.c

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  1 /*
  2  *  (c) 2005-2016 Advanced Micro Devices, Inc.
  3  *  Your use of this code is subject to the terms and conditions of the
  4  *  GNU general public license version 2. See "COPYING" or
  5  *  http://www.gnu.org/licenses/gpl.html
  6  *
  7  *  Written by Jacob Shin - AMD, Inc.
  8  *  Maintained by: Borislav Petkov <bp@alien8.de>
  9  *
 10  *  All MC4_MISCi registers are shared between cores on a node.
 11  */
 12 #include <linux/interrupt.h>
 13 #include <linux/notifier.h>
 14 #include <linux/kobject.h>
 15 #include <linux/percpu.h>
 16 #include <linux/errno.h>
 17 #include <linux/sched.h>
 18 #include <linux/sysfs.h>
 19 #include <linux/slab.h>
 20 #include <linux/init.h>
 21 #include <linux/cpu.h>
 22 #include <linux/smp.h>
 23 #include <linux/string.h>
 24 
 25 #include <asm/amd_nb.h>
 26 #include <asm/apic.h>
 27 #include <asm/mce.h>
 28 #include <asm/msr.h>
 29 #include <asm/trace/irq_vectors.h>
 30 
 31 #include "mce-internal.h"
 32 
 33 #define NR_BLOCKS         5
 34 #define THRESHOLD_MAX     0xFFF
 35 #define INT_TYPE_APIC     0x00020000
 36 #define MASK_VALID_HI     0x80000000
 37 #define MASK_CNTP_HI      0x40000000
 38 #define MASK_LOCKED_HI    0x20000000
 39 #define MASK_LVTOFF_HI    0x00F00000
 40 #define MASK_COUNT_EN_HI  0x00080000
 41 #define MASK_INT_TYPE_HI  0x00060000
 42 #define MASK_OVERFLOW_HI  0x00010000
 43 #define MASK_ERR_COUNT_HI 0x00000FFF
 44 #define MASK_BLKPTR_LO    0xFF000000
 45 #define MCG_XBLK_ADDR     0xC0000400
 46 
 47 /* Deferred error settings */
 48 #define MSR_CU_DEF_ERR          0xC0000410
 49 #define MASK_DEF_LVTOFF         0x000000F0
 50 #define MASK_DEF_INT_TYPE       0x00000006
 51 #define DEF_LVT_OFF             0x2
 52 #define DEF_INT_TYPE_APIC       0x2
 53 
 54 /* Scalable MCA: */
 55 
 56 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
 57 #define SMCA_THR_LVT_OFF        0xF000
 58 
 59 static bool thresholding_en;
 60 
 61 static const char * const th_names[] = {
 62         "load_store",
 63         "insn_fetch",
 64         "combined_unit",
 65         "decode_unit",
 66         "northbridge",
 67         "execution_unit",
 68 };
 69 
 70 static const char * const smca_umc_block_names[] = {
 71         "dram_ecc",
 72         "misc_umc"
 73 };
 74 
 75 struct smca_bank_name {
 76         const char *name;       /* Short name for sysfs */
 77         const char *long_name;  /* Long name for pretty-printing */
 78 };
 79 
 80 static struct smca_bank_name smca_names[] = {
 81         [SMCA_LS]       = { "load_store",       "Load Store Unit" },
 82         [SMCA_IF]       = { "insn_fetch",       "Instruction Fetch Unit" },
 83         [SMCA_L2_CACHE] = { "l2_cache",         "L2 Cache" },
 84         [SMCA_DE]       = { "decode_unit",      "Decode Unit" },
 85         [SMCA_EX]       = { "execution_unit",   "Execution Unit" },
 86         [SMCA_FP]       = { "floating_point",   "Floating Point Unit" },
 87         [SMCA_L3_CACHE] = { "l3_cache",         "L3 Cache" },
 88         [SMCA_CS]       = { "coherent_slave",   "Coherent Slave" },
 89         [SMCA_PIE]      = { "pie",              "Power, Interrupts, etc." },
 90         [SMCA_UMC]      = { "umc",              "Unified Memory Controller" },
 91         [SMCA_PB]       = { "param_block",      "Parameter Block" },
 92         [SMCA_PSP]      = { "psp",              "Platform Security Processor" },
 93         [SMCA_SMU]      = { "smu",              "System Management Unit" },
 94 };
 95 
 96 const char *smca_get_name(enum smca_bank_types t)
 97 {
 98         if (t >= N_SMCA_BANK_TYPES)
 99                 return NULL;
100 
101         return smca_names[t].name;
102 }
103 
104 const char *smca_get_long_name(enum smca_bank_types t)
105 {
106         if (t >= N_SMCA_BANK_TYPES)
107                 return NULL;
108 
109         return smca_names[t].long_name;
110 }
111 EXPORT_SYMBOL_GPL(smca_get_long_name);
112 
113 static struct smca_hwid smca_hwid_mcatypes[] = {
114         /* { bank_type, hwid_mcatype, xec_bitmap } */
115 
116         /* ZN Core (HWID=0xB0) MCA types */
117         { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
118         { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
119         { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
120         { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3), 0x1FF },
121         /* HWID 0xB0 MCATYPE 0x4 is Reserved */
122         { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0x7FF },
123         { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6), 0x7F },
124         { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
125 
126         /* Data Fabric MCA types */
127         { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0), 0x1FF },
128         { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0xF },
129 
130         /* Unified Memory Controller MCA type */
131         { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0x3F },
132 
133         /* Parameter Block MCA type */
134         { SMCA_PB,       HWID_MCATYPE(0x05, 0x0), 0x1 },
135 
136         /* Platform Security Processor MCA type */
137         { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0), 0x1 },
138 
139         /* System Management Unit MCA type */
140         { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0), 0x1 },
141 };
142 
143 struct smca_bank smca_banks[MAX_NR_BANKS];
144 EXPORT_SYMBOL_GPL(smca_banks);
145 
146 /*
147  * In SMCA enabled processors, we can have multiple banks for a given IP type.
148  * So to define a unique name for each bank, we use a temp c-string to append
149  * the MCA_IPID[InstanceId] to type's name in get_name().
150  *
151  * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
152  * is greater than 8 plus 1 (for underscore) plus length of longest type name.
153  */
154 #define MAX_MCATYPE_NAME_LEN    30
155 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
156 
157 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
158 static DEFINE_PER_CPU(unsigned int, bank_map);  /* see which banks are on */
159 
160 static void amd_threshold_interrupt(void);
161 static void amd_deferred_error_interrupt(void);
162 
163 static void default_deferred_error_interrupt(void)
164 {
165         pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
166 }
167 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
168 
169 static void smca_configure(unsigned int bank, unsigned int cpu)
170 {
171         unsigned int i, hwid_mcatype;
172         struct smca_hwid *s_hwid;
173         u32 high, low;
174         u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
175 
176         /* Set appropriate bits in MCA_CONFIG */
177         if (!rdmsr_safe(smca_config, &low, &high)) {
178                 /*
179                  * OS is required to set the MCAX bit to acknowledge that it is
180                  * now using the new MSR ranges and new registers under each
181                  * bank. It also means that the OS will configure deferred
182                  * errors in the new MCx_CONFIG register. If the bit is not set,
183                  * uncorrectable errors will cause a system panic.
184                  *
185                  * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
186                  */
187                 high |= BIT(0);
188 
189                 /*
190                  * SMCA sets the Deferred Error Interrupt type per bank.
191                  *
192                  * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
193                  * if the DeferredIntType bit field is available.
194                  *
195                  * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
196                  * high portion of the MSR). OS should set this to 0x1 to enable
197                  * APIC based interrupt. First, check that no interrupt has been
198                  * set.
199                  */
200                 if ((low & BIT(5)) && !((high >> 5) & 0x3))
201                         high |= BIT(5);
202 
203                 wrmsr(smca_config, low, high);
204         }
205 
206         /* Return early if this bank was already initialized. */
207         if (smca_banks[bank].hwid)
208                 return;
209 
210         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
211                 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
212                 return;
213         }
214 
215         hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
216                                     (high & MCI_IPID_MCATYPE) >> 16);
217 
218         for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
219                 s_hwid = &smca_hwid_mcatypes[i];
220                 if (hwid_mcatype == s_hwid->hwid_mcatype) {
221                         smca_banks[bank].hwid = s_hwid;
222                         smca_banks[bank].id = low;
223                         smca_banks[bank].sysfs_id = s_hwid->count++;
224                         break;
225                 }
226         }
227 }
228 
229 struct thresh_restart {
230         struct threshold_block  *b;
231         int                     reset;
232         int                     set_lvt_off;
233         int                     lvt_off;
234         u16                     old_limit;
235 };
236 
237 static inline bool is_shared_bank(int bank)
238 {
239         /*
240          * Scalable MCA provides for only one core to have access to the MSRs of
241          * a shared bank.
242          */
243         if (mce_flags.smca)
244                 return false;
245 
246         /* Bank 4 is for northbridge reporting and is thus shared */
247         return (bank == 4);
248 }
249 
250 static const char *bank4_names(const struct threshold_block *b)
251 {
252         switch (b->address) {
253         /* MSR4_MISC0 */
254         case 0x00000413:
255                 return "dram";
256 
257         case 0xc0000408:
258                 return "ht_links";
259 
260         case 0xc0000409:
261                 return "l3_cache";
262 
263         default:
264                 WARN(1, "Funny MSR: 0x%08x\n", b->address);
265                 return "";
266         }
267 };
268 
269 
270 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
271 {
272         /*
273          * bank 4 supports APIC LVT interrupts implicitly since forever.
274          */
275         if (bank == 4)
276                 return true;
277 
278         /*
279          * IntP: interrupt present; if this bit is set, the thresholding
280          * bank can generate APIC LVT interrupts
281          */
282         return msr_high_bits & BIT(28);
283 }
284 
285 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
286 {
287         int msr = (hi & MASK_LVTOFF_HI) >> 20;
288 
289         if (apic < 0) {
290                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
291                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
292                        b->bank, b->block, b->address, hi, lo);
293                 return 0;
294         }
295 
296         if (apic != msr) {
297                 /*
298                  * On SMCA CPUs, LVT offset is programmed at a different MSR, and
299                  * the BIOS provides the value. The original field where LVT offset
300                  * was set is reserved. Return early here:
301                  */
302                 if (mce_flags.smca)
303                         return 0;
304 
305                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
306                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
307                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
308                 return 0;
309         }
310 
311         return 1;
312 };
313 
314 /* Reprogram MCx_MISC MSR behind this threshold bank. */
315 static void threshold_restart_bank(void *_tr)
316 {
317         struct thresh_restart *tr = _tr;
318         u32 hi, lo;
319 
320         rdmsr(tr->b->address, lo, hi);
321 
322         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
323                 tr->reset = 1;  /* limit cannot be lower than err count */
324 
325         if (tr->reset) {                /* reset err count and overflow bit */
326                 hi =
327                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
328                     (THRESHOLD_MAX - tr->b->threshold_limit);
329         } else if (tr->old_limit) {     /* change limit w/o reset */
330                 int new_count = (hi & THRESHOLD_MAX) +
331                     (tr->old_limit - tr->b->threshold_limit);
332 
333                 hi = (hi & ~MASK_ERR_COUNT_HI) |
334                     (new_count & THRESHOLD_MAX);
335         }
336 
337         /* clear IntType */
338         hi &= ~MASK_INT_TYPE_HI;
339 
340         if (!tr->b->interrupt_capable)
341                 goto done;
342 
343         if (tr->set_lvt_off) {
344                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
345                         /* set new lvt offset */
346                         hi &= ~MASK_LVTOFF_HI;
347                         hi |= tr->lvt_off << 20;
348                 }
349         }
350 
351         if (tr->b->interrupt_enable)
352                 hi |= INT_TYPE_APIC;
353 
354  done:
355 
356         hi |= MASK_COUNT_EN_HI;
357         wrmsr(tr->b->address, lo, hi);
358 }
359 
360 static void mce_threshold_block_init(struct threshold_block *b, int offset)
361 {
362         struct thresh_restart tr = {
363                 .b                      = b,
364                 .set_lvt_off            = 1,
365                 .lvt_off                = offset,
366         };
367 
368         b->threshold_limit              = THRESHOLD_MAX;
369         threshold_restart_bank(&tr);
370 };
371 
372 static int setup_APIC_mce_threshold(int reserved, int new)
373 {
374         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
375                                               APIC_EILVT_MSG_FIX, 0))
376                 return new;
377 
378         return reserved;
379 }
380 
381 static int setup_APIC_deferred_error(int reserved, int new)
382 {
383         if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
384                                               APIC_EILVT_MSG_FIX, 0))
385                 return new;
386 
387         return reserved;
388 }
389 
390 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
391 {
392         u32 low = 0, high = 0;
393         int def_offset = -1, def_new;
394 
395         if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
396                 return;
397 
398         def_new = (low & MASK_DEF_LVTOFF) >> 4;
399         if (!(low & MASK_DEF_LVTOFF)) {
400                 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
401                 def_new = DEF_LVT_OFF;
402                 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
403         }
404 
405         def_offset = setup_APIC_deferred_error(def_offset, def_new);
406         if ((def_offset == def_new) &&
407             (deferred_error_int_vector != amd_deferred_error_interrupt))
408                 deferred_error_int_vector = amd_deferred_error_interrupt;
409 
410         low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
411         wrmsr(MSR_CU_DEF_ERR, low, high);
412 }
413 
414 static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
415                              unsigned int bank, unsigned int block)
416 {
417         u32 addr = 0, offset = 0;
418 
419         if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
420                 return addr;
421 
422         /* Get address from already initialized block. */
423         if (per_cpu(threshold_banks, cpu)) {
424                 struct threshold_bank *bankp = per_cpu(threshold_banks, cpu)[bank];
425 
426                 if (bankp && bankp->blocks) {
427                         struct threshold_block *blockp = &bankp->blocks[block];
428 
429                         if (blockp)
430                                 return blockp->address;
431                 }
432         }
433 
434         if (mce_flags.smca) {
435                 if (!block) {
436                         addr = MSR_AMD64_SMCA_MCx_MISC(bank);
437                 } else {
438                         /*
439                          * For SMCA enabled processors, BLKPTR field of the
440                          * first MISC register (MCx_MISC0) indicates presence of
441                          * additional MISC register set (MISC1-4).
442                          */
443                         u32 low, high;
444 
445                         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
446                                 return addr;
447 
448                         if (!(low & MCI_CONFIG_MCAX))
449                                 return addr;
450 
451                         if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
452                             (low & MASK_BLKPTR_LO))
453                                 addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
454                 }
455                 return addr;
456         }
457 
458         /* Fall back to method we used for older processors: */
459         switch (block) {
460         case 0:
461                 addr = msr_ops.misc(bank);
462                 break;
463         case 1:
464                 offset = ((low & MASK_BLKPTR_LO) >> 21);
465                 if (offset)
466                         addr = MCG_XBLK_ADDR + offset;
467                 break;
468         default:
469                 addr = ++current_addr;
470         }
471         return addr;
472 }
473 
474 static int
475 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
476                         int offset, u32 misc_high)
477 {
478         unsigned int cpu = smp_processor_id();
479         u32 smca_low, smca_high;
480         struct threshold_block b;
481         int new;
482 
483         if (!block)
484                 per_cpu(bank_map, cpu) |= (1 << bank);
485 
486         memset(&b, 0, sizeof(b));
487         b.cpu                   = cpu;
488         b.bank                  = bank;
489         b.block                 = block;
490         b.address               = addr;
491         b.interrupt_capable     = lvt_interrupt_supported(bank, misc_high);
492 
493         if (!b.interrupt_capable)
494                 goto done;
495 
496         b.interrupt_enable = 1;
497 
498         if (!mce_flags.smca) {
499                 new = (misc_high & MASK_LVTOFF_HI) >> 20;
500                 goto set_offset;
501         }
502 
503         /* Gather LVT offset for thresholding: */
504         if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
505                 goto out;
506 
507         new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
508 
509 set_offset:
510         offset = setup_APIC_mce_threshold(offset, new);
511 
512         if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))
513                 mce_threshold_vector = amd_threshold_interrupt;
514 
515 done:
516         mce_threshold_block_init(&b, offset);
517 
518 out:
519         return offset;
520 }
521 
522 /* cpu init entry point, called from mce.c with preempt off */
523 void mce_amd_feature_init(struct cpuinfo_x86 *c)
524 {
525         u32 low = 0, high = 0, address = 0;
526         unsigned int bank, block, cpu = smp_processor_id();
527         int offset = -1;
528 
529         for (bank = 0; bank < mca_cfg.banks; ++bank) {
530                 if (mce_flags.smca)
531                         smca_configure(bank, cpu);
532 
533                 for (block = 0; block < NR_BLOCKS; ++block) {
534                         address = get_block_address(cpu, address, low, high, bank, block);
535                         if (!address)
536                                 break;
537 
538                         if (rdmsr_safe(address, &low, &high))
539                                 break;
540 
541                         if (!(high & MASK_VALID_HI))
542                                 continue;
543 
544                         if (!(high & MASK_CNTP_HI)  ||
545                              (high & MASK_LOCKED_HI))
546                                 continue;
547 
548                         offset = prepare_threshold_block(bank, block, address, offset, high);
549                 }
550         }
551 
552         if (mce_flags.succor)
553                 deferred_error_interrupt_enable(c);
554 }
555 
556 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
557 {
558         u64 dram_base_addr, dram_limit_addr, dram_hole_base;
559         /* We start from the normalized address */
560         u64 ret_addr = norm_addr;
561 
562         u32 tmp;
563 
564         u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
565         u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
566         u8 intlv_addr_sel, intlv_addr_bit;
567         u8 num_intlv_bits, hashed_bit;
568         u8 lgcy_mmio_hole_en, base = 0;
569         u8 cs_mask, cs_id = 0;
570         bool hash_enabled = false;
571 
572         /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
573         if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
574                 goto out_err;
575 
576         /* Remove HiAddrOffset from normalized address, if enabled: */
577         if (tmp & BIT(0)) {
578                 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
579 
580                 if (norm_addr >= hi_addr_offset) {
581                         ret_addr -= hi_addr_offset;
582                         base = 1;
583                 }
584         }
585 
586         /* Read D18F0x110 (DramBaseAddress). */
587         if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
588                 goto out_err;
589 
590         /* Check if address range is valid. */
591         if (!(tmp & BIT(0))) {
592                 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
593                         __func__, tmp);
594                 goto out_err;
595         }
596 
597         lgcy_mmio_hole_en = tmp & BIT(1);
598         intlv_num_chan    = (tmp >> 4) & 0xF;
599         intlv_addr_sel    = (tmp >> 8) & 0x7;
600         dram_base_addr    = (tmp & GENMASK_ULL(31, 12)) << 16;
601 
602         /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
603         if (intlv_addr_sel > 3) {
604                 pr_err("%s: Invalid interleave address select %d.\n",
605                         __func__, intlv_addr_sel);
606                 goto out_err;
607         }
608 
609         /* Read D18F0x114 (DramLimitAddress). */
610         if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
611                 goto out_err;
612 
613         intlv_num_sockets = (tmp >> 8) & 0x1;
614         intlv_num_dies    = (tmp >> 10) & 0x3;
615         dram_limit_addr   = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
616 
617         intlv_addr_bit = intlv_addr_sel + 8;
618 
619         /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
620         switch (intlv_num_chan) {
621         case 0: intlv_num_chan = 0; break;
622         case 1: intlv_num_chan = 1; break;
623         case 3: intlv_num_chan = 2; break;
624         case 5: intlv_num_chan = 3; break;
625         case 7: intlv_num_chan = 4; break;
626 
627         case 8: intlv_num_chan = 1;
628                 hash_enabled = true;
629                 break;
630         default:
631                 pr_err("%s: Invalid number of interleaved channels %d.\n",
632                         __func__, intlv_num_chan);
633                 goto out_err;
634         }
635 
636         num_intlv_bits = intlv_num_chan;
637 
638         if (intlv_num_dies > 2) {
639                 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
640                         __func__, intlv_num_dies);
641                 goto out_err;
642         }
643 
644         num_intlv_bits += intlv_num_dies;
645 
646         /* Add a bit if sockets are interleaved. */
647         num_intlv_bits += intlv_num_sockets;
648 
649         /* Assert num_intlv_bits <= 4 */
650         if (num_intlv_bits > 4) {
651                 pr_err("%s: Invalid interleave bits %d.\n",
652                         __func__, num_intlv_bits);
653                 goto out_err;
654         }
655 
656         if (num_intlv_bits > 0) {
657                 u64 temp_addr_x, temp_addr_i, temp_addr_y;
658                 u8 die_id_bit, sock_id_bit, cs_fabric_id;
659 
660                 /*
661                  * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
662                  * This is the fabric id for this coherent slave. Use
663                  * umc/channel# as instance id of the coherent slave
664                  * for FICAA.
665                  */
666                 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
667                         goto out_err;
668 
669                 cs_fabric_id = (tmp >> 8) & 0xFF;
670                 die_id_bit   = 0;
671 
672                 /* If interleaved over more than 1 channel: */
673                 if (intlv_num_chan) {
674                         die_id_bit = intlv_num_chan;
675                         cs_mask    = (1 << die_id_bit) - 1;
676                         cs_id      = cs_fabric_id & cs_mask;
677                 }
678 
679                 sock_id_bit = die_id_bit;
680 
681                 /* Read D18F1x208 (SystemFabricIdMask). */
682                 if (intlv_num_dies || intlv_num_sockets)
683                         if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
684                                 goto out_err;
685 
686                 /* If interleaved over more than 1 die. */
687                 if (intlv_num_dies) {
688                         sock_id_bit  = die_id_bit + intlv_num_dies;
689                         die_id_shift = (tmp >> 24) & 0xF;
690                         die_id_mask  = (tmp >> 8) & 0xFF;
691 
692                         cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
693                 }
694 
695                 /* If interleaved over more than 1 socket. */
696                 if (intlv_num_sockets) {
697                         socket_id_shift = (tmp >> 28) & 0xF;
698                         socket_id_mask  = (tmp >> 16) & 0xFF;
699 
700                         cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
701                 }
702 
703                 /*
704                  * The pre-interleaved address consists of XXXXXXIIIYYYYY
705                  * where III is the ID for this CS, and XXXXXXYYYYY are the
706                  * address bits from the post-interleaved address.
707                  * "num_intlv_bits" has been calculated to tell us how many "I"
708                  * bits there are. "intlv_addr_bit" tells us how many "Y" bits
709                  * there are (where "I" starts).
710                  */
711                 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
712                 temp_addr_i = (cs_id << intlv_addr_bit);
713                 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
714                 ret_addr    = temp_addr_x | temp_addr_i | temp_addr_y;
715         }
716 
717         /* Add dram base address */
718         ret_addr += dram_base_addr;
719 
720         /* If legacy MMIO hole enabled */
721         if (lgcy_mmio_hole_en) {
722                 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
723                         goto out_err;
724 
725                 dram_hole_base = tmp & GENMASK(31, 24);
726                 if (ret_addr >= dram_hole_base)
727                         ret_addr += (BIT_ULL(32) - dram_hole_base);
728         }
729 
730         if (hash_enabled) {
731                 /* Save some parentheses and grab ls-bit at the end. */
732                 hashed_bit =    (ret_addr >> 12) ^
733                                 (ret_addr >> 18) ^
734                                 (ret_addr >> 21) ^
735                                 (ret_addr >> 30) ^
736                                 cs_id;
737 
738                 hashed_bit &= BIT(0);
739 
740                 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
741                         ret_addr ^= BIT(intlv_addr_bit);
742         }
743 
744         /* Is calculated system address is above DRAM limit address? */
745         if (ret_addr > dram_limit_addr)
746                 goto out_err;
747 
748         *sys_addr = ret_addr;
749         return 0;
750 
751 out_err:
752         return -EINVAL;
753 }
754 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
755 
756 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
757 {
758         struct mce m;
759 
760         mce_setup(&m);
761 
762         m.status = status;
763         m.misc   = misc;
764         m.bank   = bank;
765         m.tsc    = rdtsc();
766 
767         if (m.status & MCI_STATUS_ADDRV) {
768                 m.addr = addr;
769 
770                 /*
771                  * Extract [55:<lsb>] where lsb is the least significant
772                  * *valid* bit of the address bits.
773                  */
774                 if (mce_flags.smca) {
775                         u8 lsb = (m.addr >> 56) & 0x3f;
776 
777                         m.addr &= GENMASK_ULL(55, lsb);
778                 }
779         }
780 
781         if (mce_flags.smca) {
782                 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
783 
784                 if (m.status & MCI_STATUS_SYNDV)
785                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
786         }
787 
788         mce_log(&m);
789 }
790 
791 asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(void)
792 {
793         entering_irq();
794         trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
795         inc_irq_stat(irq_deferred_error_count);
796         deferred_error_int_vector();
797         trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
798         exiting_ack_irq();
799 }
800 
801 /*
802  * Returns true if the logged error is deferred. False, otherwise.
803  */
804 static inline bool
805 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
806 {
807         u64 status, addr = 0;
808 
809         rdmsrl(msr_stat, status);
810         if (!(status & MCI_STATUS_VAL))
811                 return false;
812 
813         if (status & MCI_STATUS_ADDRV)
814                 rdmsrl(msr_addr, addr);
815 
816         __log_error(bank, status, addr, misc);
817 
818         wrmsrl(msr_stat, 0);
819 
820         return status & MCI_STATUS_DEFERRED;
821 }
822 
823 /*
824  * We have three scenarios for checking for Deferred errors:
825  *
826  * 1) Non-SMCA systems check MCA_STATUS and log error if found.
827  * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
828  *    clear MCA_DESTAT.
829  * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
830  *    log it.
831  */
832 static void log_error_deferred(unsigned int bank)
833 {
834         bool defrd;
835 
836         defrd = _log_error_bank(bank, msr_ops.status(bank),
837                                         msr_ops.addr(bank), 0);
838 
839         if (!mce_flags.smca)
840                 return;
841 
842         /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
843         if (defrd) {
844                 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
845                 return;
846         }
847 
848         /*
849          * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
850          * for a valid error.
851          */
852         _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
853                               MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
854 }
855 
856 /* APIC interrupt handler for deferred errors */
857 static void amd_deferred_error_interrupt(void)
858 {
859         unsigned int bank;
860 
861         for (bank = 0; bank < mca_cfg.banks; ++bank)
862                 log_error_deferred(bank);
863 }
864 
865 static void log_error_thresholding(unsigned int bank, u64 misc)
866 {
867         _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);
868 }
869 
870 static void log_and_reset_block(struct threshold_block *block)
871 {
872         struct thresh_restart tr;
873         u32 low = 0, high = 0;
874 
875         if (!block)
876                 return;
877 
878         if (rdmsr_safe(block->address, &low, &high))
879                 return;
880 
881         if (!(high & MASK_OVERFLOW_HI))
882                 return;
883 
884         /* Log the MCE which caused the threshold event. */
885         log_error_thresholding(block->bank, ((u64)high << 32) | low);
886 
887         /* Reset threshold block after logging error. */
888         memset(&tr, 0, sizeof(tr));
889         tr.b = block;
890         threshold_restart_bank(&tr);
891 }
892 
893 /*
894  * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
895  * goes off when error_count reaches threshold_limit.
896  */
897 static void amd_threshold_interrupt(void)
898 {
899         struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
900         unsigned int bank, cpu = smp_processor_id();
901 
902         for (bank = 0; bank < mca_cfg.banks; ++bank) {
903                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
904                         continue;
905 
906                 first_block = per_cpu(threshold_banks, cpu)[bank]->blocks;
907                 if (!first_block)
908                         continue;
909 
910                 /*
911                  * The first block is also the head of the list. Check it first
912                  * before iterating over the rest.
913                  */
914                 log_and_reset_block(first_block);
915                 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
916                         log_and_reset_block(block);
917         }
918 }
919 
920 /*
921  * Sysfs Interface
922  */
923 
924 struct threshold_attr {
925         struct attribute attr;
926         ssize_t (*show) (struct threshold_block *, char *);
927         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
928 };
929 
930 #define SHOW_FIELDS(name)                                               \
931 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
932 {                                                                       \
933         return sprintf(buf, "%lu\n", (unsigned long) b->name);          \
934 }
935 SHOW_FIELDS(interrupt_enable)
936 SHOW_FIELDS(threshold_limit)
937 
938 static ssize_t
939 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
940 {
941         struct thresh_restart tr;
942         unsigned long new;
943 
944         if (!b->interrupt_capable)
945                 return -EINVAL;
946 
947         if (kstrtoul(buf, 0, &new) < 0)
948                 return -EINVAL;
949 
950         b->interrupt_enable = !!new;
951 
952         memset(&tr, 0, sizeof(tr));
953         tr.b            = b;
954 
955         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
956 
957         return size;
958 }
959 
960 static ssize_t
961 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
962 {
963         struct thresh_restart tr;
964         unsigned long new;
965 
966         if (kstrtoul(buf, 0, &new) < 0)
967                 return -EINVAL;
968 
969         if (new > THRESHOLD_MAX)
970                 new = THRESHOLD_MAX;
971         if (new < 1)
972                 new = 1;
973 
974         memset(&tr, 0, sizeof(tr));
975         tr.old_limit = b->threshold_limit;
976         b->threshold_limit = new;
977         tr.b = b;
978 
979         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
980 
981         return size;
982 }
983 
984 static ssize_t show_error_count(struct threshold_block *b, char *buf)
985 {
986         u32 lo, hi;
987 
988         rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
989 
990         return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
991                                      (THRESHOLD_MAX - b->threshold_limit)));
992 }
993 
994 static struct threshold_attr error_count = {
995         .attr = {.name = __stringify(error_count), .mode = 0444 },
996         .show = show_error_count,
997 };
998 
999 #define RW_ATTR(val)                                                    \
1000 static struct threshold_attr val = {                                    \
1001         .attr   = {.name = __stringify(val), .mode = 0644 },            \
1002         .show   = show_## val,                                          \
1003         .store  = store_## val,                                         \
1004 };
1005 
1006 RW_ATTR(interrupt_enable);
1007 RW_ATTR(threshold_limit);
1008 
1009 static struct attribute *default_attrs[] = {
1010         &threshold_limit.attr,
1011         &error_count.attr,
1012         NULL,   /* possibly interrupt_enable if supported, see below */
1013         NULL,
1014 };
1015 
1016 #define to_block(k)     container_of(k, struct threshold_block, kobj)
1017 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
1018 
1019 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1020 {
1021         struct threshold_block *b = to_block(kobj);
1022         struct threshold_attr *a = to_attr(attr);
1023         ssize_t ret;
1024 
1025         ret = a->show ? a->show(b, buf) : -EIO;
1026 
1027         return ret;
1028 }
1029 
1030 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1031                      const char *buf, size_t count)
1032 {
1033         struct threshold_block *b = to_block(kobj);
1034         struct threshold_attr *a = to_attr(attr);
1035         ssize_t ret;
1036 
1037         ret = a->store ? a->store(b, buf, count) : -EIO;
1038 
1039         return ret;
1040 }
1041 
1042 static const struct sysfs_ops threshold_ops = {
1043         .show                   = show,
1044         .store                  = store,
1045 };
1046 
1047 static struct kobj_type threshold_ktype = {
1048         .sysfs_ops              = &threshold_ops,
1049         .default_attrs          = default_attrs,
1050 };
1051 
1052 static const char *get_name(unsigned int bank, struct threshold_block *b)
1053 {
1054         unsigned int bank_type;
1055 
1056         if (!mce_flags.smca) {
1057                 if (b && bank == 4)
1058                         return bank4_names(b);
1059 
1060                 return th_names[bank];
1061         }
1062 
1063         if (!smca_banks[bank].hwid)
1064                 return NULL;
1065 
1066         bank_type = smca_banks[bank].hwid->bank_type;
1067 
1068         if (b && bank_type == SMCA_UMC) {
1069                 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1070                         return smca_umc_block_names[b->block];
1071                 return NULL;
1072         }
1073 
1074         if (smca_banks[bank].hwid->count == 1)
1075                 return smca_get_name(bank_type);
1076 
1077         snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1078                  "%s_%x", smca_get_name(bank_type),
1079                           smca_banks[bank].sysfs_id);
1080         return buf_mcatype;
1081 }
1082 
1083 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
1084                                      unsigned int block, u32 address)
1085 {
1086         struct threshold_block *b = NULL;
1087         u32 low, high;
1088         int err;
1089 
1090         if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
1091                 return 0;
1092 
1093         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1094                 return 0;
1095 
1096         if (!(high & MASK_VALID_HI)) {
1097                 if (block)
1098                         goto recurse;
1099                 else
1100                         return 0;
1101         }
1102 
1103         if (!(high & MASK_CNTP_HI)  ||
1104              (high & MASK_LOCKED_HI))
1105                 goto recurse;
1106 
1107         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1108         if (!b)
1109                 return -ENOMEM;
1110 
1111         b->block                = block;
1112         b->bank                 = bank;
1113         b->cpu                  = cpu;
1114         b->address              = address;
1115         b->interrupt_enable     = 0;
1116         b->interrupt_capable    = lvt_interrupt_supported(bank, high);
1117         b->threshold_limit      = THRESHOLD_MAX;
1118 
1119         if (b->interrupt_capable) {
1120                 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
1121                 b->interrupt_enable = 1;
1122         } else {
1123                 threshold_ktype.default_attrs[2] = NULL;
1124         }
1125 
1126         INIT_LIST_HEAD(&b->miscj);
1127 
1128         if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
1129                 list_add(&b->miscj,
1130                          &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
1131         } else {
1132                 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
1133         }
1134 
1135         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
1136                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
1137                                    get_name(bank, b));
1138         if (err)
1139                 goto out_free;
1140 recurse:
1141         address = get_block_address(cpu, address, low, high, bank, ++block);
1142         if (!address)
1143                 return 0;
1144 
1145         err = allocate_threshold_blocks(cpu, bank, block, address);
1146         if (err)
1147                 goto out_free;
1148 
1149         if (b)
1150                 kobject_uevent(&b->kobj, KOBJ_ADD);
1151 
1152         return err;
1153 
1154 out_free:
1155         if (b) {
1156                 kobject_put(&b->kobj);
1157                 list_del(&b->miscj);
1158                 kfree(b);
1159         }
1160         return err;
1161 }
1162 
1163 static int __threshold_add_blocks(struct threshold_bank *b)
1164 {
1165         struct list_head *head = &b->blocks->miscj;
1166         struct threshold_block *pos = NULL;
1167         struct threshold_block *tmp = NULL;
1168         int err = 0;
1169 
1170         err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1171         if (err)
1172                 return err;
1173 
1174         list_for_each_entry_safe(pos, tmp, head, miscj) {
1175 
1176                 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1177                 if (err) {
1178                         list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1179                                 kobject_del(&pos->kobj);
1180 
1181                         return err;
1182                 }
1183         }
1184         return err;
1185 }
1186 
1187 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1188 {
1189         struct device *dev = per_cpu(mce_device, cpu);
1190         struct amd_northbridge *nb = NULL;
1191         struct threshold_bank *b = NULL;
1192         const char *name = get_name(bank, NULL);
1193         int err = 0;
1194 
1195         if (!dev)
1196                 return -ENODEV;
1197 
1198         if (is_shared_bank(bank)) {
1199                 nb = node_to_amd_nb(amd_get_nb_id(cpu));
1200 
1201                 /* threshold descriptor already initialized on this node? */
1202                 if (nb && nb->bank4) {
1203                         /* yes, use it */
1204                         b = nb->bank4;
1205                         err = kobject_add(b->kobj, &dev->kobj, name);
1206                         if (err)
1207                                 goto out;
1208 
1209                         per_cpu(threshold_banks, cpu)[bank] = b;
1210                         refcount_inc(&b->cpus);
1211 
1212                         err = __threshold_add_blocks(b);
1213 
1214                         goto out;
1215                 }
1216         }
1217 
1218         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1219         if (!b) {
1220                 err = -ENOMEM;
1221                 goto out;
1222         }
1223 
1224         b->kobj = kobject_create_and_add(name, &dev->kobj);
1225         if (!b->kobj) {
1226                 err = -EINVAL;
1227                 goto out_free;
1228         }
1229 
1230         per_cpu(threshold_banks, cpu)[bank] = b;
1231 
1232         if (is_shared_bank(bank)) {
1233                 refcount_set(&b->cpus, 1);
1234 
1235                 /* nb is already initialized, see above */
1236                 if (nb) {
1237                         WARN_ON(nb->bank4);
1238                         nb->bank4 = b;
1239                 }
1240         }
1241 
1242         err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));
1243         if (!err)
1244                 goto out;
1245 
1246  out_free:
1247         kfree(b);
1248 
1249  out:
1250         return err;
1251 }
1252 
1253 static void deallocate_threshold_block(unsigned int cpu,
1254                                                  unsigned int bank)
1255 {
1256         struct threshold_block *pos = NULL;
1257         struct threshold_block *tmp = NULL;
1258         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
1259 
1260         if (!head)
1261                 return;
1262 
1263         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1264                 kobject_put(&pos->kobj);
1265                 list_del(&pos->miscj);
1266                 kfree(pos);
1267         }
1268 
1269         kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
1270         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
1271 }
1272 
1273 static void __threshold_remove_blocks(struct threshold_bank *b)
1274 {
1275         struct threshold_block *pos = NULL;
1276         struct threshold_block *tmp = NULL;
1277 
1278         kobject_del(b->kobj);
1279 
1280         list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1281                 kobject_del(&pos->kobj);
1282 }
1283 
1284 static void threshold_remove_bank(unsigned int cpu, int bank)
1285 {
1286         struct amd_northbridge *nb;
1287         struct threshold_bank *b;
1288 
1289         b = per_cpu(threshold_banks, cpu)[bank];
1290         if (!b)
1291                 return;
1292 
1293         if (!b->blocks)
1294                 goto free_out;
1295 
1296         if (is_shared_bank(bank)) {
1297                 if (!refcount_dec_and_test(&b->cpus)) {
1298                         __threshold_remove_blocks(b);
1299                         per_cpu(threshold_banks, cpu)[bank] = NULL;
1300                         return;
1301                 } else {
1302                         /*
1303                          * the last CPU on this node using the shared bank is
1304                          * going away, remove that bank now.
1305                          */
1306                         nb = node_to_amd_nb(amd_get_nb_id(cpu));
1307                         nb->bank4 = NULL;
1308                 }
1309         }
1310 
1311         deallocate_threshold_block(cpu, bank);
1312 
1313 free_out:
1314         kobject_del(b->kobj);
1315         kobject_put(b->kobj);
1316         kfree(b);
1317         per_cpu(threshold_banks, cpu)[bank] = NULL;
1318 }
1319 
1320 int mce_threshold_remove_device(unsigned int cpu)
1321 {
1322         unsigned int bank;
1323 
1324         if (!thresholding_en)
1325                 return 0;
1326 
1327         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1328                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1329                         continue;
1330                 threshold_remove_bank(cpu, bank);
1331         }
1332         kfree(per_cpu(threshold_banks, cpu));
1333         per_cpu(threshold_banks, cpu) = NULL;
1334         return 0;
1335 }
1336 
1337 /* create dir/files for all valid threshold banks */
1338 int mce_threshold_create_device(unsigned int cpu)
1339 {
1340         unsigned int bank;
1341         struct threshold_bank **bp;
1342         int err = 0;
1343 
1344         if (!thresholding_en)
1345                 return 0;
1346 
1347         bp = per_cpu(threshold_banks, cpu);
1348         if (bp)
1349                 return 0;
1350 
1351         bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
1352                      GFP_KERNEL);
1353         if (!bp)
1354                 return -ENOMEM;
1355 
1356         per_cpu(threshold_banks, cpu) = bp;
1357 
1358         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1359                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1360                         continue;
1361                 err = threshold_create_bank(cpu, bank);
1362                 if (err)
1363                         goto err;
1364         }
1365         return err;
1366 err:
1367         mce_threshold_remove_device(cpu);
1368         return err;
1369 }
1370 
1371 static __init int threshold_init_device(void)
1372 {
1373         unsigned lcpu = 0;
1374 
1375         if (mce_threshold_vector == amd_threshold_interrupt)
1376                 thresholding_en = true;
1377 
1378         /* to hit CPUs online before the notifier is up */
1379         for_each_online_cpu(lcpu) {
1380                 int err = mce_threshold_create_device(lcpu);
1381 
1382                 if (err)
1383                         return err;
1384         }
1385 
1386         return 0;
1387 }
1388 /*
1389  * there are 3 funcs which need to be _initcalled in a logic sequence:
1390  * 1. xen_late_init_mcelog
1391  * 2. mcheck_init_device
1392  * 3. threshold_init_device
1393  *
1394  * xen_late_init_mcelog must register xen_mce_chrdev_device before
1395  * native mce_chrdev_device registration if running under xen platform;
1396  *
1397  * mcheck_init_device should be inited before threshold_init_device to
1398  * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1399  *
1400  * so we use following _initcalls
1401  * 1. device_initcall(xen_late_init_mcelog);
1402  * 2. device_initcall_sync(mcheck_init_device);
1403  * 3. late_initcall(threshold_init_device);
1404  *
1405  * when running under xen, the initcall order is 1,2,3;
1406  * on baremetal, we skip 1 and we do only 2 and 3.
1407  */
1408 late_initcall(threshold_init_device);
1409 

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