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Linux/arch/x86/kernel/irqinit.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 #include <linux/linkage.h>
  3 #include <linux/errno.h>
  4 #include <linux/signal.h>
  5 #include <linux/sched.h>
  6 #include <linux/ioport.h>
  7 #include <linux/interrupt.h>
  8 #include <linux/timex.h>
  9 #include <linux/random.h>
 10 #include <linux/kprobes.h>
 11 #include <linux/init.h>
 12 #include <linux/kernel_stat.h>
 13 #include <linux/device.h>
 14 #include <linux/bitops.h>
 15 #include <linux/acpi.h>
 16 #include <linux/io.h>
 17 #include <linux/delay.h>
 18 
 19 #include <linux/atomic.h>
 20 #include <asm/timer.h>
 21 #include <asm/hw_irq.h>
 22 #include <asm/pgtable.h>
 23 #include <asm/desc.h>
 24 #include <asm/apic.h>
 25 #include <asm/setup.h>
 26 #include <asm/i8259.h>
 27 #include <asm/traps.h>
 28 #include <asm/prom.h>
 29 
 30 /*
 31  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
 32  * (these are usually mapped to vectors 0x30-0x3f)
 33  */
 34 
 35 /*
 36  * The IO-APIC gives us many more interrupt sources. Most of these
 37  * are unused but an SMP system is supposed to have enough memory ...
 38  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
 39  * across the spectrum, so we really want to be prepared to get all
 40  * of these. Plus, more powerful systems might have more than 64
 41  * IO-APIC registers.
 42  *
 43  * (these are usually mapped into the 0x30-0xff vector range)
 44  */
 45 
 46 /*
 47  * IRQ2 is cascade interrupt to second interrupt controller
 48  */
 49 static struct irqaction irq2 = {
 50         .handler = no_action,
 51         .name = "cascade",
 52         .flags = IRQF_NO_THREAD,
 53 };
 54 
 55 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
 56         [0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
 57 };
 58 
 59 void __init init_ISA_irqs(void)
 60 {
 61         struct irq_chip *chip = legacy_pic->chip;
 62         int i;
 63 
 64 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 65         init_bsp_APIC();
 66 #endif
 67         legacy_pic->init(0);
 68 
 69         for (i = 0; i < nr_legacy_irqs(); i++)
 70                 irq_set_chip_and_handler(i, chip, handle_level_irq);
 71 }
 72 
 73 void __init init_IRQ(void)
 74 {
 75         int i;
 76 
 77         /*
 78          * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
 79          * If these IRQ's are handled by legacy interrupt-controllers like PIC,
 80          * then this configuration will likely be static after the boot. If
 81          * these IRQ's are handled by more mordern controllers like IO-APIC,
 82          * then this vector space can be freed and re-used dynamically as the
 83          * irq's migrate etc.
 84          */
 85         for (i = 0; i < nr_legacy_irqs(); i++)
 86                 per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
 87 
 88         x86_init.irqs.intr_init();
 89 }
 90 
 91 void __init native_init_IRQ(void)
 92 {
 93         /* Execute any quirks before the call gates are initialised: */
 94         x86_init.irqs.pre_vector_init();
 95 
 96         idt_setup_apic_and_irq_gates();
 97         lapic_assign_system_vectors();
 98 
 99         if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
100                 setup_irq(2, &irq2);
101 
102         irq_ctx_init(smp_processor_id());
103 }
104 

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