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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/uprobes.c

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  1 /*
  2  * User-space Probes (UProbes) for x86
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License as published by
  6  * the Free Software Foundation; either version 2 of the License, or
  7  * (at your option) any later version.
  8  *
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, write to the Free Software
 16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 17  *
 18  * Copyright (C) IBM Corporation, 2008-2011
 19  * Authors:
 20  *      Srikar Dronamraju
 21  *      Jim Keniston
 22  */
 23 #include <linux/kernel.h>
 24 #include <linux/sched.h>
 25 #include <linux/ptrace.h>
 26 #include <linux/uprobes.h>
 27 #include <linux/uaccess.h>
 28 
 29 #include <linux/kdebug.h>
 30 #include <asm/processor.h>
 31 #include <asm/insn.h>
 32 #include <asm/mmu_context.h>
 33 
 34 /* Post-execution fixups. */
 35 
 36 /* Adjust IP back to vicinity of actual insn */
 37 #define UPROBE_FIX_IP           0x01
 38 
 39 /* Adjust the return address of a call insn */
 40 #define UPROBE_FIX_CALL         0x02
 41 
 42 /* Instruction will modify TF, don't change it */
 43 #define UPROBE_FIX_SETF         0x04
 44 
 45 #define UPROBE_FIX_RIP_SI       0x08
 46 #define UPROBE_FIX_RIP_DI       0x10
 47 #define UPROBE_FIX_RIP_BX       0x20
 48 #define UPROBE_FIX_RIP_MASK     \
 49         (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX)
 50 
 51 #define UPROBE_TRAP_NR          UINT_MAX
 52 
 53 /* Adaptations for mhiramat x86 decoder v14. */
 54 #define OPCODE1(insn)           ((insn)->opcode.bytes[0])
 55 #define OPCODE2(insn)           ((insn)->opcode.bytes[1])
 56 #define OPCODE3(insn)           ((insn)->opcode.bytes[2])
 57 #define MODRM_REG(insn)         X86_MODRM_REG((insn)->modrm.value)
 58 
 59 #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
 60         (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) |   \
 61           (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) |   \
 62           (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) |   \
 63           (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf))    \
 64          << (row % 32))
 65 
 66 /*
 67  * Good-instruction tables for 32-bit apps.  This is non-const and volatile
 68  * to keep gcc from statically optimizing it out, as variable_test_bit makes
 69  * some versions of gcc to think only *(unsigned long*) is used.
 70  *
 71  * Opcodes we'll probably never support:
 72  * 6c-6f - ins,outs. SEGVs if used in userspace
 73  * e4-e7 - in,out imm. SEGVs if used in userspace
 74  * ec-ef - in,out acc. SEGVs if used in userspace
 75  * cc - int3. SIGTRAP if used in userspace
 76  * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs
 77  *      (why we support bound (62) then? it's similar, and similarly unused...)
 78  * f1 - int1. SIGTRAP if used in userspace
 79  * f4 - hlt. SEGVs if used in userspace
 80  * fa - cli. SEGVs if used in userspace
 81  * fb - sti. SEGVs if used in userspace
 82  *
 83  * Opcodes which need some work to be supported:
 84  * 07,17,1f - pop es/ss/ds
 85  *      Normally not used in userspace, but would execute if used.
 86  *      Can cause GP or stack exception if tries to load wrong segment descriptor.
 87  *      We hesitate to run them under single step since kernel's handling
 88  *      of userspace single-stepping (TF flag) is fragile.
 89  *      We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e)
 90  *      on the same grounds that they are never used.
 91  * cd - int N.
 92  *      Used by userspace for "int 80" syscall entry. (Other "int N"
 93  *      cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
 94  *      Not supported since kernel's handling of userspace single-stepping
 95  *      (TF flag) is fragile.
 96  * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
 97  */
 98 #if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
 99 static volatile u32 good_insns_32[256 / 32] = {
100         /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f         */
101         /*      ----------------------------------------------         */
102         W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */
103         W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
104         W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
105         W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
106         W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
107         W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
108         W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
109         W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
110         W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
111         W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
112         W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
113         W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
114         W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
115         W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
116         W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
117         W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1)   /* f0 */
118         /*      ----------------------------------------------         */
119         /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f         */
120 };
121 #else
122 #define good_insns_32   NULL
123 #endif
124 
125 /* Good-instruction tables for 64-bit apps.
126  *
127  * Genuinely invalid opcodes:
128  * 06,07 - formerly push/pop es
129  * 0e - formerly push cs
130  * 16,17 - formerly push/pop ss
131  * 1e,1f - formerly push/pop ds
132  * 27,2f,37,3f - formerly daa/das/aaa/aas
133  * 60,61 - formerly pusha/popa
134  * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported)
135  * 82 - formerly redundant encoding of Group1
136  * 9a - formerly call seg:ofs
137  * ce - formerly into
138  * d4,d5 - formerly aam/aad
139  * d6 - formerly undocumented salc
140  * ea - formerly jmp seg:ofs
141  *
142  * Opcodes we'll probably never support:
143  * 6c-6f - ins,outs. SEGVs if used in userspace
144  * e4-e7 - in,out imm. SEGVs if used in userspace
145  * ec-ef - in,out acc. SEGVs if used in userspace
146  * cc - int3. SIGTRAP if used in userspace
147  * f1 - int1. SIGTRAP if used in userspace
148  * f4 - hlt. SEGVs if used in userspace
149  * fa - cli. SEGVs if used in userspace
150  * fb - sti. SEGVs if used in userspace
151  *
152  * Opcodes which need some work to be supported:
153  * cd - int N.
154  *      Used by userspace for "int 80" syscall entry. (Other "int N"
155  *      cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
156  *      Not supported since kernel's handling of userspace single-stepping
157  *      (TF flag) is fragile.
158  * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
159  */
160 #if defined(CONFIG_X86_64)
161 static volatile u32 good_insns_64[256 / 32] = {
162         /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f         */
163         /*      ----------------------------------------------         */
164         W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */
165         W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
166         W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */
167         W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */
168         W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
169         W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
170         W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
171         W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
172         W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
173         W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */
174         W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
175         W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
176         W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
177         W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
178         W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */
179         W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1)   /* f0 */
180         /*      ----------------------------------------------         */
181         /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f         */
182 };
183 #else
184 #define good_insns_64   NULL
185 #endif
186 
187 /* Using this for both 64-bit and 32-bit apps.
188  * Opcodes we don't support:
189  * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns
190  * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group.
191  *      Also encodes tons of other system insns if mod=11.
192  *      Some are in fact non-system: xend, xtest, rdtscp, maybe more
193  * 0f 05 - syscall
194  * 0f 06 - clts (CPL0 insn)
195  * 0f 07 - sysret
196  * 0f 08 - invd (CPL0 insn)
197  * 0f 09 - wbinvd (CPL0 insn)
198  * 0f 0b - ud2
199  * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?)
200  * 0f 34 - sysenter
201  * 0f 35 - sysexit
202  * 0f 37 - getsec
203  * 0f 78 - vmread (Intel VMX. CPL0 insn)
204  * 0f 79 - vmwrite (Intel VMX. CPL0 insn)
205  *      Note: with prefixes, these two opcodes are
206  *      extrq/insertq/AVX512 convert vector ops.
207  * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt],
208  *      {rd,wr}{fs,gs}base,{s,l,m}fence.
209  *      Why? They are all user-executable.
210  */
211 static volatile u32 good_2byte_insns[256 / 32] = {
212         /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f         */
213         /*      ----------------------------------------------         */
214         W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */
215         W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
216         W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
217         W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
218         W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
219         W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
220         W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
221         W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */
222         W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
223         W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
224         W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
225         W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
226         W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
227         W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
228         W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
229         W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)   /* f0 */
230         /*      ----------------------------------------------         */
231         /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f         */
232 };
233 #undef W
234 
235 /*
236  * opcodes we may need to refine support for:
237  *
238  *  0f - 2-byte instructions: For many of these instructions, the validity
239  *  depends on the prefix and/or the reg field.  On such instructions, we
240  *  just consider the opcode combination valid if it corresponds to any
241  *  valid instruction.
242  *
243  *  8f - Group 1 - only reg = 0 is OK
244  *  c6-c7 - Group 11 - only reg = 0 is OK
245  *  d9-df - fpu insns with some illegal encodings
246  *  f2, f3 - repnz, repz prefixes.  These are also the first byte for
247  *  certain floating-point instructions, such as addsd.
248  *
249  *  fe - Group 4 - only reg = 0 or 1 is OK
250  *  ff - Group 5 - only reg = 0-6 is OK
251  *
252  * others -- Do we need to support these?
253  *
254  *  0f - (floating-point?) prefetch instructions
255  *  07, 17, 1f - pop es, pop ss, pop ds
256  *  26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
257  *      but 64 and 65 (fs: and gs:) seem to be used, so we support them
258  *  67 - addr16 prefix
259  *  ce - into
260  *  f0 - lock prefix
261  */
262 
263 /*
264  * TODO:
265  * - Where necessary, examine the modrm byte and allow only valid instructions
266  * in the different Groups and fpu instructions.
267  */
268 
269 static bool is_prefix_bad(struct insn *insn)
270 {
271         int i;
272 
273         for (i = 0; i < insn->prefixes.nbytes; i++) {
274                 switch (insn->prefixes.bytes[i]) {
275                 case 0x26:      /* INAT_PFX_ES   */
276                 case 0x2E:      /* INAT_PFX_CS   */
277                 case 0x36:      /* INAT_PFX_DS   */
278                 case 0x3E:      /* INAT_PFX_SS   */
279                 case 0xF0:      /* INAT_PFX_LOCK */
280                         return true;
281                 }
282         }
283         return false;
284 }
285 
286 static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64)
287 {
288         u32 volatile *good_insns;
289 
290         insn_init(insn, auprobe->insn, sizeof(auprobe->insn), x86_64);
291         /* has the side-effect of processing the entire instruction */
292         insn_get_length(insn);
293         if (WARN_ON_ONCE(!insn_complete(insn)))
294                 return -ENOEXEC;
295 
296         if (is_prefix_bad(insn))
297                 return -ENOTSUPP;
298 
299         if (x86_64)
300                 good_insns = good_insns_64;
301         else
302                 good_insns = good_insns_32;
303 
304         if (test_bit(OPCODE1(insn), (unsigned long *)good_insns))
305                 return 0;
306 
307         if (insn->opcode.nbytes == 2) {
308                 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
309                         return 0;
310         }
311 
312         return -ENOTSUPP;
313 }
314 
315 #ifdef CONFIG_X86_64
316 /*
317  * If arch_uprobe->insn doesn't use rip-relative addressing, return
318  * immediately.  Otherwise, rewrite the instruction so that it accesses
319  * its memory operand indirectly through a scratch register.  Set
320  * defparam->fixups accordingly. (The contents of the scratch register
321  * will be saved before we single-step the modified instruction,
322  * and restored afterward).
323  *
324  * We do this because a rip-relative instruction can access only a
325  * relatively small area (+/- 2 GB from the instruction), and the XOL
326  * area typically lies beyond that area.  At least for instructions
327  * that store to memory, we can't execute the original instruction
328  * and "fix things up" later, because the misdirected store could be
329  * disastrous.
330  *
331  * Some useful facts about rip-relative instructions:
332  *
333  *  - There's always a modrm byte with bit layout "00 reg 101".
334  *  - There's never a SIB byte.
335  *  - The displacement is always 4 bytes.
336  *  - REX.B=1 bit in REX prefix, which normally extends r/m field,
337  *    has no effect on rip-relative mode. It doesn't make modrm byte
338  *    with r/m=101 refer to register 1101 = R13.
339  */
340 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
341 {
342         u8 *cursor;
343         u8 reg;
344         u8 reg2;
345 
346         if (!insn_rip_relative(insn))
347                 return;
348 
349         /*
350          * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm.
351          * Clear REX.b bit (extension of MODRM.rm field):
352          * we want to encode low numbered reg, not r8+.
353          */
354         if (insn->rex_prefix.nbytes) {
355                 cursor = auprobe->insn + insn_offset_rex_prefix(insn);
356                 /* REX byte has 0100wrxb layout, clearing REX.b bit */
357                 *cursor &= 0xfe;
358         }
359         /*
360          * Similar treatment for VEX3 prefix.
361          * TODO: add XOP/EVEX treatment when insn decoder supports them
362          */
363         if (insn->vex_prefix.nbytes == 3) {
364                 /*
365                  * vex2:     c5    rvvvvLpp   (has no b bit)
366                  * vex3/xop: c4/8f rxbmmmmm wvvvvLpp
367                  * evex:     62    rxbR00mm wvvvv1pp zllBVaaa
368                  *   (evex will need setting of both b and x since
369                  *   in non-sib encoding evex.x is 4th bit of MODRM.rm)
370                  * Setting VEX3.b (setting because it has inverted meaning):
371                  */
372                 cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1;
373                 *cursor |= 0x20;
374         }
375 
376         /*
377          * Convert from rip-relative addressing to register-relative addressing
378          * via a scratch register.
379          *
380          * This is tricky since there are insns with modrm byte
381          * which also use registers not encoded in modrm byte:
382          * [i]div/[i]mul: implicitly use dx:ax
383          * shift ops: implicitly use cx
384          * cmpxchg: implicitly uses ax
385          * cmpxchg8/16b: implicitly uses dx:ax and bx:cx
386          *   Encoding: 0f c7/1 modrm
387          *   The code below thinks that reg=1 (cx), chooses si as scratch.
388          * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m.
389          *   First appeared in Haswell (BMI2 insn). It is vex-encoded.
390          *   Example where none of bx,cx,dx can be used as scratch reg:
391          *   c4 e2 63 f6 0d disp32   mulx disp32(%rip),%ebx,%ecx
392          * [v]pcmpistri: implicitly uses cx, xmm0
393          * [v]pcmpistrm: implicitly uses xmm0
394          * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0
395          * [v]pcmpestrm: implicitly uses ax, dx, xmm0
396          *   Evil SSE4.2 string comparison ops from hell.
397          * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination.
398          *   Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm.
399          *   Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi).
400          *   AMD says it has no 3-operand form (vex.vvvv must be 1111)
401          *   and that it can have only register operands, not mem
402          *   (its modrm byte must have mode=11).
403          *   If these restrictions will ever be lifted,
404          *   we'll need code to prevent selection of di as scratch reg!
405          *
406          * Summary: I don't know any insns with modrm byte which
407          * use SI register implicitly. DI register is used only
408          * by one insn (maskmovq) and BX register is used
409          * only by one too (cmpxchg8b).
410          * BP is stack-segment based (may be a problem?).
411          * AX, DX, CX are off-limits (many implicit users).
412          * SP is unusable (it's stack pointer - think about "pop mem";
413          * also, rsp+disp32 needs sib encoding -> insn length change).
414          */
415 
416         reg = MODRM_REG(insn);  /* Fetch modrm.reg */
417         reg2 = 0xff;            /* Fetch vex.vvvv */
418         if (insn->vex_prefix.nbytes == 2)
419                 reg2 = insn->vex_prefix.bytes[1];
420         else if (insn->vex_prefix.nbytes == 3)
421                 reg2 = insn->vex_prefix.bytes[2];
422         /*
423          * TODO: add XOP, EXEV vvvv reading.
424          *
425          * vex.vvvv field is in bits 6-3, bits are inverted.
426          * But in 32-bit mode, high-order bit may be ignored.
427          * Therefore, let's consider only 3 low-order bits.
428          */
429         reg2 = ((reg2 >> 3) & 0x7) ^ 0x7;
430         /*
431          * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15.
432          *
433          * Choose scratch reg. Order is important: must not select bx
434          * if we can use si (cmpxchg8b case!)
435          */
436         if (reg != 6 && reg2 != 6) {
437                 reg2 = 6;
438                 auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI;
439         } else if (reg != 7 && reg2 != 7) {
440                 reg2 = 7;
441                 auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI;
442                 /* TODO (paranoia): force maskmovq to not use di */
443         } else {
444                 reg2 = 3;
445                 auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX;
446         }
447         /*
448          * Point cursor at the modrm byte.  The next 4 bytes are the
449          * displacement.  Beyond the displacement, for some instructions,
450          * is the immediate operand.
451          */
452         cursor = auprobe->insn + insn_offset_modrm(insn);
453         /*
454          * Change modrm from "00 reg 101" to "10 reg reg2". Example:
455          * 89 05 disp32  mov %eax,disp32(%rip) becomes
456          * 89 86 disp32  mov %eax,disp32(%rsi)
457          */
458         *cursor = 0x80 | (reg << 3) | reg2;
459 }
460 
461 static inline unsigned long *
462 scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs)
463 {
464         if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI)
465                 return &regs->si;
466         if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI)
467                 return &regs->di;
468         return &regs->bx;
469 }
470 
471 /*
472  * If we're emulating a rip-relative instruction, save the contents
473  * of the scratch register and store the target address in that register.
474  */
475 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
476 {
477         if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
478                 struct uprobe_task *utask = current->utask;
479                 unsigned long *sr = scratch_reg(auprobe, regs);
480 
481                 utask->autask.saved_scratch_register = *sr;
482                 *sr = utask->vaddr + auprobe->defparam.ilen;
483         }
484 }
485 
486 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
487 {
488         if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
489                 struct uprobe_task *utask = current->utask;
490                 unsigned long *sr = scratch_reg(auprobe, regs);
491 
492                 *sr = utask->autask.saved_scratch_register;
493         }
494 }
495 #else /* 32-bit: */
496 /*
497  * No RIP-relative addressing on 32-bit
498  */
499 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
500 {
501 }
502 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
503 {
504 }
505 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
506 {
507 }
508 #endif /* CONFIG_X86_64 */
509 
510 struct uprobe_xol_ops {
511         bool    (*emulate)(struct arch_uprobe *, struct pt_regs *);
512         int     (*pre_xol)(struct arch_uprobe *, struct pt_regs *);
513         int     (*post_xol)(struct arch_uprobe *, struct pt_regs *);
514         void    (*abort)(struct arch_uprobe *, struct pt_regs *);
515 };
516 
517 static inline int sizeof_long(void)
518 {
519         return is_ia32_task() ? 4 : 8;
520 }
521 
522 static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
523 {
524         riprel_pre_xol(auprobe, regs);
525         return 0;
526 }
527 
528 static int push_ret_address(struct pt_regs *regs, unsigned long ip)
529 {
530         unsigned long new_sp = regs->sp - sizeof_long();
531 
532         if (copy_to_user((void __user *)new_sp, &ip, sizeof_long()))
533                 return -EFAULT;
534 
535         regs->sp = new_sp;
536         return 0;
537 }
538 
539 /*
540  * We have to fix things up as follows:
541  *
542  * Typically, the new ip is relative to the copied instruction.  We need
543  * to make it relative to the original instruction (FIX_IP).  Exceptions
544  * are return instructions and absolute or indirect jump or call instructions.
545  *
546  * If the single-stepped instruction was a call, the return address that
547  * is atop the stack is the address following the copied instruction.  We
548  * need to make it the address following the original instruction (FIX_CALL).
549  *
550  * If the original instruction was a rip-relative instruction such as
551  * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent
552  * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)".
553  * We need to restore the contents of the scratch register
554  * (FIX_RIP_reg).
555  */
556 static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
557 {
558         struct uprobe_task *utask = current->utask;
559 
560         riprel_post_xol(auprobe, regs);
561         if (auprobe->defparam.fixups & UPROBE_FIX_IP) {
562                 long correction = utask->vaddr - utask->xol_vaddr;
563                 regs->ip += correction;
564         } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) {
565                 regs->sp += sizeof_long(); /* Pop incorrect return address */
566                 if (push_ret_address(regs, utask->vaddr + auprobe->defparam.ilen))
567                         return -ERESTART;
568         }
569         /* popf; tell the caller to not touch TF */
570         if (auprobe->defparam.fixups & UPROBE_FIX_SETF)
571                 utask->autask.saved_tf = true;
572 
573         return 0;
574 }
575 
576 static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
577 {
578         riprel_post_xol(auprobe, regs);
579 }
580 
581 static struct uprobe_xol_ops default_xol_ops = {
582         .pre_xol  = default_pre_xol_op,
583         .post_xol = default_post_xol_op,
584         .abort    = default_abort_op,
585 };
586 
587 static bool branch_is_call(struct arch_uprobe *auprobe)
588 {
589         return auprobe->branch.opc1 == 0xe8;
590 }
591 
592 #define CASE_COND                                       \
593         COND(70, 71, XF(OF))                            \
594         COND(72, 73, XF(CF))                            \
595         COND(74, 75, XF(ZF))                            \
596         COND(78, 79, XF(SF))                            \
597         COND(7a, 7b, XF(PF))                            \
598         COND(76, 77, XF(CF) || XF(ZF))                  \
599         COND(7c, 7d, XF(SF) != XF(OF))                  \
600         COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF))
601 
602 #define COND(op_y, op_n, expr)                          \
603         case 0x ## op_y: DO((expr) != 0)                \
604         case 0x ## op_n: DO((expr) == 0)
605 
606 #define XF(xf)  (!!(flags & X86_EFLAGS_ ## xf))
607 
608 static bool is_cond_jmp_opcode(u8 opcode)
609 {
610         switch (opcode) {
611         #define DO(expr)        \
612                 return true;
613         CASE_COND
614         #undef  DO
615 
616         default:
617                 return false;
618         }
619 }
620 
621 static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs)
622 {
623         unsigned long flags = regs->flags;
624 
625         switch (auprobe->branch.opc1) {
626         #define DO(expr)        \
627                 return expr;
628         CASE_COND
629         #undef  DO
630 
631         default:        /* not a conditional jmp */
632                 return true;
633         }
634 }
635 
636 #undef  XF
637 #undef  COND
638 #undef  CASE_COND
639 
640 static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
641 {
642         unsigned long new_ip = regs->ip += auprobe->branch.ilen;
643         unsigned long offs = (long)auprobe->branch.offs;
644 
645         if (branch_is_call(auprobe)) {
646                 /*
647                  * If it fails we execute this (mangled, see the comment in
648                  * branch_clear_offset) insn out-of-line. In the likely case
649                  * this should trigger the trap, and the probed application
650                  * should die or restart the same insn after it handles the
651                  * signal, arch_uprobe_post_xol() won't be even called.
652                  *
653                  * But there is corner case, see the comment in ->post_xol().
654                  */
655                 if (push_ret_address(regs, new_ip))
656                         return false;
657         } else if (!check_jmp_cond(auprobe, regs)) {
658                 offs = 0;
659         }
660 
661         regs->ip = new_ip + offs;
662         return true;
663 }
664 
665 static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
666 {
667         BUG_ON(!branch_is_call(auprobe));
668         /*
669          * We can only get here if branch_emulate_op() failed to push the ret
670          * address _and_ another thread expanded our stack before the (mangled)
671          * "call" insn was executed out-of-line. Just restore ->sp and restart.
672          * We could also restore ->ip and try to call branch_emulate_op() again.
673          */
674         regs->sp += sizeof_long();
675         return -ERESTART;
676 }
677 
678 static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn)
679 {
680         /*
681          * Turn this insn into "call 1f; 1:", this is what we will execute
682          * out-of-line if ->emulate() fails. We only need this to generate
683          * a trap, so that the probed task receives the correct signal with
684          * the properly filled siginfo.
685          *
686          * But see the comment in ->post_xol(), in the unlikely case it can
687          * succeed. So we need to ensure that the new ->ip can not fall into
688          * the non-canonical area and trigger #GP.
689          *
690          * We could turn it into (say) "pushf", but then we would need to
691          * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte
692          * of ->insn[] for set_orig_insn().
693          */
694         memset(auprobe->insn + insn_offset_immediate(insn),
695                 0, insn->immediate.nbytes);
696 }
697 
698 static struct uprobe_xol_ops branch_xol_ops = {
699         .emulate  = branch_emulate_op,
700         .post_xol = branch_post_xol_op,
701 };
702 
703 /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */
704 static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
705 {
706         u8 opc1 = OPCODE1(insn);
707         int i;
708 
709         switch (opc1) {
710         case 0xeb:      /* jmp 8 */
711         case 0xe9:      /* jmp 32 */
712         case 0x90:      /* prefix* + nop; same as jmp with .offs = 0 */
713                 break;
714 
715         case 0xe8:      /* call relative */
716                 branch_clear_offset(auprobe, insn);
717                 break;
718 
719         case 0x0f:
720                 if (insn->opcode.nbytes != 2)
721                         return -ENOSYS;
722                 /*
723                  * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches
724                  * OPCODE1() of the "short" jmp which checks the same condition.
725                  */
726                 opc1 = OPCODE2(insn) - 0x10;
727         default:
728                 if (!is_cond_jmp_opcode(opc1))
729                         return -ENOSYS;
730         }
731 
732         /*
733          * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported.
734          * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix.
735          * No one uses these insns, reject any branch insns with such prefix.
736          */
737         for (i = 0; i < insn->prefixes.nbytes; i++) {
738                 if (insn->prefixes.bytes[i] == 0x66)
739                         return -ENOTSUPP;
740         }
741 
742         auprobe->branch.opc1 = opc1;
743         auprobe->branch.ilen = insn->length;
744         auprobe->branch.offs = insn->immediate.value;
745 
746         auprobe->ops = &branch_xol_ops;
747         return 0;
748 }
749 
750 /**
751  * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
752  * @mm: the probed address space.
753  * @arch_uprobe: the probepoint information.
754  * @addr: virtual address at which to install the probepoint
755  * Return 0 on success or a -ve number on error.
756  */
757 int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr)
758 {
759         struct insn insn;
760         u8 fix_ip_or_call = UPROBE_FIX_IP;
761         int ret;
762 
763         ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm));
764         if (ret)
765                 return ret;
766 
767         ret = branch_setup_xol_ops(auprobe, &insn);
768         if (ret != -ENOSYS)
769                 return ret;
770 
771         /*
772          * Figure out which fixups default_post_xol_op() will need to perform,
773          * and annotate defparam->fixups accordingly.
774          */
775         switch (OPCODE1(&insn)) {
776         case 0x9d:              /* popf */
777                 auprobe->defparam.fixups |= UPROBE_FIX_SETF;
778                 break;
779         case 0xc3:              /* ret or lret -- ip is correct */
780         case 0xcb:
781         case 0xc2:
782         case 0xca:
783         case 0xea:              /* jmp absolute -- ip is correct */
784                 fix_ip_or_call = 0;
785                 break;
786         case 0x9a:              /* call absolute - Fix return addr, not ip */
787                 fix_ip_or_call = UPROBE_FIX_CALL;
788                 break;
789         case 0xff:
790                 switch (MODRM_REG(&insn)) {
791                 case 2: case 3:                 /* call or lcall, indirect */
792                         fix_ip_or_call = UPROBE_FIX_CALL;
793                         break;
794                 case 4: case 5:                 /* jmp or ljmp, indirect */
795                         fix_ip_or_call = 0;
796                         break;
797                 }
798                 /* fall through */
799         default:
800                 riprel_analyze(auprobe, &insn);
801         }
802 
803         auprobe->defparam.ilen = insn.length;
804         auprobe->defparam.fixups |= fix_ip_or_call;
805 
806         auprobe->ops = &default_xol_ops;
807         return 0;
808 }
809 
810 /*
811  * arch_uprobe_pre_xol - prepare to execute out of line.
812  * @auprobe: the probepoint information.
813  * @regs: reflects the saved user state of current task.
814  */
815 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
816 {
817         struct uprobe_task *utask = current->utask;
818 
819         if (auprobe->ops->pre_xol) {
820                 int err = auprobe->ops->pre_xol(auprobe, regs);
821                 if (err)
822                         return err;
823         }
824 
825         regs->ip = utask->xol_vaddr;
826         utask->autask.saved_trap_nr = current->thread.trap_nr;
827         current->thread.trap_nr = UPROBE_TRAP_NR;
828 
829         utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF);
830         regs->flags |= X86_EFLAGS_TF;
831         if (test_tsk_thread_flag(current, TIF_BLOCKSTEP))
832                 set_task_blockstep(current, false);
833 
834         return 0;
835 }
836 
837 /*
838  * If xol insn itself traps and generates a signal(Say,
839  * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
840  * instruction jumps back to its own address. It is assumed that anything
841  * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
842  *
843  * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
844  * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
845  * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
846  */
847 bool arch_uprobe_xol_was_trapped(struct task_struct *t)
848 {
849         if (t->thread.trap_nr != UPROBE_TRAP_NR)
850                 return true;
851 
852         return false;
853 }
854 
855 /*
856  * Called after single-stepping. To avoid the SMP problems that can
857  * occur when we temporarily put back the original opcode to
858  * single-step, we single-stepped a copy of the instruction.
859  *
860  * This function prepares to resume execution after the single-step.
861  */
862 int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
863 {
864         struct uprobe_task *utask = current->utask;
865         bool send_sigtrap = utask->autask.saved_tf;
866         int err = 0;
867 
868         WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
869         current->thread.trap_nr = utask->autask.saved_trap_nr;
870 
871         if (auprobe->ops->post_xol) {
872                 err = auprobe->ops->post_xol(auprobe, regs);
873                 if (err) {
874                         /*
875                          * Restore ->ip for restart or post mortem analysis.
876                          * ->post_xol() must not return -ERESTART unless this
877                          * is really possible.
878                          */
879                         regs->ip = utask->vaddr;
880                         if (err == -ERESTART)
881                                 err = 0;
882                         send_sigtrap = false;
883                 }
884         }
885         /*
886          * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP
887          * so we can get an extra SIGTRAP if we do not clear TF. We need
888          * to examine the opcode to make it right.
889          */
890         if (send_sigtrap)
891                 send_sig(SIGTRAP, current, 0);
892 
893         if (!utask->autask.saved_tf)
894                 regs->flags &= ~X86_EFLAGS_TF;
895 
896         return err;
897 }
898 
899 /* callback routine for handling exceptions. */
900 int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
901 {
902         struct die_args *args = data;
903         struct pt_regs *regs = args->regs;
904         int ret = NOTIFY_DONE;
905 
906         /* We are only interested in userspace traps */
907         if (regs && !user_mode(regs))
908                 return NOTIFY_DONE;
909 
910         switch (val) {
911         case DIE_INT3:
912                 if (uprobe_pre_sstep_notifier(regs))
913                         ret = NOTIFY_STOP;
914 
915                 break;
916 
917         case DIE_DEBUG:
918                 if (uprobe_post_sstep_notifier(regs))
919                         ret = NOTIFY_STOP;
920 
921         default:
922                 break;
923         }
924 
925         return ret;
926 }
927 
928 /*
929  * This function gets called when XOL instruction either gets trapped or
930  * the thread has a fatal signal. Reset the instruction pointer to its
931  * probed address for the potential restart or for post mortem analysis.
932  */
933 void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
934 {
935         struct uprobe_task *utask = current->utask;
936 
937         if (auprobe->ops->abort)
938                 auprobe->ops->abort(auprobe, regs);
939 
940         current->thread.trap_nr = utask->autask.saved_trap_nr;
941         regs->ip = utask->vaddr;
942         /* clear TF if it was set by us in arch_uprobe_pre_xol() */
943         if (!utask->autask.saved_tf)
944                 regs->flags &= ~X86_EFLAGS_TF;
945 }
946 
947 static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
948 {
949         if (auprobe->ops->emulate)
950                 return auprobe->ops->emulate(auprobe, regs);
951         return false;
952 }
953 
954 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
955 {
956         bool ret = __skip_sstep(auprobe, regs);
957         if (ret && (regs->flags & X86_EFLAGS_TF))
958                 send_sig(SIGTRAP, current, 0);
959         return ret;
960 }
961 
962 unsigned long
963 arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
964 {
965         int rasize = sizeof_long(), nleft;
966         unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
967 
968         if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize))
969                 return -1;
970 
971         /* check whether address has been already hijacked */
972         if (orig_ret_vaddr == trampoline_vaddr)
973                 return orig_ret_vaddr;
974 
975         nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize);
976         if (likely(!nleft))
977                 return orig_ret_vaddr;
978 
979         if (nleft != rasize) {
980                 pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, "
981                         "%%ip=%#lx\n", current->pid, regs->sp, regs->ip);
982 
983                 force_sig_info(SIGSEGV, SEND_SIG_FORCED, current);
984         }
985 
986         return -1;
987 }
988 
989 bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
990                                 struct pt_regs *regs)
991 {
992         if (ctx == RP_CHECK_CALL) /* sp was just decremented by "call" insn */
993                 return regs->sp < ret->stack;
994         else
995                 return regs->sp <= ret->stack;
996 }
997 

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