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Linux/arch/x86/kvm/mmu.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * This module enables machines with Intel VT-x extensions to run virtual
  5  * machines without emulation or binary translation.
  6  *
  7  * MMU support
  8  *
  9  * Copyright (C) 2006 Qumranet, Inc.
 10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 11  *
 12  * Authors:
 13  *   Yaniv Kamay  <yaniv@qumranet.com>
 14  *   Avi Kivity   <avi@qumranet.com>
 15  *
 16  * This work is licensed under the terms of the GNU GPL, version 2.  See
 17  * the COPYING file in the top-level directory.
 18  *
 19  */
 20 
 21 #include "irq.h"
 22 #include "mmu.h"
 23 #include "x86.h"
 24 #include "kvm_cache_regs.h"
 25 #include "cpuid.h"
 26 
 27 #include <linux/kvm_host.h>
 28 #include <linux/types.h>
 29 #include <linux/string.h>
 30 #include <linux/mm.h>
 31 #include <linux/highmem.h>
 32 #include <linux/moduleparam.h>
 33 #include <linux/export.h>
 34 #include <linux/swap.h>
 35 #include <linux/hugetlb.h>
 36 #include <linux/compiler.h>
 37 #include <linux/srcu.h>
 38 #include <linux/slab.h>
 39 #include <linux/sched/signal.h>
 40 #include <linux/uaccess.h>
 41 #include <linux/hash.h>
 42 #include <linux/kern_levels.h>
 43 
 44 #include <asm/page.h>
 45 #include <asm/cmpxchg.h>
 46 #include <asm/io.h>
 47 #include <asm/vmx.h>
 48 #include <asm/kvm_page_track.h>
 49 #include "trace.h"
 50 
 51 /*
 52  * When setting this variable to true it enables Two-Dimensional-Paging
 53  * where the hardware walks 2 page tables:
 54  * 1. the guest-virtual to guest-physical
 55  * 2. while doing 1. it walks guest-physical to host-physical
 56  * If the hardware supports that we don't need to do shadow paging.
 57  */
 58 bool tdp_enabled = false;
 59 
 60 enum {
 61         AUDIT_PRE_PAGE_FAULT,
 62         AUDIT_POST_PAGE_FAULT,
 63         AUDIT_PRE_PTE_WRITE,
 64         AUDIT_POST_PTE_WRITE,
 65         AUDIT_PRE_SYNC,
 66         AUDIT_POST_SYNC
 67 };
 68 
 69 #undef MMU_DEBUG
 70 
 71 #ifdef MMU_DEBUG
 72 static bool dbg = 0;
 73 module_param(dbg, bool, 0644);
 74 
 75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
 76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
 77 #define MMU_WARN_ON(x) WARN_ON(x)
 78 #else
 79 #define pgprintk(x...) do { } while (0)
 80 #define rmap_printk(x...) do { } while (0)
 81 #define MMU_WARN_ON(x) do { } while (0)
 82 #endif
 83 
 84 #define PTE_PREFETCH_NUM                8
 85 
 86 #define PT_FIRST_AVAIL_BITS_SHIFT 10
 87 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
 88 
 89 #define PT64_LEVEL_BITS 9
 90 
 91 #define PT64_LEVEL_SHIFT(level) \
 92                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
 93 
 94 #define PT64_INDEX(address, level)\
 95         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
 96 
 97 
 98 #define PT32_LEVEL_BITS 10
 99 
100 #define PT32_LEVEL_SHIFT(level) \
101                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
102 
103 #define PT32_LVL_OFFSET_MASK(level) \
104         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
105                                                 * PT32_LEVEL_BITS))) - 1))
106 
107 #define PT32_INDEX(address, level)\
108         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
109 
110 
111 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
112 #define PT64_DIR_BASE_ADDR_MASK \
113         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
114 #define PT64_LVL_ADDR_MASK(level) \
115         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
116                                                 * PT64_LEVEL_BITS))) - 1))
117 #define PT64_LVL_OFFSET_MASK(level) \
118         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
119                                                 * PT64_LEVEL_BITS))) - 1))
120 
121 #define PT32_BASE_ADDR_MASK PAGE_MASK
122 #define PT32_DIR_BASE_ADDR_MASK \
123         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
124 #define PT32_LVL_ADDR_MASK(level) \
125         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
126                                             * PT32_LEVEL_BITS))) - 1))
127 
128 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
129                         | shadow_x_mask | shadow_nx_mask)
130 
131 #define ACC_EXEC_MASK    1
132 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
133 #define ACC_USER_MASK    PT_USER_MASK
134 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
135 
136 /* The mask for the R/X bits in EPT PTEs */
137 #define PT64_EPT_READABLE_MASK                  0x1ull
138 #define PT64_EPT_EXECUTABLE_MASK                0x4ull
139 
140 #include <trace/events/kvm.h>
141 
142 #define CREATE_TRACE_POINTS
143 #include "mmutrace.h"
144 
145 #define SPTE_HOST_WRITEABLE     (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
146 #define SPTE_MMU_WRITEABLE      (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
147 
148 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
149 
150 /* make pte_list_desc fit well in cache line */
151 #define PTE_LIST_EXT 3
152 
153 struct pte_list_desc {
154         u64 *sptes[PTE_LIST_EXT];
155         struct pte_list_desc *more;
156 };
157 
158 struct kvm_shadow_walk_iterator {
159         u64 addr;
160         hpa_t shadow_addr;
161         u64 *sptep;
162         int level;
163         unsigned index;
164 };
165 
166 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
167         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
168              shadow_walk_okay(&(_walker));                      \
169              shadow_walk_next(&(_walker)))
170 
171 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
172         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
173              shadow_walk_okay(&(_walker)) &&                            \
174                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
175              __shadow_walk_next(&(_walker), spte))
176 
177 static struct kmem_cache *pte_list_desc_cache;
178 static struct kmem_cache *mmu_page_header_cache;
179 static struct percpu_counter kvm_total_used_mmu_pages;
180 
181 static u64 __read_mostly shadow_nx_mask;
182 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
183 static u64 __read_mostly shadow_user_mask;
184 static u64 __read_mostly shadow_accessed_mask;
185 static u64 __read_mostly shadow_dirty_mask;
186 static u64 __read_mostly shadow_mmio_mask;
187 static u64 __read_mostly shadow_mmio_value;
188 static u64 __read_mostly shadow_present_mask;
189 
190 /*
191  * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
192  * Non-present SPTEs with shadow_acc_track_value set are in place for access
193  * tracking.
194  */
195 static u64 __read_mostly shadow_acc_track_mask;
196 static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
197 
198 /*
199  * The mask/shift to use for saving the original R/X bits when marking the PTE
200  * as not-present for access tracking purposes. We do not save the W bit as the
201  * PTEs being access tracked also need to be dirty tracked, so the W bit will be
202  * restored only when a write is attempted to the page.
203  */
204 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
205                                                     PT64_EPT_EXECUTABLE_MASK;
206 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
207 
208 static void mmu_spte_set(u64 *sptep, u64 spte);
209 static void mmu_free_roots(struct kvm_vcpu *vcpu);
210 
211 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value)
212 {
213         BUG_ON((mmio_mask & mmio_value) != mmio_value);
214         shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK;
215         shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
216 }
217 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
218 
219 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
220 {
221         return sp->role.ad_disabled;
222 }
223 
224 static inline bool spte_ad_enabled(u64 spte)
225 {
226         MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
227         return !(spte & shadow_acc_track_value);
228 }
229 
230 static inline u64 spte_shadow_accessed_mask(u64 spte)
231 {
232         MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
233         return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
234 }
235 
236 static inline u64 spte_shadow_dirty_mask(u64 spte)
237 {
238         MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
239         return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
240 }
241 
242 static inline bool is_access_track_spte(u64 spte)
243 {
244         return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
245 }
246 
247 /*
248  * the low bit of the generation number is always presumed to be zero.
249  * This disables mmio caching during memslot updates.  The concept is
250  * similar to a seqcount but instead of retrying the access we just punt
251  * and ignore the cache.
252  *
253  * spte bits 3-11 are used as bits 1-9 of the generation number,
254  * the bits 52-61 are used as bits 10-19 of the generation number.
255  */
256 #define MMIO_SPTE_GEN_LOW_SHIFT         2
257 #define MMIO_SPTE_GEN_HIGH_SHIFT        52
258 
259 #define MMIO_GEN_SHIFT                  20
260 #define MMIO_GEN_LOW_SHIFT              10
261 #define MMIO_GEN_LOW_MASK               ((1 << MMIO_GEN_LOW_SHIFT) - 2)
262 #define MMIO_GEN_MASK                   ((1 << MMIO_GEN_SHIFT) - 1)
263 
264 static u64 generation_mmio_spte_mask(unsigned int gen)
265 {
266         u64 mask;
267 
268         WARN_ON(gen & ~MMIO_GEN_MASK);
269 
270         mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
271         mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
272         return mask;
273 }
274 
275 static unsigned int get_mmio_spte_generation(u64 spte)
276 {
277         unsigned int gen;
278 
279         spte &= ~shadow_mmio_mask;
280 
281         gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
282         gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
283         return gen;
284 }
285 
286 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
287 {
288         return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
289 }
290 
291 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
292                            unsigned access)
293 {
294         unsigned int gen = kvm_current_mmio_generation(vcpu);
295         u64 mask = generation_mmio_spte_mask(gen);
296 
297         access &= ACC_WRITE_MASK | ACC_USER_MASK;
298         mask |= shadow_mmio_value | access | gfn << PAGE_SHIFT;
299 
300         trace_mark_mmio_spte(sptep, gfn, access, gen);
301         mmu_spte_set(sptep, mask);
302 }
303 
304 static bool is_mmio_spte(u64 spte)
305 {
306         return (spte & shadow_mmio_mask) == shadow_mmio_value;
307 }
308 
309 static gfn_t get_mmio_spte_gfn(u64 spte)
310 {
311         u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
312         return (spte & ~mask) >> PAGE_SHIFT;
313 }
314 
315 static unsigned get_mmio_spte_access(u64 spte)
316 {
317         u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
318         return (spte & ~mask) & ~PAGE_MASK;
319 }
320 
321 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
322                           kvm_pfn_t pfn, unsigned access)
323 {
324         if (unlikely(is_noslot_pfn(pfn))) {
325                 mark_mmio_spte(vcpu, sptep, gfn, access);
326                 return true;
327         }
328 
329         return false;
330 }
331 
332 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
333 {
334         unsigned int kvm_gen, spte_gen;
335 
336         kvm_gen = kvm_current_mmio_generation(vcpu);
337         spte_gen = get_mmio_spte_generation(spte);
338 
339         trace_check_mmio_spte(spte, kvm_gen, spte_gen);
340         return likely(kvm_gen == spte_gen);
341 }
342 
343 /*
344  * Sets the shadow PTE masks used by the MMU.
345  *
346  * Assumptions:
347  *  - Setting either @accessed_mask or @dirty_mask requires setting both
348  *  - At least one of @accessed_mask or @acc_track_mask must be set
349  */
350 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
351                 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
352                 u64 acc_track_mask)
353 {
354         BUG_ON(!dirty_mask != !accessed_mask);
355         BUG_ON(!accessed_mask && !acc_track_mask);
356         BUG_ON(acc_track_mask & shadow_acc_track_value);
357 
358         shadow_user_mask = user_mask;
359         shadow_accessed_mask = accessed_mask;
360         shadow_dirty_mask = dirty_mask;
361         shadow_nx_mask = nx_mask;
362         shadow_x_mask = x_mask;
363         shadow_present_mask = p_mask;
364         shadow_acc_track_mask = acc_track_mask;
365 }
366 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
367 
368 void kvm_mmu_clear_all_pte_masks(void)
369 {
370         shadow_user_mask = 0;
371         shadow_accessed_mask = 0;
372         shadow_dirty_mask = 0;
373         shadow_nx_mask = 0;
374         shadow_x_mask = 0;
375         shadow_mmio_mask = 0;
376         shadow_present_mask = 0;
377         shadow_acc_track_mask = 0;
378 }
379 
380 static int is_cpuid_PSE36(void)
381 {
382         return 1;
383 }
384 
385 static int is_nx(struct kvm_vcpu *vcpu)
386 {
387         return vcpu->arch.efer & EFER_NX;
388 }
389 
390 static int is_shadow_present_pte(u64 pte)
391 {
392         return (pte != 0) && !is_mmio_spte(pte);
393 }
394 
395 static int is_large_pte(u64 pte)
396 {
397         return pte & PT_PAGE_SIZE_MASK;
398 }
399 
400 static int is_last_spte(u64 pte, int level)
401 {
402         if (level == PT_PAGE_TABLE_LEVEL)
403                 return 1;
404         if (is_large_pte(pte))
405                 return 1;
406         return 0;
407 }
408 
409 static bool is_executable_pte(u64 spte)
410 {
411         return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
412 }
413 
414 static kvm_pfn_t spte_to_pfn(u64 pte)
415 {
416         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
417 }
418 
419 static gfn_t pse36_gfn_delta(u32 gpte)
420 {
421         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
422 
423         return (gpte & PT32_DIR_PSE36_MASK) << shift;
424 }
425 
426 #ifdef CONFIG_X86_64
427 static void __set_spte(u64 *sptep, u64 spte)
428 {
429         WRITE_ONCE(*sptep, spte);
430 }
431 
432 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
433 {
434         WRITE_ONCE(*sptep, spte);
435 }
436 
437 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
438 {
439         return xchg(sptep, spte);
440 }
441 
442 static u64 __get_spte_lockless(u64 *sptep)
443 {
444         return ACCESS_ONCE(*sptep);
445 }
446 #else
447 union split_spte {
448         struct {
449                 u32 spte_low;
450                 u32 spte_high;
451         };
452         u64 spte;
453 };
454 
455 static void count_spte_clear(u64 *sptep, u64 spte)
456 {
457         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
458 
459         if (is_shadow_present_pte(spte))
460                 return;
461 
462         /* Ensure the spte is completely set before we increase the count */
463         smp_wmb();
464         sp->clear_spte_count++;
465 }
466 
467 static void __set_spte(u64 *sptep, u64 spte)
468 {
469         union split_spte *ssptep, sspte;
470 
471         ssptep = (union split_spte *)sptep;
472         sspte = (union split_spte)spte;
473 
474         ssptep->spte_high = sspte.spte_high;
475 
476         /*
477          * If we map the spte from nonpresent to present, We should store
478          * the high bits firstly, then set present bit, so cpu can not
479          * fetch this spte while we are setting the spte.
480          */
481         smp_wmb();
482 
483         WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
484 }
485 
486 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
487 {
488         union split_spte *ssptep, sspte;
489 
490         ssptep = (union split_spte *)sptep;
491         sspte = (union split_spte)spte;
492 
493         WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
494 
495         /*
496          * If we map the spte from present to nonpresent, we should clear
497          * present bit firstly to avoid vcpu fetch the old high bits.
498          */
499         smp_wmb();
500 
501         ssptep->spte_high = sspte.spte_high;
502         count_spte_clear(sptep, spte);
503 }
504 
505 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
506 {
507         union split_spte *ssptep, sspte, orig;
508 
509         ssptep = (union split_spte *)sptep;
510         sspte = (union split_spte)spte;
511 
512         /* xchg acts as a barrier before the setting of the high bits */
513         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
514         orig.spte_high = ssptep->spte_high;
515         ssptep->spte_high = sspte.spte_high;
516         count_spte_clear(sptep, spte);
517 
518         return orig.spte;
519 }
520 
521 /*
522  * The idea using the light way get the spte on x86_32 guest is from
523  * gup_get_pte(arch/x86/mm/gup.c).
524  *
525  * An spte tlb flush may be pending, because kvm_set_pte_rmapp
526  * coalesces them and we are running out of the MMU lock.  Therefore
527  * we need to protect against in-progress updates of the spte.
528  *
529  * Reading the spte while an update is in progress may get the old value
530  * for the high part of the spte.  The race is fine for a present->non-present
531  * change (because the high part of the spte is ignored for non-present spte),
532  * but for a present->present change we must reread the spte.
533  *
534  * All such changes are done in two steps (present->non-present and
535  * non-present->present), hence it is enough to count the number of
536  * present->non-present updates: if it changed while reading the spte,
537  * we might have hit the race.  This is done using clear_spte_count.
538  */
539 static u64 __get_spte_lockless(u64 *sptep)
540 {
541         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
542         union split_spte spte, *orig = (union split_spte *)sptep;
543         int count;
544 
545 retry:
546         count = sp->clear_spte_count;
547         smp_rmb();
548 
549         spte.spte_low = orig->spte_low;
550         smp_rmb();
551 
552         spte.spte_high = orig->spte_high;
553         smp_rmb();
554 
555         if (unlikely(spte.spte_low != orig->spte_low ||
556               count != sp->clear_spte_count))
557                 goto retry;
558 
559         return spte.spte;
560 }
561 #endif
562 
563 static bool spte_can_locklessly_be_made_writable(u64 spte)
564 {
565         return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
566                 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
567 }
568 
569 static bool spte_has_volatile_bits(u64 spte)
570 {
571         if (!is_shadow_present_pte(spte))
572                 return false;
573 
574         /*
575          * Always atomically update spte if it can be updated
576          * out of mmu-lock, it can ensure dirty bit is not lost,
577          * also, it can help us to get a stable is_writable_pte()
578          * to ensure tlb flush is not missed.
579          */
580         if (spte_can_locklessly_be_made_writable(spte) ||
581             is_access_track_spte(spte))
582                 return true;
583 
584         if (spte_ad_enabled(spte)) {
585                 if ((spte & shadow_accessed_mask) == 0 ||
586                     (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
587                         return true;
588         }
589 
590         return false;
591 }
592 
593 static bool is_accessed_spte(u64 spte)
594 {
595         u64 accessed_mask = spte_shadow_accessed_mask(spte);
596 
597         return accessed_mask ? spte & accessed_mask
598                              : !is_access_track_spte(spte);
599 }
600 
601 static bool is_dirty_spte(u64 spte)
602 {
603         u64 dirty_mask = spte_shadow_dirty_mask(spte);
604 
605         return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
606 }
607 
608 /* Rules for using mmu_spte_set:
609  * Set the sptep from nonpresent to present.
610  * Note: the sptep being assigned *must* be either not present
611  * or in a state where the hardware will not attempt to update
612  * the spte.
613  */
614 static void mmu_spte_set(u64 *sptep, u64 new_spte)
615 {
616         WARN_ON(is_shadow_present_pte(*sptep));
617         __set_spte(sptep, new_spte);
618 }
619 
620 /*
621  * Update the SPTE (excluding the PFN), but do not track changes in its
622  * accessed/dirty status.
623  */
624 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
625 {
626         u64 old_spte = *sptep;
627 
628         WARN_ON(!is_shadow_present_pte(new_spte));
629 
630         if (!is_shadow_present_pte(old_spte)) {
631                 mmu_spte_set(sptep, new_spte);
632                 return old_spte;
633         }
634 
635         if (!spte_has_volatile_bits(old_spte))
636                 __update_clear_spte_fast(sptep, new_spte);
637         else
638                 old_spte = __update_clear_spte_slow(sptep, new_spte);
639 
640         WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
641 
642         return old_spte;
643 }
644 
645 /* Rules for using mmu_spte_update:
646  * Update the state bits, it means the mapped pfn is not changed.
647  *
648  * Whenever we overwrite a writable spte with a read-only one we
649  * should flush remote TLBs. Otherwise rmap_write_protect
650  * will find a read-only spte, even though the writable spte
651  * might be cached on a CPU's TLB, the return value indicates this
652  * case.
653  *
654  * Returns true if the TLB needs to be flushed
655  */
656 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
657 {
658         bool flush = false;
659         u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
660 
661         if (!is_shadow_present_pte(old_spte))
662                 return false;
663 
664         /*
665          * For the spte updated out of mmu-lock is safe, since
666          * we always atomically update it, see the comments in
667          * spte_has_volatile_bits().
668          */
669         if (spte_can_locklessly_be_made_writable(old_spte) &&
670               !is_writable_pte(new_spte))
671                 flush = true;
672 
673         /*
674          * Flush TLB when accessed/dirty states are changed in the page tables,
675          * to guarantee consistency between TLB and page tables.
676          */
677 
678         if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
679                 flush = true;
680                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
681         }
682 
683         if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
684                 flush = true;
685                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
686         }
687 
688         return flush;
689 }
690 
691 /*
692  * Rules for using mmu_spte_clear_track_bits:
693  * It sets the sptep from present to nonpresent, and track the
694  * state bits, it is used to clear the last level sptep.
695  * Returns non-zero if the PTE was previously valid.
696  */
697 static int mmu_spte_clear_track_bits(u64 *sptep)
698 {
699         kvm_pfn_t pfn;
700         u64 old_spte = *sptep;
701 
702         if (!spte_has_volatile_bits(old_spte))
703                 __update_clear_spte_fast(sptep, 0ull);
704         else
705                 old_spte = __update_clear_spte_slow(sptep, 0ull);
706 
707         if (!is_shadow_present_pte(old_spte))
708                 return 0;
709 
710         pfn = spte_to_pfn(old_spte);
711 
712         /*
713          * KVM does not hold the refcount of the page used by
714          * kvm mmu, before reclaiming the page, we should
715          * unmap it from mmu first.
716          */
717         WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
718 
719         if (is_accessed_spte(old_spte))
720                 kvm_set_pfn_accessed(pfn);
721 
722         if (is_dirty_spte(old_spte))
723                 kvm_set_pfn_dirty(pfn);
724 
725         return 1;
726 }
727 
728 /*
729  * Rules for using mmu_spte_clear_no_track:
730  * Directly clear spte without caring the state bits of sptep,
731  * it is used to set the upper level spte.
732  */
733 static void mmu_spte_clear_no_track(u64 *sptep)
734 {
735         __update_clear_spte_fast(sptep, 0ull);
736 }
737 
738 static u64 mmu_spte_get_lockless(u64 *sptep)
739 {
740         return __get_spte_lockless(sptep);
741 }
742 
743 static u64 mark_spte_for_access_track(u64 spte)
744 {
745         if (spte_ad_enabled(spte))
746                 return spte & ~shadow_accessed_mask;
747 
748         if (is_access_track_spte(spte))
749                 return spte;
750 
751         /*
752          * Making an Access Tracking PTE will result in removal of write access
753          * from the PTE. So, verify that we will be able to restore the write
754          * access in the fast page fault path later on.
755          */
756         WARN_ONCE((spte & PT_WRITABLE_MASK) &&
757                   !spte_can_locklessly_be_made_writable(spte),
758                   "kvm: Writable SPTE is not locklessly dirty-trackable\n");
759 
760         WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
761                           shadow_acc_track_saved_bits_shift),
762                   "kvm: Access Tracking saved bit locations are not zero\n");
763 
764         spte |= (spte & shadow_acc_track_saved_bits_mask) <<
765                 shadow_acc_track_saved_bits_shift;
766         spte &= ~shadow_acc_track_mask;
767 
768         return spte;
769 }
770 
771 /* Restore an acc-track PTE back to a regular PTE */
772 static u64 restore_acc_track_spte(u64 spte)
773 {
774         u64 new_spte = spte;
775         u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
776                          & shadow_acc_track_saved_bits_mask;
777 
778         WARN_ON_ONCE(spte_ad_enabled(spte));
779         WARN_ON_ONCE(!is_access_track_spte(spte));
780 
781         new_spte &= ~shadow_acc_track_mask;
782         new_spte &= ~(shadow_acc_track_saved_bits_mask <<
783                       shadow_acc_track_saved_bits_shift);
784         new_spte |= saved_bits;
785 
786         return new_spte;
787 }
788 
789 /* Returns the Accessed status of the PTE and resets it at the same time. */
790 static bool mmu_spte_age(u64 *sptep)
791 {
792         u64 spte = mmu_spte_get_lockless(sptep);
793 
794         if (!is_accessed_spte(spte))
795                 return false;
796 
797         if (spte_ad_enabled(spte)) {
798                 clear_bit((ffs(shadow_accessed_mask) - 1),
799                           (unsigned long *)sptep);
800         } else {
801                 /*
802                  * Capture the dirty status of the page, so that it doesn't get
803                  * lost when the SPTE is marked for access tracking.
804                  */
805                 if (is_writable_pte(spte))
806                         kvm_set_pfn_dirty(spte_to_pfn(spte));
807 
808                 spte = mark_spte_for_access_track(spte);
809                 mmu_spte_update_no_track(sptep, spte);
810         }
811 
812         return true;
813 }
814 
815 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
816 {
817         /*
818          * Prevent page table teardown by making any free-er wait during
819          * kvm_flush_remote_tlbs() IPI to all active vcpus.
820          */
821         local_irq_disable();
822 
823         /*
824          * Make sure a following spte read is not reordered ahead of the write
825          * to vcpu->mode.
826          */
827         smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
828 }
829 
830 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
831 {
832         /*
833          * Make sure the write to vcpu->mode is not reordered in front of
834          * reads to sptes.  If it does, kvm_commit_zap_page() can see us
835          * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
836          */
837         smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
838         local_irq_enable();
839 }
840 
841 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
842                                   struct kmem_cache *base_cache, int min)
843 {
844         void *obj;
845 
846         if (cache->nobjs >= min)
847                 return 0;
848         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
849                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
850                 if (!obj)
851                         return -ENOMEM;
852                 cache->objects[cache->nobjs++] = obj;
853         }
854         return 0;
855 }
856 
857 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
858 {
859         return cache->nobjs;
860 }
861 
862 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
863                                   struct kmem_cache *cache)
864 {
865         while (mc->nobjs)
866                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
867 }
868 
869 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
870                                        int min)
871 {
872         void *page;
873 
874         if (cache->nobjs >= min)
875                 return 0;
876         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
877                 page = (void *)__get_free_page(GFP_KERNEL);
878                 if (!page)
879                         return -ENOMEM;
880                 cache->objects[cache->nobjs++] = page;
881         }
882         return 0;
883 }
884 
885 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
886 {
887         while (mc->nobjs)
888                 free_page((unsigned long)mc->objects[--mc->nobjs]);
889 }
890 
891 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
892 {
893         int r;
894 
895         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
896                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
897         if (r)
898                 goto out;
899         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
900         if (r)
901                 goto out;
902         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
903                                    mmu_page_header_cache, 4);
904 out:
905         return r;
906 }
907 
908 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
909 {
910         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
911                                 pte_list_desc_cache);
912         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
913         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
914                                 mmu_page_header_cache);
915 }
916 
917 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
918 {
919         void *p;
920 
921         BUG_ON(!mc->nobjs);
922         p = mc->objects[--mc->nobjs];
923         return p;
924 }
925 
926 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
927 {
928         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
929 }
930 
931 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
932 {
933         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
934 }
935 
936 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
937 {
938         if (!sp->role.direct)
939                 return sp->gfns[index];
940 
941         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
942 }
943 
944 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
945 {
946         if (sp->role.direct)
947                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
948         else
949                 sp->gfns[index] = gfn;
950 }
951 
952 /*
953  * Return the pointer to the large page information for a given gfn,
954  * handling slots that are not large page aligned.
955  */
956 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
957                                               struct kvm_memory_slot *slot,
958                                               int level)
959 {
960         unsigned long idx;
961 
962         idx = gfn_to_index(gfn, slot->base_gfn, level);
963         return &slot->arch.lpage_info[level - 2][idx];
964 }
965 
966 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
967                                             gfn_t gfn, int count)
968 {
969         struct kvm_lpage_info *linfo;
970         int i;
971 
972         for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
973                 linfo = lpage_info_slot(gfn, slot, i);
974                 linfo->disallow_lpage += count;
975                 WARN_ON(linfo->disallow_lpage < 0);
976         }
977 }
978 
979 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
980 {
981         update_gfn_disallow_lpage_count(slot, gfn, 1);
982 }
983 
984 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
985 {
986         update_gfn_disallow_lpage_count(slot, gfn, -1);
987 }
988 
989 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
990 {
991         struct kvm_memslots *slots;
992         struct kvm_memory_slot *slot;
993         gfn_t gfn;
994 
995         kvm->arch.indirect_shadow_pages++;
996         gfn = sp->gfn;
997         slots = kvm_memslots_for_spte_role(kvm, sp->role);
998         slot = __gfn_to_memslot(slots, gfn);
999 
1000         /* the non-leaf shadow pages are keeping readonly. */
1001         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1002                 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1003                                                     KVM_PAGE_TRACK_WRITE);
1004 
1005         kvm_mmu_gfn_disallow_lpage(slot, gfn);
1006 }
1007 
1008 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1009 {
1010         struct kvm_memslots *slots;
1011         struct kvm_memory_slot *slot;
1012         gfn_t gfn;
1013 
1014         kvm->arch.indirect_shadow_pages--;
1015         gfn = sp->gfn;
1016         slots = kvm_memslots_for_spte_role(kvm, sp->role);
1017         slot = __gfn_to_memslot(slots, gfn);
1018         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1019                 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1020                                                        KVM_PAGE_TRACK_WRITE);
1021 
1022         kvm_mmu_gfn_allow_lpage(slot, gfn);
1023 }
1024 
1025 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
1026                                           struct kvm_memory_slot *slot)
1027 {
1028         struct kvm_lpage_info *linfo;
1029 
1030         if (slot) {
1031                 linfo = lpage_info_slot(gfn, slot, level);
1032                 return !!linfo->disallow_lpage;
1033         }
1034 
1035         return true;
1036 }
1037 
1038 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1039                                         int level)
1040 {
1041         struct kvm_memory_slot *slot;
1042 
1043         slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1044         return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1045 }
1046 
1047 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1048 {
1049         unsigned long page_size;
1050         int i, ret = 0;
1051 
1052         page_size = kvm_host_page_size(kvm, gfn);
1053 
1054         for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1055                 if (page_size >= KVM_HPAGE_SIZE(i))
1056                         ret = i;
1057                 else
1058                         break;
1059         }
1060 
1061         return ret;
1062 }
1063 
1064 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1065                                           bool no_dirty_log)
1066 {
1067         if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1068                 return false;
1069         if (no_dirty_log && slot->dirty_bitmap)
1070                 return false;
1071 
1072         return true;
1073 }
1074 
1075 static struct kvm_memory_slot *
1076 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1077                             bool no_dirty_log)
1078 {
1079         struct kvm_memory_slot *slot;
1080 
1081         slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1082         if (!memslot_valid_for_gpte(slot, no_dirty_log))
1083                 slot = NULL;
1084 
1085         return slot;
1086 }
1087 
1088 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1089                          bool *force_pt_level)
1090 {
1091         int host_level, level, max_level;
1092         struct kvm_memory_slot *slot;
1093 
1094         if (unlikely(*force_pt_level))
1095                 return PT_PAGE_TABLE_LEVEL;
1096 
1097         slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1098         *force_pt_level = !memslot_valid_for_gpte(slot, true);
1099         if (unlikely(*force_pt_level))
1100                 return PT_PAGE_TABLE_LEVEL;
1101 
1102         host_level = host_mapping_level(vcpu->kvm, large_gfn);
1103 
1104         if (host_level == PT_PAGE_TABLE_LEVEL)
1105                 return host_level;
1106 
1107         max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1108 
1109         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
1110                 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
1111                         break;
1112 
1113         return level - 1;
1114 }
1115 
1116 /*
1117  * About rmap_head encoding:
1118  *
1119  * If the bit zero of rmap_head->val is clear, then it points to the only spte
1120  * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1121  * pte_list_desc containing more mappings.
1122  */
1123 
1124 /*
1125  * Returns the number of pointers in the rmap chain, not counting the new one.
1126  */
1127 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1128                         struct kvm_rmap_head *rmap_head)
1129 {
1130         struct pte_list_desc *desc;
1131         int i, count = 0;
1132 
1133         if (!rmap_head->val) {
1134                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1135                 rmap_head->val = (unsigned long)spte;
1136         } else if (!(rmap_head->val & 1)) {
1137                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1138                 desc = mmu_alloc_pte_list_desc(vcpu);
1139                 desc->sptes[0] = (u64 *)rmap_head->val;
1140                 desc->sptes[1] = spte;
1141                 rmap_head->val = (unsigned long)desc | 1;
1142                 ++count;
1143         } else {
1144                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1145                 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1146                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1147                         desc = desc->more;
1148                         count += PTE_LIST_EXT;
1149                 }
1150                 if (desc->sptes[PTE_LIST_EXT-1]) {
1151                         desc->more = mmu_alloc_pte_list_desc(vcpu);
1152                         desc = desc->more;
1153                 }
1154                 for (i = 0; desc->sptes[i]; ++i)
1155                         ++count;
1156                 desc->sptes[i] = spte;
1157         }
1158         return count;
1159 }
1160 
1161 static void
1162 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1163                            struct pte_list_desc *desc, int i,
1164                            struct pte_list_desc *prev_desc)
1165 {
1166         int j;
1167 
1168         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1169                 ;
1170         desc->sptes[i] = desc->sptes[j];
1171         desc->sptes[j] = NULL;
1172         if (j != 0)
1173                 return;
1174         if (!prev_desc && !desc->more)
1175                 rmap_head->val = (unsigned long)desc->sptes[0];
1176         else
1177                 if (prev_desc)
1178                         prev_desc->more = desc->more;
1179                 else
1180                         rmap_head->val = (unsigned long)desc->more | 1;
1181         mmu_free_pte_list_desc(desc);
1182 }
1183 
1184 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1185 {
1186         struct pte_list_desc *desc;
1187         struct pte_list_desc *prev_desc;
1188         int i;
1189 
1190         if (!rmap_head->val) {
1191                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1192                 BUG();
1193         } else if (!(rmap_head->val & 1)) {
1194                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
1195                 if ((u64 *)rmap_head->val != spte) {
1196                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
1197                         BUG();
1198                 }
1199                 rmap_head->val = 0;
1200         } else {
1201                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
1202                 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1203                 prev_desc = NULL;
1204                 while (desc) {
1205                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1206                                 if (desc->sptes[i] == spte) {
1207                                         pte_list_desc_remove_entry(rmap_head,
1208                                                         desc, i, prev_desc);
1209                                         return;
1210                                 }
1211                         }
1212                         prev_desc = desc;
1213                         desc = desc->more;
1214                 }
1215                 pr_err("pte_list_remove: %p many->many\n", spte);
1216                 BUG();
1217         }
1218 }
1219 
1220 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1221                                            struct kvm_memory_slot *slot)
1222 {
1223         unsigned long idx;
1224 
1225         idx = gfn_to_index(gfn, slot->base_gfn, level);
1226         return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1227 }
1228 
1229 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1230                                          struct kvm_mmu_page *sp)
1231 {
1232         struct kvm_memslots *slots;
1233         struct kvm_memory_slot *slot;
1234 
1235         slots = kvm_memslots_for_spte_role(kvm, sp->role);
1236         slot = __gfn_to_memslot(slots, gfn);
1237         return __gfn_to_rmap(gfn, sp->role.level, slot);
1238 }
1239 
1240 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1241 {
1242         struct kvm_mmu_memory_cache *cache;
1243 
1244         cache = &vcpu->arch.mmu_pte_list_desc_cache;
1245         return mmu_memory_cache_free_objects(cache);
1246 }
1247 
1248 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1249 {
1250         struct kvm_mmu_page *sp;
1251         struct kvm_rmap_head *rmap_head;
1252 
1253         sp = page_header(__pa(spte));
1254         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1255         rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1256         return pte_list_add(vcpu, spte, rmap_head);
1257 }
1258 
1259 static void rmap_remove(struct kvm *kvm, u64 *spte)
1260 {
1261         struct kvm_mmu_page *sp;
1262         gfn_t gfn;
1263         struct kvm_rmap_head *rmap_head;
1264 
1265         sp = page_header(__pa(spte));
1266         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1267         rmap_head = gfn_to_rmap(kvm, gfn, sp);
1268         pte_list_remove(spte, rmap_head);
1269 }
1270 
1271 /*
1272  * Used by the following functions to iterate through the sptes linked by a
1273  * rmap.  All fields are private and not assumed to be used outside.
1274  */
1275 struct rmap_iterator {
1276         /* private fields */
1277         struct pte_list_desc *desc;     /* holds the sptep if not NULL */
1278         int pos;                        /* index of the sptep */
1279 };
1280 
1281 /*
1282  * Iteration must be started by this function.  This should also be used after
1283  * removing/dropping sptes from the rmap link because in such cases the
1284  * information in the itererator may not be valid.
1285  *
1286  * Returns sptep if found, NULL otherwise.
1287  */
1288 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1289                            struct rmap_iterator *iter)
1290 {
1291         u64 *sptep;
1292 
1293         if (!rmap_head->val)
1294                 return NULL;
1295 
1296         if (!(rmap_head->val & 1)) {
1297                 iter->desc = NULL;
1298                 sptep = (u64 *)rmap_head->val;
1299                 goto out;
1300         }
1301 
1302         iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1303         iter->pos = 0;
1304         sptep = iter->desc->sptes[iter->pos];
1305 out:
1306         BUG_ON(!is_shadow_present_pte(*sptep));
1307         return sptep;
1308 }
1309 
1310 /*
1311  * Must be used with a valid iterator: e.g. after rmap_get_first().
1312  *
1313  * Returns sptep if found, NULL otherwise.
1314  */
1315 static u64 *rmap_get_next(struct rmap_iterator *iter)
1316 {
1317         u64 *sptep;
1318 
1319         if (iter->desc) {
1320                 if (iter->pos < PTE_LIST_EXT - 1) {
1321                         ++iter->pos;
1322                         sptep = iter->desc->sptes[iter->pos];
1323                         if (sptep)
1324                                 goto out;
1325                 }
1326 
1327                 iter->desc = iter->desc->more;
1328 
1329                 if (iter->desc) {
1330                         iter->pos = 0;
1331                         /* desc->sptes[0] cannot be NULL */
1332                         sptep = iter->desc->sptes[iter->pos];
1333                         goto out;
1334                 }
1335         }
1336 
1337         return NULL;
1338 out:
1339         BUG_ON(!is_shadow_present_pte(*sptep));
1340         return sptep;
1341 }
1342 
1343 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_)                 \
1344         for (_spte_ = rmap_get_first(_rmap_head_, _iter_);              \
1345              _spte_; _spte_ = rmap_get_next(_iter_))
1346 
1347 static void drop_spte(struct kvm *kvm, u64 *sptep)
1348 {
1349         if (mmu_spte_clear_track_bits(sptep))
1350                 rmap_remove(kvm, sptep);
1351 }
1352 
1353 
1354 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1355 {
1356         if (is_large_pte(*sptep)) {
1357                 WARN_ON(page_header(__pa(sptep))->role.level ==
1358                         PT_PAGE_TABLE_LEVEL);
1359                 drop_spte(kvm, sptep);
1360                 --kvm->stat.lpages;
1361                 return true;
1362         }
1363 
1364         return false;
1365 }
1366 
1367 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1368 {
1369         if (__drop_large_spte(vcpu->kvm, sptep))
1370                 kvm_flush_remote_tlbs(vcpu->kvm);
1371 }
1372 
1373 /*
1374  * Write-protect on the specified @sptep, @pt_protect indicates whether
1375  * spte write-protection is caused by protecting shadow page table.
1376  *
1377  * Note: write protection is difference between dirty logging and spte
1378  * protection:
1379  * - for dirty logging, the spte can be set to writable at anytime if
1380  *   its dirty bitmap is properly set.
1381  * - for spte protection, the spte can be writable only after unsync-ing
1382  *   shadow page.
1383  *
1384  * Return true if tlb need be flushed.
1385  */
1386 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1387 {
1388         u64 spte = *sptep;
1389 
1390         if (!is_writable_pte(spte) &&
1391               !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1392                 return false;
1393 
1394         rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1395 
1396         if (pt_protect)
1397                 spte &= ~SPTE_MMU_WRITEABLE;
1398         spte = spte & ~PT_WRITABLE_MASK;
1399 
1400         return mmu_spte_update(sptep, spte);
1401 }
1402 
1403 static bool __rmap_write_protect(struct kvm *kvm,
1404                                  struct kvm_rmap_head *rmap_head,
1405                                  bool pt_protect)
1406 {
1407         u64 *sptep;
1408         struct rmap_iterator iter;
1409         bool flush = false;
1410 
1411         for_each_rmap_spte(rmap_head, &iter, sptep)
1412                 flush |= spte_write_protect(sptep, pt_protect);
1413 
1414         return flush;
1415 }
1416 
1417 static bool spte_clear_dirty(u64 *sptep)
1418 {
1419         u64 spte = *sptep;
1420 
1421         rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1422 
1423         spte &= ~shadow_dirty_mask;
1424 
1425         return mmu_spte_update(sptep, spte);
1426 }
1427 
1428 static bool wrprot_ad_disabled_spte(u64 *sptep)
1429 {
1430         bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1431                                                (unsigned long *)sptep);
1432         if (was_writable)
1433                 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1434 
1435         return was_writable;
1436 }
1437 
1438 /*
1439  * Gets the GFN ready for another round of dirty logging by clearing the
1440  *      - D bit on ad-enabled SPTEs, and
1441  *      - W bit on ad-disabled SPTEs.
1442  * Returns true iff any D or W bits were cleared.
1443  */
1444 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1445 {
1446         u64 *sptep;
1447         struct rmap_iterator iter;
1448         bool flush = false;
1449 
1450         for_each_rmap_spte(rmap_head, &iter, sptep)
1451                 if (spte_ad_enabled(*sptep))
1452                         flush |= spte_clear_dirty(sptep);
1453                 else
1454                         flush |= wrprot_ad_disabled_spte(sptep);
1455 
1456         return flush;
1457 }
1458 
1459 static bool spte_set_dirty(u64 *sptep)
1460 {
1461         u64 spte = *sptep;
1462 
1463         rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1464 
1465         spte |= shadow_dirty_mask;
1466 
1467         return mmu_spte_update(sptep, spte);
1468 }
1469 
1470 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1471 {
1472         u64 *sptep;
1473         struct rmap_iterator iter;
1474         bool flush = false;
1475 
1476         for_each_rmap_spte(rmap_head, &iter, sptep)
1477                 if (spte_ad_enabled(*sptep))
1478                         flush |= spte_set_dirty(sptep);
1479 
1480         return flush;
1481 }
1482 
1483 /**
1484  * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1485  * @kvm: kvm instance
1486  * @slot: slot to protect
1487  * @gfn_offset: start of the BITS_PER_LONG pages we care about
1488  * @mask: indicates which pages we should protect
1489  *
1490  * Used when we do not need to care about huge page mappings: e.g. during dirty
1491  * logging we do not have any such mappings.
1492  */
1493 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1494                                      struct kvm_memory_slot *slot,
1495                                      gfn_t gfn_offset, unsigned long mask)
1496 {
1497         struct kvm_rmap_head *rmap_head;
1498 
1499         while (mask) {
1500                 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1501                                           PT_PAGE_TABLE_LEVEL, slot);
1502                 __rmap_write_protect(kvm, rmap_head, false);
1503 
1504                 /* clear the first set bit */
1505                 mask &= mask - 1;
1506         }
1507 }
1508 
1509 /**
1510  * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1511  * protect the page if the D-bit isn't supported.
1512  * @kvm: kvm instance
1513  * @slot: slot to clear D-bit
1514  * @gfn_offset: start of the BITS_PER_LONG pages we care about
1515  * @mask: indicates which pages we should clear D-bit
1516  *
1517  * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1518  */
1519 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1520                                      struct kvm_memory_slot *slot,
1521                                      gfn_t gfn_offset, unsigned long mask)
1522 {
1523         struct kvm_rmap_head *rmap_head;
1524 
1525         while (mask) {
1526                 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1527                                           PT_PAGE_TABLE_LEVEL, slot);
1528                 __rmap_clear_dirty(kvm, rmap_head);
1529 
1530                 /* clear the first set bit */
1531                 mask &= mask - 1;
1532         }
1533 }
1534 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1535 
1536 /**
1537  * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1538  * PT level pages.
1539  *
1540  * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1541  * enable dirty logging for them.
1542  *
1543  * Used when we do not need to care about huge page mappings: e.g. during dirty
1544  * logging we do not have any such mappings.
1545  */
1546 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1547                                 struct kvm_memory_slot *slot,
1548                                 gfn_t gfn_offset, unsigned long mask)
1549 {
1550         if (kvm_x86_ops->enable_log_dirty_pt_masked)
1551                 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1552                                 mask);
1553         else
1554                 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1555 }
1556 
1557 /**
1558  * kvm_arch_write_log_dirty - emulate dirty page logging
1559  * @vcpu: Guest mode vcpu
1560  *
1561  * Emulate arch specific page modification logging for the
1562  * nested hypervisor
1563  */
1564 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1565 {
1566         if (kvm_x86_ops->write_log_dirty)
1567                 return kvm_x86_ops->write_log_dirty(vcpu);
1568 
1569         return 0;
1570 }
1571 
1572 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1573                                     struct kvm_memory_slot *slot, u64 gfn)
1574 {
1575         struct kvm_rmap_head *rmap_head;
1576         int i;
1577         bool write_protected = false;
1578 
1579         for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1580                 rmap_head = __gfn_to_rmap(gfn, i, slot);
1581                 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1582         }
1583 
1584         return write_protected;
1585 }
1586 
1587 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1588 {
1589         struct kvm_memory_slot *slot;
1590 
1591         slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1592         return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1593 }
1594 
1595 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1596 {
1597         u64 *sptep;
1598         struct rmap_iterator iter;
1599         bool flush = false;
1600 
1601         while ((sptep = rmap_get_first(rmap_head, &iter))) {
1602                 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1603 
1604                 drop_spte(kvm, sptep);
1605                 flush = true;
1606         }
1607 
1608         return flush;
1609 }
1610 
1611 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1612                            struct kvm_memory_slot *slot, gfn_t gfn, int level,
1613                            unsigned long data)
1614 {
1615         return kvm_zap_rmapp(kvm, rmap_head);
1616 }
1617 
1618 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1619                              struct kvm_memory_slot *slot, gfn_t gfn, int level,
1620                              unsigned long data)
1621 {
1622         u64 *sptep;
1623         struct rmap_iterator iter;
1624         int need_flush = 0;
1625         u64 new_spte;
1626         pte_t *ptep = (pte_t *)data;
1627         kvm_pfn_t new_pfn;
1628 
1629         WARN_ON(pte_huge(*ptep));
1630         new_pfn = pte_pfn(*ptep);
1631 
1632 restart:
1633         for_each_rmap_spte(rmap_head, &iter, sptep) {
1634                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1635                             sptep, *sptep, gfn, level);
1636 
1637                 need_flush = 1;
1638 
1639                 if (pte_write(*ptep)) {
1640                         drop_spte(kvm, sptep);
1641                         goto restart;
1642                 } else {
1643                         new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1644                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1645 
1646                         new_spte &= ~PT_WRITABLE_MASK;
1647                         new_spte &= ~SPTE_HOST_WRITEABLE;
1648 
1649                         new_spte = mark_spte_for_access_track(new_spte);
1650 
1651                         mmu_spte_clear_track_bits(sptep);
1652                         mmu_spte_set(sptep, new_spte);
1653                 }
1654         }
1655 
1656         if (need_flush)
1657                 kvm_flush_remote_tlbs(kvm);
1658 
1659         return 0;
1660 }
1661 
1662 struct slot_rmap_walk_iterator {
1663         /* input fields. */
1664         struct kvm_memory_slot *slot;
1665         gfn_t start_gfn;
1666         gfn_t end_gfn;
1667         int start_level;
1668         int end_level;
1669 
1670         /* output fields. */
1671         gfn_t gfn;
1672         struct kvm_rmap_head *rmap;
1673         int level;
1674 
1675         /* private field. */
1676         struct kvm_rmap_head *end_rmap;
1677 };
1678 
1679 static void
1680 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1681 {
1682         iterator->level = level;
1683         iterator->gfn = iterator->start_gfn;
1684         iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1685         iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1686                                            iterator->slot);
1687 }
1688 
1689 static void
1690 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1691                     struct kvm_memory_slot *slot, int start_level,
1692                     int end_level, gfn_t start_gfn, gfn_t end_gfn)
1693 {
1694         iterator->slot = slot;
1695         iterator->start_level = start_level;
1696         iterator->end_level = end_level;
1697         iterator->start_gfn = start_gfn;
1698         iterator->end_gfn = end_gfn;
1699 
1700         rmap_walk_init_level(iterator, iterator->start_level);
1701 }
1702 
1703 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1704 {
1705         return !!iterator->rmap;
1706 }
1707 
1708 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1709 {
1710         if (++iterator->rmap <= iterator->end_rmap) {
1711                 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1712                 return;
1713         }
1714 
1715         if (++iterator->level > iterator->end_level) {
1716                 iterator->rmap = NULL;
1717                 return;
1718         }
1719 
1720         rmap_walk_init_level(iterator, iterator->level);
1721 }
1722 
1723 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_,    \
1724            _start_gfn, _end_gfn, _iter_)                                \
1725         for (slot_rmap_walk_init(_iter_, _slot_, _start_level_,         \
1726                                  _end_level_, _start_gfn, _end_gfn);    \
1727              slot_rmap_walk_okay(_iter_);                               \
1728              slot_rmap_walk_next(_iter_))
1729 
1730 static int kvm_handle_hva_range(struct kvm *kvm,
1731                                 unsigned long start,
1732                                 unsigned long end,
1733                                 unsigned long data,
1734                                 int (*handler)(struct kvm *kvm,
1735                                                struct kvm_rmap_head *rmap_head,
1736                                                struct kvm_memory_slot *slot,
1737                                                gfn_t gfn,
1738                                                int level,
1739                                                unsigned long data))
1740 {
1741         struct kvm_memslots *slots;
1742         struct kvm_memory_slot *memslot;
1743         struct slot_rmap_walk_iterator iterator;
1744         int ret = 0;
1745         int i;
1746 
1747         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1748                 slots = __kvm_memslots(kvm, i);
1749                 kvm_for_each_memslot(memslot, slots) {
1750                         unsigned long hva_start, hva_end;
1751                         gfn_t gfn_start, gfn_end;
1752 
1753                         hva_start = max(start, memslot->userspace_addr);
1754                         hva_end = min(end, memslot->userspace_addr +
1755                                       (memslot->npages << PAGE_SHIFT));
1756                         if (hva_start >= hva_end)
1757                                 continue;
1758                         /*
1759                          * {gfn(page) | page intersects with [hva_start, hva_end)} =
1760                          * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1761                          */
1762                         gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1763                         gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1764 
1765                         for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1766                                                  PT_MAX_HUGEPAGE_LEVEL,
1767                                                  gfn_start, gfn_end - 1,
1768                                                  &iterator)
1769                                 ret |= handler(kvm, iterator.rmap, memslot,
1770                                                iterator.gfn, iterator.level, data);
1771                 }
1772         }
1773 
1774         return ret;
1775 }
1776 
1777 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1778                           unsigned long data,
1779                           int (*handler)(struct kvm *kvm,
1780                                          struct kvm_rmap_head *rmap_head,
1781                                          struct kvm_memory_slot *slot,
1782                                          gfn_t gfn, int level,
1783                                          unsigned long data))
1784 {
1785         return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1786 }
1787 
1788 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1789 {
1790         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1791 }
1792 
1793 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1794 {
1795         return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1796 }
1797 
1798 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1799 {
1800         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1801 }
1802 
1803 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1804                          struct kvm_memory_slot *slot, gfn_t gfn, int level,
1805                          unsigned long data)
1806 {
1807         u64 *sptep;
1808         struct rmap_iterator uninitialized_var(iter);
1809         int young = 0;
1810 
1811         for_each_rmap_spte(rmap_head, &iter, sptep)
1812                 young |= mmu_spte_age(sptep);
1813 
1814         trace_kvm_age_page(gfn, level, slot, young);
1815         return young;
1816 }
1817 
1818 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1819                               struct kvm_memory_slot *slot, gfn_t gfn,
1820                               int level, unsigned long data)
1821 {
1822         u64 *sptep;
1823         struct rmap_iterator iter;
1824 
1825         for_each_rmap_spte(rmap_head, &iter, sptep)
1826                 if (is_accessed_spte(*sptep))
1827                         return 1;
1828         return 0;
1829 }
1830 
1831 #define RMAP_RECYCLE_THRESHOLD 1000
1832 
1833 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1834 {
1835         struct kvm_rmap_head *rmap_head;
1836         struct kvm_mmu_page *sp;
1837 
1838         sp = page_header(__pa(spte));
1839 
1840         rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1841 
1842         kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1843         kvm_flush_remote_tlbs(vcpu->kvm);
1844 }
1845 
1846 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1847 {
1848         return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1849 }
1850 
1851 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1852 {
1853         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1854 }
1855 
1856 #ifdef MMU_DEBUG
1857 static int is_empty_shadow_page(u64 *spt)
1858 {
1859         u64 *pos;
1860         u64 *end;
1861 
1862         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1863                 if (is_shadow_present_pte(*pos)) {
1864                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1865                                pos, *pos);
1866                         return 0;
1867                 }
1868         return 1;
1869 }
1870 #endif
1871 
1872 /*
1873  * This value is the sum of all of the kvm instances's
1874  * kvm->arch.n_used_mmu_pages values.  We need a global,
1875  * aggregate version in order to make the slab shrinker
1876  * faster
1877  */
1878 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1879 {
1880         kvm->arch.n_used_mmu_pages += nr;
1881         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1882 }
1883 
1884 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1885 {
1886         MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1887         hlist_del(&sp->hash_link);
1888         list_del(&sp->link);
1889         free_page((unsigned long)sp->spt);
1890         if (!sp->role.direct)
1891                 free_page((unsigned long)sp->gfns);
1892         kmem_cache_free(mmu_page_header_cache, sp);
1893 }
1894 
1895 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1896 {
1897         return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1898 }
1899 
1900 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1901                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1902 {
1903         if (!parent_pte)
1904                 return;
1905 
1906         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1907 }
1908 
1909 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1910                                        u64 *parent_pte)
1911 {
1912         pte_list_remove(parent_pte, &sp->parent_ptes);
1913 }
1914 
1915 static void drop_parent_pte(struct kvm_mmu_page *sp,
1916                             u64 *parent_pte)
1917 {
1918         mmu_page_remove_parent_pte(sp, parent_pte);
1919         mmu_spte_clear_no_track(parent_pte);
1920 }
1921 
1922 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1923 {
1924         struct kvm_mmu_page *sp;
1925 
1926         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1927         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1928         if (!direct)
1929                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1930         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1931 
1932         /*
1933          * The active_mmu_pages list is the FIFO list, do not move the
1934          * page until it is zapped. kvm_zap_obsolete_pages depends on
1935          * this feature. See the comments in kvm_zap_obsolete_pages().
1936          */
1937         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1938         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1939         return sp;
1940 }
1941 
1942 static void mark_unsync(u64 *spte);
1943 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1944 {
1945         u64 *sptep;
1946         struct rmap_iterator iter;
1947 
1948         for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1949                 mark_unsync(sptep);
1950         }
1951 }
1952 
1953 static void mark_unsync(u64 *spte)
1954 {
1955         struct kvm_mmu_page *sp;
1956         unsigned int index;
1957 
1958         sp = page_header(__pa(spte));
1959         index = spte - sp->spt;
1960         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1961                 return;
1962         if (sp->unsync_children++)
1963                 return;
1964         kvm_mmu_mark_parents_unsync(sp);
1965 }
1966 
1967 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1968                                struct kvm_mmu_page *sp)
1969 {
1970         return 0;
1971 }
1972 
1973 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1974 {
1975 }
1976 
1977 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1978                                  struct kvm_mmu_page *sp, u64 *spte,
1979                                  const void *pte)
1980 {
1981         WARN_ON(1);
1982 }
1983 
1984 #define KVM_PAGE_ARRAY_NR 16
1985 
1986 struct kvm_mmu_pages {
1987         struct mmu_page_and_offset {
1988                 struct kvm_mmu_page *sp;
1989                 unsigned int idx;
1990         } page[KVM_PAGE_ARRAY_NR];
1991         unsigned int nr;
1992 };
1993 
1994 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1995                          int idx)
1996 {
1997         int i;
1998 
1999         if (sp->unsync)
2000                 for (i=0; i < pvec->nr; i++)
2001                         if (pvec->page[i].sp == sp)
2002                                 return 0;
2003 
2004         pvec->page[pvec->nr].sp = sp;
2005         pvec->page[pvec->nr].idx = idx;
2006         pvec->nr++;
2007         return (pvec->nr == KVM_PAGE_ARRAY_NR);
2008 }
2009 
2010 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2011 {
2012         --sp->unsync_children;
2013         WARN_ON((int)sp->unsync_children < 0);
2014         __clear_bit(idx, sp->unsync_child_bitmap);
2015 }
2016 
2017 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2018                            struct kvm_mmu_pages *pvec)
2019 {
2020         int i, ret, nr_unsync_leaf = 0;
2021 
2022         for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2023                 struct kvm_mmu_page *child;
2024                 u64 ent = sp->spt[i];
2025 
2026                 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2027                         clear_unsync_child_bit(sp, i);
2028                         continue;
2029                 }
2030 
2031                 child = page_header(ent & PT64_BASE_ADDR_MASK);
2032 
2033                 if (child->unsync_children) {
2034                         if (mmu_pages_add(pvec, child, i))
2035                                 return -ENOSPC;
2036 
2037                         ret = __mmu_unsync_walk(child, pvec);
2038                         if (!ret) {
2039                                 clear_unsync_child_bit(sp, i);
2040                                 continue;
2041                         } else if (ret > 0) {
2042                                 nr_unsync_leaf += ret;
2043                         } else
2044                                 return ret;
2045                 } else if (child->unsync) {
2046                         nr_unsync_leaf++;
2047                         if (mmu_pages_add(pvec, child, i))
2048                                 return -ENOSPC;
2049                 } else
2050                         clear_unsync_child_bit(sp, i);
2051         }
2052 
2053         return nr_unsync_leaf;
2054 }
2055 
2056 #define INVALID_INDEX (-1)
2057 
2058 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2059                            struct kvm_mmu_pages *pvec)
2060 {
2061         pvec->nr = 0;
2062         if (!sp->unsync_children)
2063                 return 0;
2064 
2065         mmu_pages_add(pvec, sp, INVALID_INDEX);
2066         return __mmu_unsync_walk(sp, pvec);
2067 }
2068 
2069 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2070 {
2071         WARN_ON(!sp->unsync);
2072         trace_kvm_mmu_sync_page(sp);
2073         sp->unsync = 0;
2074         --kvm->stat.mmu_unsync;
2075 }
2076 
2077 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2078                                     struct list_head *invalid_list);
2079 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2080                                     struct list_head *invalid_list);
2081 
2082 /*
2083  * NOTE: we should pay more attention on the zapped-obsolete page
2084  * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2085  * since it has been deleted from active_mmu_pages but still can be found
2086  * at hast list.
2087  *
2088  * for_each_valid_sp() has skipped that kind of pages.
2089  */
2090 #define for_each_valid_sp(_kvm, _sp, _gfn)                              \
2091         hlist_for_each_entry(_sp,                                       \
2092           &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2093                 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) {    \
2094                 } else
2095 
2096 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn)                 \
2097         for_each_valid_sp(_kvm, _sp, _gfn)                              \
2098                 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2099 
2100 /* @sp->gfn should be write-protected at the call site */
2101 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2102                             struct list_head *invalid_list)
2103 {
2104         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
2105                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2106                 return false;
2107         }
2108 
2109         if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
2110                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2111                 return false;
2112         }
2113 
2114         return true;
2115 }
2116 
2117 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2118                                  struct list_head *invalid_list,
2119                                  bool remote_flush, bool local_flush)
2120 {
2121         if (!list_empty(invalid_list)) {
2122                 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
2123                 return;
2124         }
2125 
2126         if (remote_flush)
2127                 kvm_flush_remote_tlbs(vcpu->kvm);
2128         else if (local_flush)
2129                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2130 }
2131 
2132 #ifdef CONFIG_KVM_MMU_AUDIT
2133 #include "mmu_audit.c"
2134 #else
2135 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2136 static void mmu_audit_disable(void) { }
2137 #endif
2138 
2139 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2140 {
2141         return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2142 }
2143 
2144 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2145                          struct list_head *invalid_list)
2146 {
2147         kvm_unlink_unsync_page(vcpu->kvm, sp);
2148         return __kvm_sync_page(vcpu, sp, invalid_list);
2149 }
2150 
2151 /* @gfn should be write-protected at the call site */
2152 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2153                            struct list_head *invalid_list)
2154 {
2155         struct kvm_mmu_page *s;
2156         bool ret = false;
2157 
2158         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2159                 if (!s->unsync)
2160                         continue;
2161 
2162                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2163                 ret |= kvm_sync_page(vcpu, s, invalid_list);
2164         }
2165 
2166         return ret;
2167 }
2168 
2169 struct mmu_page_path {
2170         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL];
2171         unsigned int idx[PT64_ROOT_LEVEL];
2172 };
2173 
2174 #define for_each_sp(pvec, sp, parents, i)                       \
2175                 for (i = mmu_pages_first(&pvec, &parents);      \
2176                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
2177                         i = mmu_pages_next(&pvec, &parents, i))
2178 
2179 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2180                           struct mmu_page_path *parents,
2181                           int i)
2182 {
2183         int n;
2184 
2185         for (n = i+1; n < pvec->nr; n++) {
2186                 struct kvm_mmu_page *sp = pvec->page[n].sp;
2187                 unsigned idx = pvec->page[n].idx;
2188                 int level = sp->role.level;
2189 
2190                 parents->idx[level-1] = idx;
2191                 if (level == PT_PAGE_TABLE_LEVEL)
2192                         break;
2193 
2194                 parents->parent[level-2] = sp;
2195         }
2196 
2197         return n;
2198 }
2199 
2200 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2201                            struct mmu_page_path *parents)
2202 {
2203         struct kvm_mmu_page *sp;
2204         int level;
2205 
2206         if (pvec->nr == 0)
2207                 return 0;
2208 
2209         WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2210 
2211         sp = pvec->page[0].sp;
2212         level = sp->role.level;
2213         WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2214 
2215         parents->parent[level-2] = sp;
2216 
2217         /* Also set up a sentinel.  Further entries in pvec are all
2218          * children of sp, so this element is never overwritten.
2219          */
2220         parents->parent[level-1] = NULL;
2221         return mmu_pages_next(pvec, parents, 0);
2222 }
2223 
2224 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2225 {
2226         struct kvm_mmu_page *sp;
2227         unsigned int level = 0;
2228 
2229         do {
2230                 unsigned int idx = parents->idx[level];
2231                 sp = parents->parent[level];
2232                 if (!sp)
2233                         return;
2234 
2235                 WARN_ON(idx == INVALID_INDEX);
2236                 clear_unsync_child_bit(sp, idx);
2237                 level++;
2238         } while (!sp->unsync_children);
2239 }
2240 
2241 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2242                               struct kvm_mmu_page *parent)
2243 {
2244         int i;
2245         struct kvm_mmu_page *sp;
2246         struct mmu_page_path parents;
2247         struct kvm_mmu_pages pages;
2248         LIST_HEAD(invalid_list);
2249         bool flush = false;
2250 
2251         while (mmu_unsync_walk(parent, &pages)) {
2252                 bool protected = false;
2253 
2254                 for_each_sp(pages, sp, parents, i)
2255                         protected |= rmap_write_protect(vcpu, sp->gfn);
2256 
2257                 if (protected) {
2258                         kvm_flush_remote_tlbs(vcpu->kvm);
2259                         flush = false;
2260                 }
2261 
2262                 for_each_sp(pages, sp, parents, i) {
2263                         flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2264                         mmu_pages_clear_parents(&parents);
2265                 }
2266                 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2267                         kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2268                         cond_resched_lock(&vcpu->kvm->mmu_lock);
2269                         flush = false;
2270                 }
2271         }
2272 
2273         kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2274 }
2275 
2276 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2277 {
2278         atomic_set(&sp->write_flooding_count,  0);
2279 }
2280 
2281 static void clear_sp_write_flooding_count(u64 *spte)
2282 {
2283         struct kvm_mmu_page *sp =  page_header(__pa(spte));
2284 
2285         __clear_sp_write_flooding_count(sp);
2286 }
2287 
2288 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2289                                              gfn_t gfn,
2290                                              gva_t gaddr,
2291                                              unsigned level,
2292                                              int direct,
2293                                              unsigned access)
2294 {
2295         union kvm_mmu_page_role role;
2296         unsigned quadrant;
2297         struct kvm_mmu_page *sp;
2298         bool need_sync = false;
2299         bool flush = false;
2300         int collisions = 0;
2301         LIST_HEAD(invalid_list);
2302 
2303         role = vcpu->arch.mmu.base_role;
2304         role.level = level;
2305         role.direct = direct;
2306         if (role.direct)
2307                 role.cr4_pae = 0;
2308         role.access = access;
2309         if (!vcpu->arch.mmu.direct_map
2310             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2311                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2312                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2313                 role.quadrant = quadrant;
2314         }
2315         for_each_valid_sp(vcpu->kvm, sp, gfn) {
2316                 if (sp->gfn != gfn) {
2317                         collisions++;
2318                         continue;
2319                 }
2320 
2321                 if (!need_sync && sp->unsync)
2322                         need_sync = true;
2323 
2324                 if (sp->role.word != role.word)
2325                         continue;
2326 
2327                 if (sp->unsync) {
2328                         /* The page is good, but __kvm_sync_page might still end
2329                          * up zapping it.  If so, break in order to rebuild it.
2330                          */
2331                         if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2332                                 break;
2333 
2334                         WARN_ON(!list_empty(&invalid_list));
2335                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2336                 }
2337 
2338                 if (sp->unsync_children)
2339                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2340 
2341                 __clear_sp_write_flooding_count(sp);
2342                 trace_kvm_mmu_get_page(sp, false);
2343                 goto out;
2344         }
2345 
2346         ++vcpu->kvm->stat.mmu_cache_miss;
2347 
2348         sp = kvm_mmu_alloc_page(vcpu, direct);
2349 
2350         sp->gfn = gfn;
2351         sp->role = role;
2352         hlist_add_head(&sp->hash_link,
2353                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2354         if (!direct) {
2355                 /*
2356                  * we should do write protection before syncing pages
2357                  * otherwise the content of the synced shadow page may
2358                  * be inconsistent with guest page table.
2359                  */
2360                 account_shadowed(vcpu->kvm, sp);
2361                 if (level == PT_PAGE_TABLE_LEVEL &&
2362                       rmap_write_protect(vcpu, gfn))
2363                         kvm_flush_remote_tlbs(vcpu->kvm);
2364 
2365                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2366                         flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2367         }
2368         sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2369         clear_page(sp->spt);
2370         trace_kvm_mmu_get_page(sp, true);
2371 
2372         kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2373 out:
2374         if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2375                 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2376         return sp;
2377 }
2378 
2379 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2380                              struct kvm_vcpu *vcpu, u64 addr)
2381 {
2382         iterator->addr = addr;
2383         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2384         iterator->level = vcpu->arch.mmu.shadow_root_level;
2385 
2386         if (iterator->level == PT64_ROOT_LEVEL &&
2387             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2388             !vcpu->arch.mmu.direct_map)
2389                 --iterator->level;
2390 
2391         if (iterator->level == PT32E_ROOT_LEVEL) {
2392                 iterator->shadow_addr
2393                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2394                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2395                 --iterator->level;
2396                 if (!iterator->shadow_addr)
2397                         iterator->level = 0;
2398         }
2399 }
2400 
2401 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2402 {
2403         if (iterator->level < PT_PAGE_TABLE_LEVEL)
2404                 return false;
2405 
2406         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2407         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2408         return true;
2409 }
2410 
2411 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2412                                u64 spte)
2413 {
2414         if (is_last_spte(spte, iterator->level)) {
2415                 iterator->level = 0;
2416                 return;
2417         }
2418 
2419         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2420         --iterator->level;
2421 }
2422 
2423 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2424 {
2425         return __shadow_walk_next(iterator, *iterator->sptep);
2426 }
2427 
2428 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2429                              struct kvm_mmu_page *sp)
2430 {
2431         u64 spte;
2432 
2433         BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2434 
2435         spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2436                shadow_user_mask | shadow_x_mask;
2437 
2438         if (sp_ad_disabled(sp))
2439                 spte |= shadow_acc_track_value;
2440         else
2441                 spte |= shadow_accessed_mask;
2442 
2443         mmu_spte_set(sptep, spte);
2444 
2445         mmu_page_add_parent_pte(vcpu, sp, sptep);
2446 
2447         if (sp->unsync_children || sp->unsync)
2448                 mark_unsync(sptep);
2449 }
2450 
2451 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2452                                    unsigned direct_access)
2453 {
2454         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2455                 struct kvm_mmu_page *child;
2456 
2457                 /*
2458                  * For the direct sp, if the guest pte's dirty bit
2459                  * changed form clean to dirty, it will corrupt the
2460                  * sp's access: allow writable in the read-only sp,
2461                  * so we should update the spte at this point to get
2462                  * a new sp with the correct access.
2463                  */
2464                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2465                 if (child->role.access == direct_access)
2466                         return;
2467 
2468                 drop_parent_pte(child, sptep);
2469                 kvm_flush_remote_tlbs(vcpu->kvm);
2470         }
2471 }
2472 
2473 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2474                              u64 *spte)
2475 {
2476         u64 pte;
2477         struct kvm_mmu_page *child;
2478 
2479         pte = *spte;
2480         if (is_shadow_present_pte(pte)) {
2481                 if (is_last_spte(pte, sp->role.level)) {
2482                         drop_spte(kvm, spte);
2483                         if (is_large_pte(pte))
2484                                 --kvm->stat.lpages;
2485                 } else {
2486                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2487                         drop_parent_pte(child, spte);
2488                 }
2489                 return true;
2490         }
2491 
2492         if (is_mmio_spte(pte))
2493                 mmu_spte_clear_no_track(spte);
2494 
2495         return false;
2496 }
2497 
2498 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2499                                          struct kvm_mmu_page *sp)
2500 {
2501         unsigned i;
2502 
2503         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2504                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2505 }
2506 
2507 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2508 {
2509         u64 *sptep;
2510         struct rmap_iterator iter;
2511 
2512         while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2513                 drop_parent_pte(sp, sptep);
2514 }
2515 
2516 static int mmu_zap_unsync_children(struct kvm *kvm,
2517                                    struct kvm_mmu_page *parent,
2518                                    struct list_head *invalid_list)
2519 {
2520         int i, zapped = 0;
2521         struct mmu_page_path parents;
2522         struct kvm_mmu_pages pages;
2523 
2524         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2525                 return 0;
2526 
2527         while (mmu_unsync_walk(parent, &pages)) {
2528                 struct kvm_mmu_page *sp;
2529 
2530                 for_each_sp(pages, sp, parents, i) {
2531                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2532                         mmu_pages_clear_parents(&parents);
2533                         zapped++;
2534                 }
2535         }
2536 
2537         return zapped;
2538 }
2539 
2540 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2541                                     struct list_head *invalid_list)
2542 {
2543         int ret;
2544 
2545         trace_kvm_mmu_prepare_zap_page(sp);
2546         ++kvm->stat.mmu_shadow_zapped;
2547         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2548         kvm_mmu_page_unlink_children(kvm, sp);
2549         kvm_mmu_unlink_parents(kvm, sp);
2550 
2551         if (!sp->role.invalid && !sp->role.direct)
2552                 unaccount_shadowed(kvm, sp);
2553 
2554         if (sp->unsync)
2555                 kvm_unlink_unsync_page(kvm, sp);
2556         if (!sp->root_count) {
2557                 /* Count self */
2558                 ret++;
2559                 list_move(&sp->link, invalid_list);
2560                 kvm_mod_used_mmu_pages(kvm, -1);
2561         } else {
2562                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2563 
2564                 /*
2565                  * The obsolete pages can not be used on any vcpus.
2566                  * See the comments in kvm_mmu_invalidate_zap_all_pages().
2567                  */
2568                 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2569                         kvm_reload_remote_mmus(kvm);
2570         }
2571 
2572         sp->role.invalid = 1;
2573         return ret;
2574 }
2575 
2576 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2577                                     struct list_head *invalid_list)
2578 {
2579         struct kvm_mmu_page *sp, *nsp;
2580 
2581         if (list_empty(invalid_list))
2582                 return;
2583 
2584         /*
2585          * We need to make sure everyone sees our modifications to
2586          * the page tables and see changes to vcpu->mode here. The barrier
2587          * in the kvm_flush_remote_tlbs() achieves this. This pairs
2588          * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2589          *
2590          * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2591          * guest mode and/or lockless shadow page table walks.
2592          */
2593         kvm_flush_remote_tlbs(kvm);
2594 
2595         list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2596                 WARN_ON(!sp->role.invalid || sp->root_count);
2597                 kvm_mmu_free_page(sp);
2598         }
2599 }
2600 
2601 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2602                                         struct list_head *invalid_list)
2603 {
2604         struct kvm_mmu_page *sp;
2605 
2606         if (list_empty(&kvm->arch.active_mmu_pages))
2607                 return false;
2608 
2609         sp = list_last_entry(&kvm->arch.active_mmu_pages,
2610                              struct kvm_mmu_page, link);
2611         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2612 
2613         return true;
2614 }
2615 
2616 /*
2617  * Changing the number of mmu pages allocated to the vm
2618  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2619  */
2620 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2621 {
2622         LIST_HEAD(invalid_list);
2623 
2624         spin_lock(&kvm->mmu_lock);
2625 
2626         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2627                 /* Need to free some mmu pages to achieve the goal. */
2628                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2629                         if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2630                                 break;
2631 
2632                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2633                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2634         }
2635 
2636         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2637 
2638         spin_unlock(&kvm->mmu_lock);
2639 }
2640 
2641 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2642 {
2643         struct kvm_mmu_page *sp;
2644         LIST_HEAD(invalid_list);
2645         int r;
2646 
2647         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2648         r = 0;
2649         spin_lock(&kvm->mmu_lock);
2650         for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2651                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2652                          sp->role.word);
2653                 r = 1;
2654                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2655         }
2656         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2657         spin_unlock(&kvm->mmu_lock);
2658 
2659         return r;
2660 }
2661 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2662 
2663 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2664 {
2665         trace_kvm_mmu_unsync_page(sp);
2666         ++vcpu->kvm->stat.mmu_unsync;
2667         sp->unsync = 1;
2668 
2669         kvm_mmu_mark_parents_unsync(sp);
2670 }
2671 
2672 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2673                                    bool can_unsync)
2674 {
2675         struct kvm_mmu_page *sp;
2676 
2677         if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2678                 return true;
2679 
2680         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2681                 if (!can_unsync)
2682                         return true;
2683 
2684                 if (sp->unsync)
2685                         continue;
2686 
2687                 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2688                 kvm_unsync_page(vcpu, sp);
2689         }
2690 
2691         return false;
2692 }
2693 
2694 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2695 {
2696         if (pfn_valid(pfn))
2697                 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2698 
2699         return true;
2700 }
2701 
2702 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2703                     unsigned pte_access, int level,
2704                     gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2705                     bool can_unsync, bool host_writable)
2706 {
2707         u64 spte = 0;
2708         int ret = 0;
2709         struct kvm_mmu_page *sp;
2710 
2711         if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2712                 return 0;
2713 
2714         sp = page_header(__pa(sptep));
2715         if (sp_ad_disabled(sp))
2716                 spte |= shadow_acc_track_value;
2717 
2718         /*
2719          * For the EPT case, shadow_present_mask is 0 if hardware
2720          * supports exec-only page table entries.  In that case,
2721          * ACC_USER_MASK and shadow_user_mask are used to represent
2722          * read access.  See FNAME(gpte_access) in paging_tmpl.h.
2723          */
2724         spte |= shadow_present_mask;
2725         if (!speculative)
2726                 spte |= spte_shadow_accessed_mask(spte);
2727 
2728         if (pte_access & ACC_EXEC_MASK)
2729                 spte |= shadow_x_mask;
2730         else
2731                 spte |= shadow_nx_mask;
2732 
2733         if (pte_access & ACC_USER_MASK)
2734                 spte |= shadow_user_mask;
2735 
2736         if (level > PT_PAGE_TABLE_LEVEL)
2737                 spte |= PT_PAGE_SIZE_MASK;
2738         if (tdp_enabled)
2739                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2740                         kvm_is_mmio_pfn(pfn));
2741 
2742         if (host_writable)
2743                 spte |= SPTE_HOST_WRITEABLE;
2744         else
2745                 pte_access &= ~ACC_WRITE_MASK;
2746 
2747         spte |= (u64)pfn << PAGE_SHIFT;
2748 
2749         if (pte_access & ACC_WRITE_MASK) {
2750 
2751                 /*
2752                  * Other vcpu creates new sp in the window between
2753                  * mapping_level() and acquiring mmu-lock. We can
2754                  * allow guest to retry the access, the mapping can
2755                  * be fixed if guest refault.
2756                  */
2757                 if (level > PT_PAGE_TABLE_LEVEL &&
2758                     mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2759                         goto done;
2760 
2761                 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2762 
2763                 /*
2764                  * Optimization: for pte sync, if spte was writable the hash
2765                  * lookup is unnecessary (and expensive). Write protection
2766                  * is responsibility of mmu_get_page / kvm_sync_page.
2767                  * Same reasoning can be applied to dirty page accounting.
2768                  */
2769                 if (!can_unsync && is_writable_pte(*sptep))
2770                         goto set_pte;
2771 
2772                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2773                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2774                                  __func__, gfn);
2775                         ret = 1;
2776                         pte_access &= ~ACC_WRITE_MASK;
2777                         spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2778                 }
2779         }
2780 
2781         if (pte_access & ACC_WRITE_MASK) {
2782                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2783                 spte |= spte_shadow_dirty_mask(spte);
2784         }
2785 
2786         if (speculative)
2787                 spte = mark_spte_for_access_track(spte);
2788 
2789 set_pte:
2790         if (mmu_spte_update(sptep, spte))
2791                 kvm_flush_remote_tlbs(vcpu->kvm);
2792 done:
2793         return ret;
2794 }
2795 
2796 static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2797                          int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2798                          bool speculative, bool host_writable)
2799 {
2800         int was_rmapped = 0;
2801         int rmap_count;
2802         bool emulate = false;
2803 
2804         pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2805                  *sptep, write_fault, gfn);
2806 
2807         if (is_shadow_present_pte(*sptep)) {
2808                 /*
2809                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2810                  * the parent of the now unreachable PTE.
2811                  */
2812                 if (level > PT_PAGE_TABLE_LEVEL &&
2813                     !is_large_pte(*sptep)) {
2814                         struct kvm_mmu_page *child;
2815                         u64 pte = *sptep;
2816 
2817                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2818                         drop_parent_pte(child, sptep);
2819                         kvm_flush_remote_tlbs(vcpu->kvm);
2820                 } else if (pfn != spte_to_pfn(*sptep)) {
2821                         pgprintk("hfn old %llx new %llx\n",
2822                                  spte_to_pfn(*sptep), pfn);
2823                         drop_spte(vcpu->kvm, sptep);
2824                         kvm_flush_remote_tlbs(vcpu->kvm);
2825                 } else
2826                         was_rmapped = 1;
2827         }
2828 
2829         if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2830               true, host_writable)) {
2831                 if (write_fault)
2832                         emulate = true;
2833                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2834         }
2835 
2836         if (unlikely(is_mmio_spte(*sptep)))
2837                 emulate = true;
2838 
2839         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2840         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2841                  is_large_pte(*sptep)? "2MB" : "4kB",
2842                  *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn,
2843                  *sptep, sptep);
2844         if (!was_rmapped && is_large_pte(*sptep))
2845                 ++vcpu->kvm->stat.lpages;
2846 
2847         if (is_shadow_present_pte(*sptep)) {
2848                 if (!was_rmapped) {
2849                         rmap_count = rmap_add(vcpu, sptep, gfn);
2850                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2851                                 rmap_recycle(vcpu, sptep, gfn);
2852                 }
2853         }
2854 
2855         kvm_release_pfn_clean(pfn);
2856 
2857         return emulate;
2858 }
2859 
2860 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2861                                      bool no_dirty_log)
2862 {
2863         struct kvm_memory_slot *slot;
2864 
2865         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2866         if (!slot)
2867                 return KVM_PFN_ERR_FAULT;
2868 
2869         return gfn_to_pfn_memslot_atomic(slot, gfn);
2870 }
2871 
2872 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2873                                     struct kvm_mmu_page *sp,
2874                                     u64 *start, u64 *end)
2875 {
2876         struct page *pages[PTE_PREFETCH_NUM];
2877         struct kvm_memory_slot *slot;
2878         unsigned access = sp->role.access;
2879         int i, ret;
2880         gfn_t gfn;
2881 
2882         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2883         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2884         if (!slot)
2885                 return -1;
2886 
2887         ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2888         if (ret <= 0)
2889                 return -1;
2890 
2891         for (i = 0; i < ret; i++, gfn++, start++)
2892                 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2893                              page_to_pfn(pages[i]), true, true);
2894 
2895         return 0;
2896 }
2897 
2898 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2899                                   struct kvm_mmu_page *sp, u64 *sptep)
2900 {
2901         u64 *spte, *start = NULL;
2902         int i;
2903 
2904         WARN_ON(!sp->role.direct);
2905 
2906         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2907         spte = sp->spt + i;
2908 
2909         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2910                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2911                         if (!start)
2912                                 continue;
2913                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2914                                 break;
2915                         start = NULL;
2916                 } else if (!start)
2917                         start = spte;
2918         }
2919 }
2920 
2921 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2922 {
2923         struct kvm_mmu_page *sp;
2924 
2925         sp = page_header(__pa(sptep));
2926 
2927         /*
2928          * Without accessed bits, there's no way to distinguish between
2929          * actually accessed translations and prefetched, so disable pte
2930          * prefetch if accessed bits aren't available.
2931          */
2932         if (sp_ad_disabled(sp))
2933                 return;
2934 
2935         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2936                 return;
2937 
2938         __direct_pte_prefetch(vcpu, sp, sptep);
2939 }
2940 
2941 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2942                         int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2943 {
2944         struct kvm_shadow_walk_iterator iterator;
2945         struct kvm_mmu_page *sp;
2946         int emulate = 0;
2947         gfn_t pseudo_gfn;
2948 
2949         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2950                 return 0;
2951 
2952         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2953                 if (iterator.level == level) {
2954                         emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2955                                                write, level, gfn, pfn, prefault,
2956                                                map_writable);
2957                         direct_pte_prefetch(vcpu, iterator.sptep);
2958                         ++vcpu->stat.pf_fixed;
2959                         break;
2960                 }
2961 
2962                 drop_large_spte(vcpu, iterator.sptep);
2963                 if (!is_shadow_present_pte(*iterator.sptep)) {
2964                         u64 base_addr = iterator.addr;
2965 
2966                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2967                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2968                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2969                                               iterator.level - 1, 1, ACC_ALL);
2970 
2971                         link_shadow_page(vcpu, iterator.sptep, sp);
2972                 }
2973         }
2974         return emulate;
2975 }
2976 
2977 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2978 {
2979         siginfo_t info;
2980 
2981         info.si_signo   = SIGBUS;
2982         info.si_errno   = 0;
2983         info.si_code    = BUS_MCEERR_AR;
2984         info.si_addr    = (void __user *)address;
2985         info.si_addr_lsb = PAGE_SHIFT;
2986 
2987         send_sig_info(SIGBUS, &info, tsk);
2988 }
2989 
2990 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2991 {
2992         /*
2993          * Do not cache the mmio info caused by writing the readonly gfn
2994          * into the spte otherwise read access on readonly gfn also can
2995          * caused mmio page fault and treat it as mmio access.
2996          * Return 1 to tell kvm to emulate it.
2997          */
2998         if (pfn == KVM_PFN_ERR_RO_FAULT)
2999                 return 1;
3000 
3001         if (pfn == KVM_PFN_ERR_HWPOISON) {
3002                 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3003                 return 0;
3004         }
3005 
3006         return -EFAULT;
3007 }
3008 
3009 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
3010                                         gfn_t *gfnp, kvm_pfn_t *pfnp,
3011                                         int *levelp)
3012 {
3013         kvm_pfn_t pfn = *pfnp;
3014         gfn_t gfn = *gfnp;
3015         int level = *levelp;
3016 
3017         /*
3018          * Check if it's a transparent hugepage. If this would be an
3019          * hugetlbfs page, level wouldn't be set to
3020          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3021          * here.
3022          */
3023         if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
3024             level == PT_PAGE_TABLE_LEVEL &&
3025             PageTransCompoundMap(pfn_to_page(pfn)) &&
3026             !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
3027                 unsigned long mask;
3028                 /*
3029                  * mmu_notifier_retry was successful and we hold the
3030                  * mmu_lock here, so the pmd can't become splitting
3031                  * from under us, and in turn
3032                  * __split_huge_page_refcount() can't run from under
3033                  * us and we can safely transfer the refcount from
3034                  * PG_tail to PG_head as we switch the pfn to tail to
3035                  * head.
3036                  */
3037                 *levelp = level = PT_DIRECTORY_LEVEL;
3038                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3039                 VM_BUG_ON((gfn & mask) != (pfn & mask));
3040                 if (pfn & mask) {
3041                         gfn &= ~mask;
3042                         *gfnp = gfn;
3043                         kvm_release_pfn_clean(pfn);
3044                         pfn &= ~mask;
3045                         kvm_get_pfn(pfn);
3046                         *pfnp = pfn;
3047                 }
3048         }
3049 }
3050 
3051 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3052                                 kvm_pfn_t pfn, unsigned access, int *ret_val)
3053 {
3054         /* The pfn is invalid, report the error! */
3055         if (unlikely(is_error_pfn(pfn))) {
3056                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3057                 return true;
3058         }
3059 
3060         if (unlikely(is_noslot_pfn(pfn)))
3061                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
3062 
3063         return false;
3064 }
3065 
3066 static bool page_fault_can_be_fast(u32 error_code)
3067 {
3068         /*
3069          * Do not fix the mmio spte with invalid generation number which
3070          * need to be updated by slow page fault path.
3071          */
3072         if (unlikely(error_code & PFERR_RSVD_MASK))
3073                 return false;
3074 
3075         /* See if the page fault is due to an NX violation */
3076         if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3077                       == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3078                 return false;
3079 
3080         /*
3081          * #PF can be fast if:
3082          * 1. The shadow page table entry is not present, which could mean that
3083          *    the fault is potentially caused by access tracking (if enabled).
3084          * 2. The shadow page table entry is present and the fault
3085          *    is caused by write-protect, that means we just need change the W
3086          *    bit of the spte which can be done out of mmu-lock.
3087          *
3088          * However, if access tracking is disabled we know that a non-present
3089          * page must be a genuine page fault where we have to create a new SPTE.
3090          * So, if access tracking is disabled, we return true only for write
3091          * accesses to a present page.
3092          */
3093 
3094         return shadow_acc_track_mask != 0 ||
3095                ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3096                 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3097 }
3098 
3099 /*
3100  * Returns true if the SPTE was fixed successfully. Otherwise,
3101  * someone else modified the SPTE from its original value.
3102  */
3103 static bool
3104 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3105                         u64 *sptep, u64 old_spte, u64 new_spte)
3106 {
3107         gfn_t gfn;
3108 
3109         WARN_ON(!sp->role.direct);
3110 
3111         /*
3112          * Theoretically we could also set dirty bit (and flush TLB) here in
3113          * order to eliminate unnecessary PML logging. See comments in
3114          * set_spte. But fast_page_fault is very unlikely to happen with PML
3115          * enabled, so we do not do this. This might result in the same GPA
3116          * to be logged in PML buffer again when the write really happens, and
3117          * eventually to be called by mark_page_dirty twice. But it's also no
3118          * harm. This also avoids the TLB flush needed after setting dirty bit
3119          * so non-PML cases won't be impacted.
3120          *
3121          * Compare with set_spte where instead shadow_dirty_mask is set.
3122          */
3123         if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3124                 return false;
3125 
3126         if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3127                 /*
3128                  * The gfn of direct spte is stable since it is
3129                  * calculated by sp->gfn.
3130                  */
3131                 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3132                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3133         }
3134 
3135         return true;
3136 }
3137 
3138 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3139 {
3140         if (fault_err_code & PFERR_FETCH_MASK)
3141                 return is_executable_pte(spte);
3142 
3143         if (fault_err_code & PFERR_WRITE_MASK)
3144                 return is_writable_pte(spte);
3145 
3146         /* Fault was on Read access */
3147         return spte & PT_PRESENT_MASK;
3148 }
3149 
3150 /*
3151  * Return value:
3152  * - true: let the vcpu to access on the same address again.
3153  * - false: let the real page fault path to fix it.
3154  */
3155 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
3156                             u32 error_code)
3157 {
3158         struct kvm_shadow_walk_iterator iterator;
3159         struct kvm_mmu_page *sp;
3160         bool fault_handled = false;
3161         u64 spte = 0ull;
3162         uint retry_count = 0;
3163 
3164         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3165                 return false;
3166 
3167         if (!page_fault_can_be_fast(error_code))
3168                 return false;
3169 
3170         walk_shadow_page_lockless_begin(vcpu);
3171 
3172         do {
3173                 u64 new_spte;
3174 
3175                 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
3176                         if (!is_shadow_present_pte(spte) ||
3177                             iterator.level < level)
3178                                 break;
3179 
3180                 sp = page_header(__pa(iterator.sptep));
3181                 if (!is_last_spte(spte, sp->role.level))
3182                         break;
3183 
3184                 /*
3185                  * Check whether the memory access that caused the fault would
3186                  * still cause it if it were to be performed right now. If not,
3187                  * then this is a spurious fault caused by TLB lazily flushed,
3188                  * or some other CPU has already fixed the PTE after the
3189                  * current CPU took the fault.
3190                  *
3191                  * Need not check the access of upper level table entries since
3192                  * they are always ACC_ALL.
3193                  */
3194                 if (is_access_allowed(error_code, spte)) {
3195                         fault_handled = true;
3196                         break;
3197                 }
3198 
3199                 new_spte = spte;
3200 
3201                 if (is_access_track_spte(spte))
3202                         new_spte = restore_acc_track_spte(new_spte);
3203 
3204                 /*
3205                  * Currently, to simplify the code, write-protection can
3206                  * be removed in the fast path only if the SPTE was
3207                  * write-protected for dirty-logging or access tracking.
3208                  */
3209                 if ((error_code & PFERR_WRITE_MASK) &&
3210                     spte_can_locklessly_be_made_writable(spte))
3211                 {
3212                         new_spte |= PT_WRITABLE_MASK;
3213 
3214                         /*
3215                          * Do not fix write-permission on the large spte.  Since
3216                          * we only dirty the first page into the dirty-bitmap in
3217                          * fast_pf_fix_direct_spte(), other pages are missed
3218                          * if its slot has dirty logging enabled.
3219                          *
3220                          * Instead, we let the slow page fault path create a
3221                          * normal spte to fix the access.
3222                          *
3223                          * See the comments in kvm_arch_commit_memory_region().
3224                          */
3225                         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3226                                 break;
3227                 }
3228 
3229                 /* Verify that the fault can be handled in the fast path */
3230                 if (new_spte == spte ||
3231                     !is_access_allowed(error_code, new_spte))
3232                         break;
3233 
3234                 /*
3235                  * Currently, fast page fault only works for direct mapping
3236                  * since the gfn is not stable for indirect shadow page. See
3237                  * Documentation/virtual/kvm/locking.txt to get more detail.
3238                  */
3239                 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3240                                                         iterator.sptep, spte,
3241                                                         new_spte);
3242                 if (fault_handled)
3243                         break;
3244 
3245                 if (++retry_count > 4) {
3246                         printk_once(KERN_WARNING
3247                                 "kvm: Fast #PF retrying more than 4 times.\n");
3248                         break;
3249                 }
3250 
3251         } while (true);
3252 
3253         trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3254                               spte, fault_handled);
3255         walk_shadow_page_lockless_end(vcpu);
3256 
3257         return fault_handled;
3258 }
3259 
3260 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3261                          gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3262 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
3263 
3264 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3265                          gfn_t gfn, bool prefault)
3266 {
3267         int r;
3268         int level;
3269         bool force_pt_level = false;
3270         kvm_pfn_t pfn;
3271         unsigned long mmu_seq;
3272         bool map_writable, write = error_code & PFERR_WRITE_MASK;
3273 
3274         level = mapping_level(vcpu, gfn, &force_pt_level);
3275         if (likely(!force_pt_level)) {
3276                 /*
3277                  * This path builds a PAE pagetable - so we can map
3278                  * 2mb pages at maximum. Therefore check if the level
3279                  * is larger than that.
3280                  */
3281                 if (level > PT_DIRECTORY_LEVEL)
3282                         level = PT_DIRECTORY_LEVEL;
3283 
3284                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3285         }
3286 
3287         if (fast_page_fault(vcpu, v, level, error_code))
3288                 return 0;
3289 
3290         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3291         smp_rmb();
3292 
3293         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3294                 return 0;
3295 
3296         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3297                 return r;
3298 
3299         spin_lock(&vcpu->kvm->mmu_lock);
3300         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3301                 goto out_unlock;
3302         make_mmu_pages_available(vcpu);
3303         if (likely(!force_pt_level))
3304                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3305         r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3306         spin_unlock(&vcpu->kvm->mmu_lock);
3307 
3308         return r;
3309 
3310 out_unlock:
3311         spin_unlock(&vcpu->kvm->mmu_lock);
3312         kvm_release_pfn_clean(pfn);
3313         return 0;
3314 }
3315 
3316 
3317 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3318 {
3319         int i;
3320         struct kvm_mmu_page *sp;
3321         LIST_HEAD(invalid_list);
3322 
3323         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3324                 return;
3325 
3326         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3327             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3328              vcpu->arch.mmu.direct_map)) {
3329                 hpa_t root = vcpu->arch.mmu.root_hpa;
3330 
3331                 spin_lock(&vcpu->kvm->mmu_lock);
3332                 sp = page_header(root);
3333                 --sp->root_count;
3334                 if (!sp->root_count && sp->role.invalid) {
3335                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3336                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3337                 }
3338                 spin_unlock(&vcpu->kvm->mmu_lock);
3339                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3340                 return;
3341         }
3342 
3343         spin_lock(&vcpu->kvm->mmu_lock);
3344         for (i = 0; i < 4; ++i) {
3345                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3346 
3347                 if (root) {
3348                         root &= PT64_BASE_ADDR_MASK;
3349                         sp = page_header(root);
3350                         --sp->root_count;
3351                         if (!sp->root_count && sp->role.invalid)
3352                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3353                                                          &invalid_list);
3354                 }
3355                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3356         }
3357         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3358         spin_unlock(&vcpu->kvm->mmu_lock);
3359         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3360 }
3361 
3362 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3363 {
3364         int ret = 0;
3365 
3366         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3367                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3368                 ret = 1;
3369         }
3370 
3371         return ret;
3372 }
3373 
3374 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3375 {
3376         struct kvm_mmu_page *sp;
3377         unsigned i;
3378 
3379         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3380                 spin_lock(&vcpu->kvm->mmu_lock);
3381                 make_mmu_pages_available(vcpu);
3382                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL);
3383                 ++sp->root_count;
3384                 spin_unlock(&vcpu->kvm->mmu_lock);
3385                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3386         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3387                 for (i = 0; i < 4; ++i) {
3388                         hpa_t root = vcpu->arch.mmu.pae_root[i];
3389 
3390                         MMU_WARN_ON(VALID_PAGE(root));
3391                         spin_lock(&vcpu->kvm->mmu_lock);
3392                         make_mmu_pages_available(vcpu);
3393                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3394                                         i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3395                         root = __pa(sp->spt);
3396                         ++sp->root_count;
3397                         spin_unlock(&vcpu->kvm->mmu_lock);
3398                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3399                 }
3400                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3401         } else
3402                 BUG();
3403 
3404         return 0;
3405 }
3406 
3407 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3408 {
3409         struct kvm_mmu_page *sp;
3410         u64 pdptr, pm_mask;
3411         gfn_t root_gfn;
3412         int i;
3413 
3414         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3415 
3416         if (mmu_check_root(vcpu, root_gfn))
3417                 return 1;
3418 
3419         /*
3420          * Do we shadow a long mode page table? If so we need to
3421          * write-protect the guests page table root.
3422          */
3423         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3424                 hpa_t root = vcpu->arch.mmu.root_hpa;
3425 
3426                 MMU_WARN_ON(VALID_PAGE(root));
3427 
3428                 spin_lock(&vcpu->kvm->mmu_lock);
3429                 make_mmu_pages_available(vcpu);
3430                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3431                                       0, ACC_ALL);
3432                 root = __pa(sp->spt);
3433                 ++sp->root_count;
3434                 spin_unlock(&vcpu->kvm->mmu_lock);
3435                 vcpu->arch.mmu.root_hpa = root;
3436                 return 0;
3437         }
3438 
3439         /*
3440          * We shadow a 32 bit page table. This may be a legacy 2-level
3441          * or a PAE 3-level page table. In either case we need to be aware that
3442          * the shadow page table may be a PAE or a long mode page table.
3443          */
3444         pm_mask = PT_PRESENT_MASK;
3445         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3446                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3447 
3448         for (i = 0; i < 4; ++i) {
3449                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3450 
3451                 MMU_WARN_ON(VALID_PAGE(root));
3452                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3453                         pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3454                         if (!(pdptr & PT_PRESENT_MASK)) {
3455                                 vcpu->arch.mmu.pae_root[i] = 0;
3456                                 continue;
3457                         }
3458                         root_gfn = pdptr >> PAGE_SHIFT;
3459                         if (mmu_check_root(vcpu, root_gfn))
3460                                 return 1;
3461                 }
3462                 spin_lock(&vcpu->kvm->mmu_lock);
3463                 make_mmu_pages_available(vcpu);
3464                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3465                                       0, ACC_ALL);
3466                 root = __pa(sp->spt);
3467                 ++sp->root_count;
3468                 spin_unlock(&vcpu->kvm->mmu_lock);
3469 
3470                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3471         }
3472         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3473 
3474         /*
3475          * If we shadow a 32 bit page table with a long mode page
3476          * table we enter this path.
3477          */
3478         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3479                 if (vcpu->arch.mmu.lm_root == NULL) {
3480                         /*
3481                          * The additional page necessary for this is only
3482                          * allocated on demand.
3483                          */
3484 
3485                         u64 *lm_root;
3486 
3487                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3488                         if (lm_root == NULL)
3489                                 return 1;
3490 
3491                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3492 
3493                         vcpu->arch.mmu.lm_root = lm_root;
3494                 }
3495 
3496                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3497         }
3498 
3499         return 0;
3500 }
3501 
3502 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3503 {
3504         if (vcpu->arch.mmu.direct_map)
3505                 return mmu_alloc_direct_roots(vcpu);
3506         else
3507                 return mmu_alloc_shadow_roots(vcpu);
3508 }
3509 
3510 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3511 {
3512         int i;
3513         struct kvm_mmu_page *sp;
3514 
3515         if (vcpu->arch.mmu.direct_map)
3516                 return;
3517 
3518         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3519                 return;
3520 
3521         vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3522         kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3523         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3524                 hpa_t root = vcpu->arch.mmu.root_hpa;
3525                 sp = page_header(root);
3526                 mmu_sync_children(vcpu, sp);
3527                 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3528                 return;
3529         }
3530         for (i = 0; i < 4; ++i) {
3531                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3532 
3533                 if (root && VALID_PAGE(root)) {
3534                         root &= PT64_BASE_ADDR_MASK;
3535                         sp = page_header(root);
3536                         mmu_sync_children(vcpu, sp);
3537                 }
3538         }
3539         kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3540 }
3541 
3542 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3543 {
3544         spin_lock(&vcpu->kvm->mmu_lock);
3545         mmu_sync_roots(vcpu);
3546         spin_unlock(&vcpu->kvm->mmu_lock);
3547 }
3548 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3549 
3550 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3551                                   u32 access, struct x86_exception *exception)
3552 {
3553         if (exception)
3554                 exception->error_code = 0;
3555         return vaddr;
3556 }
3557 
3558 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3559                                          u32 access,
3560                                          struct x86_exception *exception)
3561 {
3562         if (exception)
3563                 exception->error_code = 0;
3564         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3565 }
3566 
3567 static bool
3568 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3569 {
3570         int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3571 
3572         return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3573                 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3574 }
3575 
3576 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3577 {
3578         return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3579 }
3580 
3581 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3582 {
3583         return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3584 }
3585 
3586 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3587 {
3588         if (direct)
3589                 return vcpu_match_mmio_gpa(vcpu, addr);
3590 
3591         return vcpu_match_mmio_gva(vcpu, addr);
3592 }
3593 
3594 /* return true if reserved bit is detected on spte. */
3595 static bool
3596 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3597 {
3598         struct kvm_shadow_walk_iterator iterator;
3599         u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3600         int root, leaf;
3601         bool reserved = false;
3602 
3603         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3604                 goto exit;
3605 
3606         walk_shadow_page_lockless_begin(vcpu);
3607 
3608         for (shadow_walk_init(&iterator, vcpu, addr),
3609                  leaf = root = iterator.level;
3610              shadow_walk_okay(&iterator);
3611              __shadow_walk_next(&iterator, spte)) {
3612                 spte = mmu_spte_get_lockless(iterator.sptep);
3613 
3614                 sptes[leaf - 1] = spte;
3615                 leaf--;
3616 
3617                 if (!is_shadow_present_pte(spte))
3618                         break;
3619 
3620                 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3621                                                     iterator.level);
3622         }
3623 
3624         walk_shadow_page_lockless_end(vcpu);
3625 
3626         if (reserved) {
3627                 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3628                        __func__, addr);
3629                 while (root > leaf) {
3630                         pr_err("------ spte 0x%llx level %d.\n",
3631                                sptes[root - 1], root);
3632                         root--;
3633                 }
3634         }
3635 exit:
3636         *sptep = spte;
3637         return reserved;
3638 }
3639 
3640 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3641 {
3642         u64 spte;
3643         bool reserved;
3644 
3645         if (mmio_info_in_cache(vcpu, addr, direct))
3646                 return RET_MMIO_PF_EMULATE;
3647 
3648         reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3649         if (WARN_ON(reserved))
3650                 return RET_MMIO_PF_BUG;
3651 
3652         if (is_mmio_spte(spte)) {
3653                 gfn_t gfn = get_mmio_spte_gfn(spte);
3654                 unsigned access = get_mmio_spte_access(spte);
3655 
3656                 if (!check_mmio_spte(vcpu, spte))
3657                         return RET_MMIO_PF_INVALID;
3658 
3659                 if (direct)
3660                         addr = 0;
3661 
3662                 trace_handle_mmio_page_fault(addr, gfn, access);
3663                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3664                 return RET_MMIO_PF_EMULATE;
3665         }
3666 
3667         /*
3668          * If the page table is zapped by other cpus, let CPU fault again on
3669          * the address.
3670          */
3671         return RET_MMIO_PF_RETRY;
3672 }
3673 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3674 
3675 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3676                                          u32 error_code, gfn_t gfn)
3677 {
3678         if (unlikely(error_code & PFERR_RSVD_MASK))
3679                 return false;
3680 
3681         if (!(error_code & PFERR_PRESENT_MASK) ||
3682               !(error_code & PFERR_WRITE_MASK))
3683                 return false;
3684 
3685         /*
3686          * guest is writing the page which is write tracked which can
3687          * not be fixed by page fault handler.
3688          */
3689         if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3690                 return true;
3691 
3692         return false;
3693 }
3694 
3695 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3696 {
3697         struct kvm_shadow_walk_iterator iterator;
3698         u64 spte;
3699 
3700         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3701                 return;
3702 
3703         walk_shadow_page_lockless_begin(vcpu);
3704         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3705                 clear_sp_write_flooding_count(iterator.sptep);
3706                 if (!is_shadow_present_pte(spte))
3707                         break;
3708         }
3709         walk_shadow_page_lockless_end(vcpu);
3710 }
3711 
3712 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3713                                 u32 error_code, bool prefault)
3714 {
3715         gfn_t gfn = gva >> PAGE_SHIFT;
3716         int r;
3717 
3718         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3719 
3720         if (page_fault_handle_page_track(vcpu, error_code, gfn))
3721                 return 1;
3722 
3723         r = mmu_topup_memory_caches(vcpu);
3724         if (r)
3725                 return r;
3726 
3727         MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3728 
3729 
3730         return nonpaging_map(vcpu, gva & PAGE_MASK,
3731                              error_code, gfn, prefault);
3732 }
3733 
3734 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3735 {
3736         struct kvm_arch_async_pf arch;
3737 
3738         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3739         arch.gfn = gfn;
3740         arch.direct_map = vcpu->arch.mmu.direct_map;
3741         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3742 
3743         return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3744 }
3745 
3746 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
3747 {
3748         if (unlikely(!lapic_in_kernel(vcpu) ||
3749                      kvm_event_needs_reinjection(vcpu)))
3750                 return false;
3751 
3752         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
3753                 return false;
3754 
3755         return kvm_x86_ops->interrupt_allowed(vcpu);
3756 }
3757 
3758 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3759                          gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3760 {
3761         struct kvm_memory_slot *slot;
3762         bool async;
3763 
3764         slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3765         async = false;
3766         *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3767         if (!async)
3768                 return false; /* *pfn has correct page already */
3769 
3770         if (!prefault && kvm_can_do_async_pf(vcpu)) {
3771                 trace_kvm_try_async_get_page(gva, gfn);
3772                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3773                         trace_kvm_async_pf_doublefault(gva, gfn);
3774                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3775                         return true;
3776                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3777                         return true;
3778         }
3779 
3780         *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3781         return false;
3782 }
3783 
3784 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3785                                 u64 fault_address, char *insn, int insn_len,
3786                                 bool need_unprotect)
3787 {
3788         int r = 1;
3789 
3790         switch (vcpu->arch.apf.host_apf_reason) {
3791         default:
3792                 trace_kvm_page_fault(fault_address, error_code);
3793 
3794                 if (need_unprotect && kvm_event_needs_reinjection(vcpu))
3795                         kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3796                 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3797                                 insn_len);
3798                 break;
3799         case KVM_PV_REASON_PAGE_NOT_PRESENT:
3800                 vcpu->arch.apf.host_apf_reason = 0;
3801                 local_irq_disable();
3802                 kvm_async_pf_task_wait(fault_address, 0);
3803                 local_irq_enable();
3804                 break;
3805         case KVM_PV_REASON_PAGE_READY:
3806                 vcpu->arch.apf.host_apf_reason = 0;
3807                 local_irq_disable();
3808                 kvm_async_pf_task_wake(fault_address);
3809                 local_irq_enable();
3810                 break;
3811         }
3812         return r;
3813 }
3814 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3815 
3816 static bool
3817 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3818 {
3819         int page_num = KVM_PAGES_PER_HPAGE(level);
3820 
3821         gfn &= ~(page_num - 1);
3822 
3823         return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3824 }
3825 
3826 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3827                           bool prefault)
3828 {
3829         kvm_pfn_t pfn;
3830         int r;
3831         int level;
3832         bool force_pt_level;
3833         gfn_t gfn = gpa >> PAGE_SHIFT;
3834         unsigned long mmu_seq;
3835         int write = error_code & PFERR_WRITE_MASK;
3836         bool map_writable;
3837 
3838         MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3839 
3840         if (page_fault_handle_page_track(vcpu, error_code, gfn))
3841                 return 1;
3842 
3843         r = mmu_topup_memory_caches(vcpu);
3844         if (r)
3845                 return r;
3846 
3847         force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3848                                                            PT_DIRECTORY_LEVEL);
3849         level = mapping_level(vcpu, gfn, &force_pt_level);
3850         if (likely(!force_pt_level)) {
3851                 if (level > PT_DIRECTORY_LEVEL &&
3852                     !check_hugepage_cache_consistency(vcpu, gfn, level))
3853                         level = PT_DIRECTORY_LEVEL;
3854                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3855         }
3856 
3857         if (fast_page_fault(vcpu, gpa, level, error_code))
3858                 return 0;
3859 
3860         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3861         smp_rmb();
3862 
3863         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3864                 return 0;
3865 
3866         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3867                 return r;
3868 
3869         spin_lock(&vcpu->kvm->mmu_lock);
3870         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3871                 goto out_unlock;
3872         make_mmu_pages_available(vcpu);
3873         if (likely(!force_pt_level))
3874                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3875         r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3876         spin_unlock(&vcpu->kvm->mmu_lock);
3877 
3878         return r;
3879 
3880 out_unlock:
3881         spin_unlock(&vcpu->kvm->mmu_lock);
3882         kvm_release_pfn_clean(pfn);
3883         return 0;
3884 }
3885 
3886 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3887                                    struct kvm_mmu *context)
3888 {
3889         context->page_fault = nonpaging_page_fault;
3890         context->gva_to_gpa = nonpaging_gva_to_gpa;
3891         context->sync_page = nonpaging_sync_page;
3892         context->invlpg = nonpaging_invlpg;
3893         context->update_pte = nonpaging_update_pte;
3894         context->root_level = 0;
3895         context->shadow_root_level = PT32E_ROOT_LEVEL;
3896         context->root_hpa = INVALID_PAGE;
3897         context->direct_map = true;
3898         context->nx = false;
3899 }
3900 
3901 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3902 {
3903         mmu_free_roots(vcpu);
3904 }
3905 
3906 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3907 {
3908         return kvm_read_cr3(vcpu);
3909 }
3910 
3911 static void inject_page_fault(struct kvm_vcpu *vcpu,
3912                               struct x86_exception *fault)
3913 {
3914         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3915 }
3916 
3917 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3918                            unsigned access, int *nr_present)
3919 {
3920         if (unlikely(is_mmio_spte(*sptep))) {
3921                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3922                         mmu_spte_clear_no_track(sptep);
3923                         return true;
3924                 }
3925 
3926                 (*nr_present)++;
3927                 mark_mmio_spte(vcpu, sptep, gfn, access);
3928                 return true;
3929         }
3930 
3931         return false;
3932 }
3933 
3934 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3935                                 unsigned level, unsigned gpte)
3936 {
3937         /*
3938          * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3939          * If it is clear, there are no large pages at this level, so clear
3940          * PT_PAGE_SIZE_MASK in gpte if that is the case.
3941          */
3942         gpte &= level - mmu->last_nonleaf_level;
3943 
3944         /*
3945          * PT_PAGE_TABLE_LEVEL always terminates.  The RHS has bit 7 set
3946          * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3947          * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3948          */
3949         gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
3950 
3951         return gpte & PT_PAGE_SIZE_MASK;
3952 }
3953 
3954 #define PTTYPE_EPT 18 /* arbitrary */
3955 #define PTTYPE PTTYPE_EPT
3956 #include "paging_tmpl.h"
3957 #undef PTTYPE
3958 
3959 #define PTTYPE 64
3960 #include "paging_tmpl.h"
3961 #undef PTTYPE
3962 
3963 #define PTTYPE 32
3964 #include "paging_tmpl.h"
3965 #undef PTTYPE
3966 
3967 static void
3968 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3969                         struct rsvd_bits_validate *rsvd_check,
3970                         int maxphyaddr, int level, bool nx, bool gbpages,
3971                         bool pse, bool amd)
3972 {
3973         u64 exb_bit_rsvd = 0;
3974         u64 gbpages_bit_rsvd = 0;
3975         u64 nonleaf_bit8_rsvd = 0;
3976 
3977         rsvd_check->bad_mt_xwr = 0;
3978 
3979         if (!nx)
3980                 exb_bit_rsvd = rsvd_bits(63, 63);
3981         if (!gbpages)
3982                 gbpages_bit_rsvd = rsvd_bits(7, 7);
3983 
3984         /*
3985          * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3986          * leaf entries) on AMD CPUs only.
3987          */
3988         if (amd)
3989                 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3990 
3991         switch (level) {
3992         case PT32_ROOT_LEVEL:
3993                 /* no rsvd bits for 2 level 4K page table entries */
3994                 rsvd_check->rsvd_bits_mask[0][1] = 0;
3995                 rsvd_check->rsvd_bits_mask[0][0] = 0;
3996                 rsvd_check->rsvd_bits_mask[1][0] =
3997                         rsvd_check->rsvd_bits_mask[0][0];
3998 
3999                 if (!pse) {
4000                         rsvd_check->rsvd_bits_mask[1][1] = 0;
4001                         break;
4002                 }
4003 
4004                 if (is_cpuid_PSE36())
4005                         /* 36bits PSE 4MB page */
4006                         rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4007                 else
4008                         /* 32 bits PSE 4MB page */
4009                         rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4010                 break;
4011         case PT32E_ROOT_LEVEL:
4012                 rsvd_check->rsvd_bits_mask[0][2] =
4013                         rsvd_bits(maxphyaddr, 63) |
4014                         rsvd_bits(5, 8) | rsvd_bits(1, 2);      /* PDPTE */
4015                 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4016                         rsvd_bits(maxphyaddr, 62);      /* PDE */
4017                 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4018                         rsvd_bits(maxphyaddr, 62);      /* PTE */
4019                 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4020                         rsvd_bits(maxphyaddr, 62) |
4021                         rsvd_bits(13, 20);              /* large page */
4022                 rsvd_check->rsvd_bits_mask[1][0] =
4023                         rsvd_check->rsvd_bits_mask[0][0];
4024                 break;
4025         case PT64_ROOT_LEVEL:
4026                 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4027                         nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4028                         rsvd_bits(maxphyaddr, 51);
4029                 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4030                         nonleaf_bit8_rsvd | gbpages_bit_rsvd |
4031                         rsvd_bits(maxphyaddr, 51);
4032                 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4033                         rsvd_bits(maxphyaddr, 51);
4034                 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4035                         rsvd_bits(maxphyaddr, 51);
4036                 rsvd_check->rsvd_bits_mask[1][3] =
4037                         rsvd_check->rsvd_bits_mask[0][3];
4038                 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4039                         gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4040                         rsvd_bits(13, 29);
4041                 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4042                         rsvd_bits(maxphyaddr, 51) |
4043                         rsvd_bits(13, 20);              /* large page */
4044                 rsvd_check->rsvd_bits_mask[1][0] =
4045                         rsvd_check->rsvd_bits_mask[0][0];
4046                 break;
4047         }
4048 }
4049 
4050 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4051                                   struct kvm_mmu *context)
4052 {
4053         __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4054                                 cpuid_maxphyaddr(vcpu), context->root_level,
4055                                 context->nx, guest_cpuid_has_gbpages(vcpu),
4056                                 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
4057 }
4058 
4059 static void
4060 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4061                             int maxphyaddr, bool execonly)
4062 {
4063         u64 bad_mt_xwr;
4064 
4065         rsvd_check->rsvd_bits_mask[0][3] =
4066                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4067         rsvd_check->rsvd_bits_mask[0][2] =
4068                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4069         rsvd_check->rsvd_bits_mask[0][1] =
4070                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4071         rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4072 
4073         /* large page */
4074         rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4075         rsvd_check->rsvd_bits_mask[1][2] =
4076                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4077         rsvd_check->rsvd_bits_mask[1][1] =
4078                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4079         rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4080 
4081         bad_mt_xwr = 0xFFull << (2 * 8);        /* bits 3..5 must not be 2 */
4082         bad_mt_xwr |= 0xFFull << (3 * 8);       /* bits 3..5 must not be 3 */
4083         bad_mt_xwr |= 0xFFull << (7 * 8);       /* bits 3..5 must not be 7 */
4084         bad_mt_xwr |= REPEAT_BYTE(1ull << 2);   /* bits 0..2 must not be 010 */
4085         bad_mt_xwr |= REPEAT_BYTE(1ull << 6);   /* bits 0..2 must not be 110 */
4086         if (!execonly) {
4087                 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4088                 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4089         }
4090         rsvd_check->bad_mt_xwr = bad_mt_xwr;
4091 }
4092 
4093 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4094                 struct kvm_mmu *context, bool execonly)
4095 {
4096         __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4097                                     cpuid_maxphyaddr(vcpu), execonly);
4098 }
4099 
4100 /*
4101  * the page table on host is the shadow page table for the page
4102  * table in guest or amd nested guest, its mmu features completely
4103  * follow the features in guest.
4104  */
4105 void
4106 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4107 {
4108         bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
4109 
4110         /*
4111          * Passing "true" to the last argument is okay; it adds a check
4112          * on bit 8 of the SPTEs which KVM doesn't use anyway.
4113          */
4114         __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
4115                                 boot_cpu_data.x86_phys_bits,
4116                                 context->shadow_root_level, uses_nx,
4117                                 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
4118                                 true);
4119 }
4120 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4121 
4122 static inline bool boot_cpu_is_amd(void)
4123 {
4124         WARN_ON_ONCE(!tdp_enabled);
4125         return shadow_x_mask == 0;
4126 }
4127 
4128 /*
4129  * the direct page table on host, use as much mmu features as
4130  * possible, however, kvm currently does not do execution-protection.
4131  */
4132 static void
4133 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4134                                 struct kvm_mmu *context)
4135 {
4136         if (boot_cpu_is_amd())
4137                 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
4138                                         boot_cpu_data.x86_phys_bits,
4139                                         context->shadow_root_level, false,
4140                                         boot_cpu_has(X86_FEATURE_GBPAGES),
4141                                         true, true);
4142         else
4143                 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4144                                             boot_cpu_data.x86_phys_bits,
4145                                             false);
4146 
4147 }
4148 
4149 /*
4150  * as the comments in reset_shadow_zero_bits_mask() except it
4151  * is the shadow page table for intel nested guest.
4152  */
4153 static void
4154 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4155                                 struct kvm_mmu *context, bool execonly)
4156 {
4157         __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4158                                     boot_cpu_data.x86_phys_bits, execonly);
4159 }
4160 
4161 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4162                                       struct kvm_mmu *mmu, bool ept)
4163 {
4164         unsigned bit, byte, pfec;
4165         u8 map;
4166         bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
4167 
4168         cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4169         cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4170         for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4171                 pfec = byte << 1;
4172                 map = 0;
4173                 wf = pfec & PFERR_WRITE_MASK;
4174                 uf = pfec & PFERR_USER_MASK;
4175                 ff = pfec & PFERR_FETCH_MASK;
4176                 /*
4177                  * PFERR_RSVD_MASK bit is set in PFEC if the access is not
4178                  * subject to SMAP restrictions, and cleared otherwise. The
4179                  * bit is only meaningful if the SMAP bit is set in CR4.
4180                  */
4181                 smapf = !(pfec & PFERR_RSVD_MASK);
4182                 for (bit = 0; bit < 8; ++bit) {
4183                         x = bit & ACC_EXEC_MASK;
4184                         w = bit & ACC_WRITE_MASK;
4185                         u = bit & ACC_USER_MASK;
4186 
4187                         if (!ept) {
4188                                 /* Not really needed: !nx will cause pte.nx to fault */
4189                                 x |= !mmu->nx;
4190                                 /* Allow supervisor writes if !cr0.wp */
4191                                 w |= !is_write_protection(vcpu) && !uf;
4192                                 /* Disallow supervisor fetches of user code if cr4.smep */
4193                                 x &= !(cr4_smep && u && !uf);
4194 
4195                                 /*
4196                                  * SMAP:kernel-mode data accesses from user-mode
4197                                  * mappings should fault. A fault is considered
4198                                  * as a SMAP violation if all of the following
4199                                  * conditions are ture:
4200                                  *   - X86_CR4_SMAP is set in CR4
4201                                  *   - A user page is accessed
4202                                  *   - Page fault in kernel mode
4203                                  *   - if CPL = 3 or X86_EFLAGS_AC is clear
4204                                  *
4205                                  *   Here, we cover the first three conditions.
4206                                  *   The fourth is computed dynamically in
4207                                  *   permission_fault() and is in smapf.
4208                                  *
4209                                  *   Also, SMAP does not affect instruction
4210                                  *   fetches, add the !ff check here to make it
4211                                  *   clearer.
4212                                  */
4213                                 smap = cr4_smap && u && !uf && !ff;
4214                         }
4215 
4216                         fault = (ff && !x) || (uf && !u) || (wf && !w) ||
4217                                 (smapf && smap);
4218                         map |= fault << bit;
4219                 }
4220                 mmu->permissions[byte] = map;
4221         }
4222 }
4223 
4224 /*
4225 * PKU is an additional mechanism by which the paging controls access to
4226 * user-mode addresses based on the value in the PKRU register.  Protection
4227 * key violations are reported through a bit in the page fault error code.
4228 * Unlike other bits of the error code, the PK bit is not known at the
4229 * call site of e.g. gva_to_gpa; it must be computed directly in
4230 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4231 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4232 *
4233 * In particular the following conditions come from the error code, the
4234 * page tables and the machine state:
4235 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4236 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4237 * - PK is always zero if U=0 in the page tables
4238 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4239 *
4240 * The PKRU bitmask caches the result of these four conditions.  The error
4241 * code (minus the P bit) and the page table's U bit form an index into the
4242 * PKRU bitmask.  Two bits of the PKRU bitmask are then extracted and ANDed
4243 * with the two bits of the PKRU register corresponding to the protection key.
4244 * For the first three conditions above the bits will be 00, thus masking
4245 * away both AD and WD.  For all reads or if the last condition holds, WD
4246 * only will be masked away.
4247 */
4248 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4249                                 bool ept)
4250 {
4251         unsigned bit;
4252         bool wp;
4253 
4254         if (ept) {
4255                 mmu->pkru_mask = 0;
4256                 return;
4257         }
4258 
4259         /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4260         if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4261                 mmu->pkru_mask = 0;
4262                 return;
4263         }
4264 
4265         wp = is_write_protection(vcpu);
4266 
4267         for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4268                 unsigned pfec, pkey_bits;
4269                 bool check_pkey, check_write, ff, uf, wf, pte_user;
4270 
4271                 pfec = bit << 1;
4272                 ff = pfec & PFERR_FETCH_MASK;
4273                 uf = pfec & PFERR_USER_MASK;
4274                 wf = pfec & PFERR_WRITE_MASK;
4275 
4276                 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4277                 pte_user = pfec & PFERR_RSVD_MASK;
4278 
4279                 /*
4280                  * Only need to check the access which is not an
4281                  * instruction fetch and is to a user page.
4282                  */
4283                 check_pkey = (!ff && pte_user);
4284                 /*
4285                  * write access is controlled by PKRU if it is a
4286                  * user access or CR0.WP = 1.
4287                  */
4288                 check_write = check_pkey && wf && (uf || wp);
4289 
4290                 /* PKRU.AD stops both read and write access. */
4291                 pkey_bits = !!check_pkey;
4292                 /* PKRU.WD stops write access. */
4293                 pkey_bits |= (!!check_write) << 1;
4294 
4295                 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4296         }
4297 }
4298 
4299 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4300 {
4301         unsigned root_level = mmu->root_level;
4302 
4303         mmu->last_nonleaf_level = root_level;
4304         if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4305                 mmu->last_nonleaf_level++;
4306 }
4307 
4308 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4309                                          struct kvm_mmu *context,
4310                                          int level)
4311 {
4312         context->nx = is_nx(vcpu);
4313         context->root_level = level;
4314 
4315         reset_rsvds_bits_mask(vcpu, context);
4316         update_permission_bitmask(vcpu, context, false);
4317         update_pkru_bitmask(vcpu, context, false);
4318         update_last_nonleaf_level(vcpu, context);
4319 
4320         MMU_WARN_ON(!is_pae(vcpu));
4321         context->page_fault = paging64_page_fault;
4322         context->gva_to_gpa = paging64_gva_to_gpa;
4323         context->sync_page = paging64_sync_page;
4324         context->invlpg = paging64_invlpg;
4325         context->update_pte = paging64_update_pte;
4326         context->shadow_root_level = level;
4327         context->root_hpa = INVALID_PAGE;
4328         context->direct_map = false;
4329 }
4330 
4331 static void paging64_init_context(struct kvm_vcpu *vcpu,
4332                                   struct kvm_mmu *context)
4333 {
4334         paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
4335 }
4336 
4337 static void paging32_init_context(struct kvm_vcpu *vcpu,
4338                                   struct kvm_mmu *context)
4339 {
4340         context->nx = false;
4341         context->root_level = PT32_ROOT_LEVEL;
4342 
4343         reset_rsvds_bits_mask(vcpu, context);
4344         update_permission_bitmask(vcpu, context, false);
4345         update_pkru_bitmask(vcpu, context, false);
4346         update_last_nonleaf_level(vcpu, context);
4347 
4348         context->page_fault = paging32_page_fault;
4349         context->gva_to_gpa = paging32_gva_to_gpa;
4350         context->sync_page = paging32_sync_page;
4351         context->invlpg = paging32_invlpg;
4352         context->update_pte = paging32_update_pte;
4353         context->shadow_root_level = PT32E_ROOT_LEVEL;
4354         context->root_hpa = INVALID_PAGE;
4355         context->direct_map = false;
4356 }
4357 
4358 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4359                                    struct kvm_mmu *context)
4360 {
4361         paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4362 }
4363 
4364 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4365 {
4366         struct kvm_mmu *context = &vcpu->arch.mmu;
4367 
4368         context->base_role.word = 0;
4369         context->base_role.smm = is_smm(vcpu);
4370         context->base_role.ad_disabled = (shadow_accessed_mask == 0);
4371         context->page_fault = tdp_page_fault;
4372         context->sync_page = nonpaging_sync_page;
4373         context->invlpg = nonpaging_invlpg;
4374         context->update_pte = nonpaging_update_pte;
4375         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4376         context->root_hpa = INVALID_PAGE;
4377         context->direct_map = true;
4378         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4379         context->get_cr3 = get_cr3;
4380         context->get_pdptr = kvm_pdptr_read;
4381         context->inject_page_fault = kvm_inject_page_fault;
4382 
4383         if (!is_paging(vcpu)) {
4384                 context->nx = false;
4385                 context->gva_to_gpa = nonpaging_gva_to_gpa;
4386                 context->root_level = 0;
4387         } else if (is_long_mode(vcpu)) {
4388                 context->nx = is_nx(vcpu);
4389                 context->root_level = PT64_ROOT_LEVEL;
4390                 reset_rsvds_bits_mask(vcpu, context);
4391                 context->gva_to_gpa = paging64_gva_to_gpa;
4392         } else if (is_pae(vcpu)) {
4393                 context->nx = is_nx(vcpu);
4394                 context->root_level = PT32E_ROOT_LEVEL;
4395                 reset_rsvds_bits_mask(vcpu, context);
4396                 context->gva_to_gpa = paging64_gva_to_gpa;
4397         } else {
4398                 context->nx = false;
4399                 context->root_level = PT32_ROOT_LEVEL;
4400                 reset_rsvds_bits_mask(vcpu, context);
4401                 context->gva_to_gpa = paging32_gva_to_gpa;
4402         }
4403 
4404         update_permission_bitmask(vcpu, context, false);
4405         update_pkru_bitmask(vcpu, context, false);
4406         update_last_nonleaf_level(vcpu, context);
4407         reset_tdp_shadow_zero_bits_mask(vcpu, context);
4408 }
4409 
4410 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4411 {
4412         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4413         bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4414         struct kvm_mmu *context = &vcpu->arch.mmu;
4415 
4416         MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4417 
4418         if (!is_paging(vcpu))
4419                 nonpaging_init_context(vcpu, context);
4420         else if (is_long_mode(vcpu))
4421                 paging64_init_context(vcpu, context);
4422         else if (is_pae(vcpu))
4423                 paging32E_init_context(vcpu, context);
4424         else
4425                 paging32_init_context(vcpu, context);
4426 
4427         context->base_role.nxe = is_nx(vcpu);
4428         context->base_role.cr4_pae = !!is_pae(vcpu);
4429         context->base_role.cr0_wp  = is_write_protection(vcpu);
4430         context->base_role.smep_andnot_wp
4431                 = smep && !is_write_protection(vcpu);
4432         context->base_role.smap_andnot_wp
4433                 = smap && !is_write_protection(vcpu);
4434         context->base_role.smm = is_smm(vcpu);
4435         reset_shadow_zero_bits_mask(vcpu, context);
4436 }
4437 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4438 
4439 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4440                              bool accessed_dirty)
4441 {
4442         struct kvm_mmu *context = &vcpu->arch.mmu;
4443 
4444         MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4445 
4446         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4447 
4448         context->nx = true;
4449         context->ept_ad = accessed_dirty;
4450         context->page_fault = ept_page_fault;
4451         context->gva_to_gpa = ept_gva_to_gpa;
4452         context->sync_page = ept_sync_page;
4453         context->invlpg = ept_invlpg;
4454         context->update_pte = ept_update_pte;
4455         context->root_level = context->shadow_root_level;
4456         context->root_hpa = INVALID_PAGE;
4457         context->direct_map = false;
4458         context->base_role.ad_disabled = !accessed_dirty;
4459 
4460         update_permission_bitmask(vcpu, context, true);
4461         update_pkru_bitmask(vcpu, context, true);
4462         update_last_nonleaf_level(vcpu, context);
4463         reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4464         reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4465 }
4466 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4467 
4468 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4469 {
4470         struct kvm_mmu *context = &vcpu->arch.mmu;
4471 
4472         kvm_init_shadow_mmu(vcpu);
4473         context->set_cr3           = kvm_x86_ops->set_cr3;
4474         context->get_cr3           = get_cr3;
4475         context->get_pdptr         = kvm_pdptr_read;
4476         context->inject_page_fault = kvm_inject_page_fault;
4477 }
4478 
4479 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4480 {
4481         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4482 
4483         g_context->get_cr3           = get_cr3;
4484         g_context->get_pdptr         = kvm_pdptr_read;
4485         g_context->inject_page_fault = kvm_inject_page_fault;
4486 
4487         /*
4488          * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4489          * L1's nested page tables (e.g. EPT12). The nested translation
4490          * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4491          * L2's page tables as the first level of translation and L1's
4492          * nested page tables as the second level of translation. Basically
4493          * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4494          */
4495         if (!is_paging(vcpu)) {
4496                 g_context->nx = false;
4497                 g_context->root_level = 0;
4498                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4499         } else if (is_long_mode(vcpu)) {
4500                 g_context->nx = is_nx(vcpu);
4501                 g_context->root_level = PT64_ROOT_LEVEL;
4502                 reset_rsvds_bits_mask(vcpu, g_context);
4503                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4504         } else if (is_pae(vcpu)) {
4505                 g_context->nx = is_nx(vcpu);
4506                 g_context->root_level = PT32E_ROOT_LEVEL;
4507                 reset_rsvds_bits_mask(vcpu, g_context);
4508                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4509         } else {
4510                 g_context->nx = false;
4511                 g_context->root_level = PT32_ROOT_LEVEL;
4512                 reset_rsvds_bits_mask(vcpu, g_context);
4513                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4514         }
4515 
4516         update_permission_bitmask(vcpu, g_context, false);
4517         update_pkru_bitmask(vcpu, g_context, false);
4518         update_last_nonleaf_level(vcpu, g_context);
4519 }
4520 
4521 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4522 {
4523         if (mmu_is_nested(vcpu))
4524                 init_kvm_nested_mmu(vcpu);
4525         else if (tdp_enabled)
4526                 init_kvm_tdp_mmu(vcpu);
4527         else
4528                 init_kvm_softmmu(vcpu);
4529 }
4530 
4531 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4532 {
4533         kvm_mmu_unload(vcpu);
4534         init_kvm_mmu(vcpu);
4535 }
4536 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4537 
4538 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4539 {
4540         int r;
4541 
4542         r = mmu_topup_memory_caches(vcpu);
4543         if (r)
4544                 goto out;
4545         r = mmu_alloc_roots(vcpu);
4546         kvm_mmu_sync_roots(vcpu);
4547         if (r)
4548                 goto out;
4549         /* set_cr3() should ensure TLB has been flushed */
4550         vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4551 out:
4552         return r;
4553 }
4554 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4555 
4556 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4557 {
4558         mmu_free_roots(vcpu);
4559         WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4560 }
4561 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4562 
4563 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4564                                   struct kvm_mmu_page *sp, u64 *spte,
4565                                   const void *new)
4566 {
4567         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4568                 ++vcpu->kvm->stat.mmu_pde_zapped;
4569                 return;
4570         }
4571 
4572         ++vcpu->kvm->stat.mmu_pte_updated;
4573         vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4574 }
4575 
4576 static bool need_remote_flush(u64 old, u64 new)
4577 {
4578         if (!is_shadow_present_pte(old))
4579                 return false;
4580         if (!is_shadow_present_pte(new))
4581                 return true;
4582         if ((old ^ new) & PT64_BASE_ADDR_MASK)
4583                 return true;
4584         old ^= shadow_nx_mask;
4585         new ^= shadow_nx_mask;
4586         return (old & ~new & PT64_PERM_MASK) != 0;
4587 }
4588 
4589 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4590                                     const u8 *new, int *bytes)
4591 {
4592         u64 gentry;
4593         int r;
4594 
4595         /*
4596          * Assume that the pte write on a page table of the same type
4597          * as the current vcpu paging mode since we update the sptes only
4598          * when they have the same mode.
4599          */
4600         if (is_pae(vcpu) && *bytes == 4) {
4601                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4602                 *gpa &= ~(gpa_t)7;
4603                 *bytes = 8;
4604                 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4605                 if (r)
4606                         gentry = 0;
4607                 new = (const u8 *)&gentry;
4608         }
4609 
4610         switch (*bytes) {
4611         case 4:
4612                 gentry = *(const u32 *)new;
4613                 break;
4614         case 8:
4615                 gentry = *(const u64 *)new;
4616                 break;
4617         default:
4618                 gentry = 0;
4619                 break;
4620         }
4621 
4622         return gentry;
4623 }
4624 
4625 /*
4626  * If we're seeing too many writes to a page, it may no longer be a page table,
4627  * or we may be forking, in which case it is better to unmap the page.
4628  */
4629 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4630 {
4631         /*
4632          * Skip write-flooding detected for the sp whose level is 1, because
4633          * it can become unsync, then the guest page is not write-protected.
4634          */
4635         if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4636                 return false;
4637 
4638         atomic_inc(&sp->write_flooding_count);
4639         return atomic_read(&sp->write_flooding_count) >= 3;
4640 }
4641 
4642 /*
4643  * Misaligned accesses are too much trouble to fix up; also, they usually
4644  * indicate a page is not used as a page table.
4645  */
4646 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4647                                     int bytes)
4648 {
4649         unsigned offset, pte_size, misaligned;
4650 
4651         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4652                  gpa, bytes, sp->role.word);
4653 
4654         offset = offset_in_page(gpa);
4655         pte_size = sp->role.cr4_pae ? 8 : 4;
4656 
4657         /*
4658          * Sometimes, the OS only writes the last one bytes to update status
4659          * bits, for example, in linux, andb instruction is used in clear_bit().
4660          */
4661         if (!(offset & (pte_size - 1)) && bytes == 1)
4662                 return false;
4663 
4664         misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4665         misaligned |= bytes < 4;
4666 
4667         return misaligned;
4668 }
4669 
4670 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4671 {
4672         unsigned page_offset, quadrant;
4673         u64 *spte;
4674         int level;
4675 
4676         page_offset = offset_in_page(gpa);
4677         level = sp->role.level;
4678         *nspte = 1;
4679         if (!sp->role.cr4_pae) {
4680                 page_offset <<= 1;      /* 32->64 */
4681                 /*
4682                  * A 32-bit pde maps 4MB while the shadow pdes map
4683                  * only 2MB.  So we need to double the offset again
4684                  * and zap two pdes instead of one.
4685                  */
4686                 if (level == PT32_ROOT_LEVEL) {
4687                         page_offset &= ~7; /* kill rounding error */
4688                         page_offset <<= 1;
4689                         *nspte = 2;
4690                 }
4691                 quadrant = page_offset >> PAGE_SHIFT;
4692                 page_offset &= ~PAGE_MASK;
4693                 if (quadrant != sp->role.quadrant)
4694                         return NULL;
4695         }
4696 
4697         spte = &sp->spt[page_offset / sizeof(*spte)];
4698         return spte;
4699 }
4700 
4701 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4702                               const u8 *new, int bytes,
4703                               struct kvm_page_track_notifier_node *node)
4704 {
4705         gfn_t gfn = gpa >> PAGE_SHIFT;
4706         struct kvm_mmu_page *sp;
4707         LIST_HEAD(invalid_list);
4708         u64 entry, gentry, *spte;
4709         int npte;
4710         bool remote_flush, local_flush;
4711         union kvm_mmu_page_role mask = { };
4712 
4713         mask.cr0_wp = 1;
4714         mask.cr4_pae = 1;
4715         mask.nxe = 1;
4716         mask.smep_andnot_wp = 1;
4717         mask.smap_andnot_wp = 1;
4718         mask.smm = 1;
4719         mask.ad_disabled = 1;
4720 
4721         /*
4722          * If we don't have indirect shadow pages, it means no page is
4723          * write-protected, so we can exit simply.
4724          */
4725         if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4726                 return;
4727 
4728         remote_flush = local_flush = false;
4729 
4730         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4731 
4732         gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4733 
4734         /*
4735          * No need to care whether allocation memory is successful
4736          * or not since pte prefetch is skiped if it does not have
4737          * enough objects in the cache.
4738          */
4739         mmu_topup_memory_caches(vcpu);
4740 
4741         spin_lock(&vcpu->kvm->mmu_lock);
4742         ++vcpu->kvm->stat.mmu_pte_write;
4743         kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4744 
4745         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4746                 if (detect_write_misaligned(sp, gpa, bytes) ||
4747                       detect_write_flooding(sp)) {
4748                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4749                         ++vcpu->kvm->stat.mmu_flooded;
4750                         continue;
4751                 }
4752 
4753                 spte = get_written_sptes(sp, gpa, &npte);
4754                 if (!spte)
4755                         continue;
4756 
4757                 local_flush = true;
4758                 while (npte--) {
4759                         entry = *spte;
4760                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
4761                         if (gentry &&
4762                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4763                               & mask.word) && rmap_can_add(vcpu))
4764                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4765                         if (need_remote_flush(entry, *spte))
4766                                 remote_flush = true;
4767                         ++spte;
4768                 }
4769         }
4770         kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4771         kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4772         spin_unlock(&vcpu->kvm->mmu_lock);
4773 }
4774 
4775 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4776 {
4777         gpa_t gpa;
4778         int r;
4779 
4780         if (vcpu->arch.mmu.direct_map)
4781                 return 0;
4782 
4783         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4784 
4785         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4786 
4787         return r;
4788 }
4789 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4790 
4791 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4792 {
4793         LIST_HEAD(invalid_list);
4794 
4795         if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4796                 return;
4797 
4798         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4799                 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4800                         break;
4801 
4802                 ++vcpu->kvm->stat.mmu_recycled;
4803         }
4804         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4805 }
4806 
4807 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
4808                        void *insn, int insn_len)
4809 {
4810         int r, emulation_type = EMULTYPE_RETRY;
4811         enum emulation_result er;
4812         bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu);
4813 
4814         if (unlikely(error_code & PFERR_RSVD_MASK)) {
4815                 r = handle_mmio_page_fault(vcpu, cr2, direct);
4816                 if (r == RET_MMIO_PF_EMULATE) {
4817                         emulation_type = 0;
4818                         goto emulate;
4819                 }
4820                 if (r == RET_MMIO_PF_RETRY)
4821                         return 1;
4822                 if (r < 0)
4823                         return r;
4824         }
4825 
4826         r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code),
4827                                       false);
4828         if (r < 0)
4829                 return r;
4830         if (!r)
4831                 return 1;
4832 
4833         /*
4834          * Before emulating the instruction, check if the error code
4835          * was due to a RO violation while translating the guest page.
4836          * This can occur when using nested virtualization with nested
4837          * paging in both guests. If true, we simply unprotect the page
4838          * and resume the guest.
4839          *
4840          * Note: AMD only (since it supports the PFERR_GUEST_PAGE_MASK used
4841          *       in PFERR_NEXT_GUEST_PAGE)
4842          */
4843         if (vcpu->arch.mmu.direct_map &&
4844                 error_code == PFERR_NESTED_GUEST_PAGE) {
4845                 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
4846                 return 1;
4847         }
4848 
4849         if (mmio_info_in_cache(vcpu, cr2, direct))
4850                 emulation_type = 0;
4851 emulate:
4852         er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4853 
4854         switch (er) {
4855         case EMULATE_DONE:
4856                 return 1;
4857         case EMULATE_USER_EXIT:
4858                 ++vcpu->stat.mmio_exits;
4859                 /* fall through */
4860         case EMULATE_FAIL:
4861                 return 0;
4862         default:
4863                 BUG();
4864         }
4865 }
4866 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4867 
4868 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4869 {
4870         vcpu->arch.mmu.invlpg(vcpu, gva);
4871         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4872         ++vcpu->stat.invlpg;
4873 }
4874 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4875 
4876 void kvm_enable_tdp(void)
4877 {
4878         tdp_enabled = true;
4879 }
4880 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4881 
4882 void kvm_disable_tdp(void)
4883 {
4884         tdp_enabled = false;
4885 }
4886 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4887 
4888 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4889 {
4890         free_page((unsigned long)vcpu->arch.mmu.pae_root);
4891         if (vcpu->arch.mmu.lm_root != NULL)
4892                 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4893 }
4894 
4895 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4896 {
4897         struct page *page;
4898         int i;
4899 
4900         /*
4901          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4902          * Therefore we need to allocate shadow page tables in the first
4903          * 4GB of memory, which happens to fit the DMA32 zone.
4904          */
4905         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4906         if (!page)
4907                 return -ENOMEM;
4908 
4909         vcpu->arch.mmu.pae_root = page_address(page);
4910         for (i = 0; i < 4; ++i)
4911                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4912 
4913         return 0;
4914 }
4915 
4916 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4917 {
4918         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4919         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4920         vcpu->arch.mmu.translate_gpa = translate_gpa;
4921         vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4922 
4923         return alloc_mmu_pages(vcpu);
4924 }
4925 
4926 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4927 {
4928         MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4929 
4930         init_kvm_mmu(vcpu);
4931 }
4932 
4933 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
4934                         struct kvm_memory_slot *slot,
4935                         struct kvm_page_track_notifier_node *node)
4936 {
4937         kvm_mmu_invalidate_zap_all_pages(kvm);
4938 }
4939 
4940 void kvm_mmu_init_vm(struct kvm *kvm)
4941 {
4942         struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4943 
4944         node->track_write = kvm_mmu_pte_write;
4945         node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
4946         kvm_page_track_register_notifier(kvm, node);
4947 }
4948 
4949 void kvm_mmu_uninit_vm(struct kvm *kvm)
4950 {
4951         struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4952 
4953         kvm_page_track_unregister_notifier(kvm, node);
4954 }
4955 
4956 /* The return value indicates if tlb flush on all vcpus is needed. */
4957 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
4958 
4959 /* The caller should hold mmu-lock before calling this function. */
4960 static bool
4961 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4962                         slot_level_handler fn, int start_level, int end_level,
4963                         gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4964 {
4965         struct slot_rmap_walk_iterator iterator;
4966         bool flush = false;
4967 
4968         for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4969                         end_gfn, &iterator) {
4970                 if (iterator.rmap)
4971                         flush |= fn(kvm, iterator.rmap);
4972 
4973                 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4974                         if (flush && lock_flush_tlb) {
4975                                 kvm_flush_remote_tlbs(kvm);
4976                                 flush = false;
4977                         }
4978                         cond_resched_lock(&kvm->mmu_lock);
4979                 }
4980         }
4981 
4982         if (flush && lock_flush_tlb) {
4983                 kvm_flush_remote_tlbs(kvm);
4984                 flush = false;
4985         }
4986 
4987         return flush;
4988 }
4989 
4990 static bool
4991 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4992                   slot_level_handler fn, int start_level, int end_level,
4993                   bool lock_flush_tlb)
4994 {
4995         return slot_handle_level_range(kvm, memslot, fn, start_level,
4996                         end_level, memslot->base_gfn,
4997                         memslot->base_gfn + memslot->npages - 1,
4998                         lock_flush_tlb);
4999 }
5000 
5001 static bool
5002 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5003                       slot_level_handler fn, bool lock_flush_tlb)
5004 {
5005         return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5006                                  PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5007 }
5008 
5009 static bool
5010 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5011                         slot_level_handler fn, bool lock_flush_tlb)
5012 {
5013         return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
5014                                  PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5015 }
5016 
5017 static bool
5018 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5019                  slot_level_handler fn, bool lock_flush_tlb)
5020 {
5021         return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5022                                  PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
5023 }
5024 
5025 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5026 {
5027         struct kvm_memslots *slots;
5028         struct kvm_memory_slot *memslot;
5029         int i;
5030 
5031         spin_lock(&kvm->mmu_lock);
5032         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5033                 slots = __kvm_memslots(kvm, i);
5034                 kvm_for_each_memslot(memslot, slots) {
5035                         gfn_t start, end;
5036 
5037                         start = max(gfn_start, memslot->base_gfn);
5038                         end = min(gfn_end, memslot->base_gfn + memslot->npages);
5039                         if (start >= end)
5040                                 continue;
5041 
5042                         slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5043                                                 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
5044                                                 start, end - 1, true);
5045                 }
5046         }
5047 
5048         spin_unlock(&kvm->mmu_lock);
5049 }
5050 
5051 static bool slot_rmap_write_protect(struct kvm *kvm,
5052                                     struct kvm_rmap_head *rmap_head)
5053 {
5054         return __rmap_write_protect(kvm, rmap_head, false);
5055 }
5056 
5057 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5058                                       struct kvm_memory_slot *memslot)
5059 {
5060         bool flush;
5061 
5062         spin_lock(&kvm->mmu_lock);
5063         flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
5064                                       false);
5065         spin_unlock(&kvm->mmu_lock);
5066 
5067         /*
5068          * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5069          * which do tlb flush out of mmu-lock should be serialized by
5070          * kvm->slots_lock otherwise tlb flush would be missed.
5071          */
5072         lockdep_assert_held(&kvm->slots_lock);
5073 
5074         /*
5075          * We can flush all the TLBs out of the mmu lock without TLB
5076          * corruption since we just change the spte from writable to
5077          * readonly so that we only need to care the case of changing
5078          * spte from present to present (changing the spte from present
5079          * to nonpresent will flush all the TLBs immediately), in other
5080          * words, the only case we care is mmu_spte_update() where we
5081          * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5082          * instead of PT_WRITABLE_MASK, that means it does not depend
5083          * on PT_WRITABLE_MASK anymore.
5084          */
5085         if (flush)
5086                 kvm_flush_remote_tlbs(kvm);
5087 }
5088 
5089 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5090                                          struct kvm_rmap_head *rmap_head)
5091 {
5092         u64 *sptep;
5093         struct rmap_iterator iter;
5094         int need_tlb_flush = 0;
5095         kvm_pfn_t pfn;
5096         struct kvm_mmu_page *sp;
5097 
5098 restart:
5099         for_each_rmap_spte(rmap_head, &iter, sptep) {
5100                 sp = page_header(__pa(sptep));
5101                 pfn = spte_to_pfn(*sptep);
5102 
5103                 /*
5104                  * We cannot do huge page mapping for indirect shadow pages,
5105                  * which are found on the last rmap (level = 1) when not using
5106                  * tdp; such shadow pages are synced with the page table in
5107                  * the guest, and the guest page table is using 4K page size
5108                  * mapping if the indirect sp has level = 1.
5109                  */
5110                 if (sp->role.direct &&
5111                         !kvm_is_reserved_pfn(pfn) &&
5112                         PageTransCompoundMap(pfn_to_page(pfn))) {
5113                         drop_spte(kvm, sptep);
5114                         need_tlb_flush = 1;
5115                         goto restart;
5116                 }
5117         }
5118 
5119         return need_tlb_flush;
5120 }
5121 
5122 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5123                                    const struct kvm_memory_slot *memslot)
5124 {
5125         /* FIXME: const-ify all uses of struct kvm_memory_slot.  */
5126         spin_lock(&kvm->mmu_lock);
5127         slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5128                          kvm_mmu_zap_collapsible_spte, true);
5129         spin_unlock(&kvm->mmu_lock);
5130 }
5131 
5132 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5133                                    struct kvm_memory_slot *memslot)
5134 {
5135         bool flush;
5136 
5137         spin_lock(&kvm->mmu_lock);
5138         flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5139         spin_unlock(&kvm->mmu_lock);
5140 
5141         lockdep_assert_held(&kvm->slots_lock);
5142 
5143         /*
5144          * It's also safe to flush TLBs out of mmu lock here as currently this
5145          * function is only used for dirty logging, in which case flushing TLB
5146          * out of mmu lock also guarantees no dirty pages will be lost in
5147          * dirty_bitmap.
5148          */
5149         if (flush)
5150                 kvm_flush_remote_tlbs(kvm);
5151 }
5152 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5153 
5154 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5155                                         struct kvm_memory_slot *memslot)
5156 {
5157         bool flush;
5158 
5159         spin_lock(&kvm->mmu_lock);
5160         flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5161                                         false);
5162         spin_unlock(&kvm->mmu_lock);
5163 
5164         /* see kvm_mmu_slot_remove_write_access */
5165         lockdep_assert_held(&kvm->slots_lock);
5166 
5167         if (flush)
5168                 kvm_flush_remote_tlbs(kvm);
5169 }
5170 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5171 
5172 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5173                             struct kvm_memory_slot *memslot)
5174 {
5175         bool flush;
5176 
5177         spin_lock(&kvm->mmu_lock);
5178         flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5179         spin_unlock(&kvm->mmu_lock);
5180 
5181         lockdep_assert_held(&kvm->slots_lock);
5182 
5183         /* see kvm_mmu_slot_leaf_clear_dirty */
5184         if (flush)
5185                 kvm_flush_remote_tlbs(kvm);
5186 }
5187 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5188 
5189 #define BATCH_ZAP_PAGES 10
5190 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5191 {
5192         struct kvm_mmu_page *sp, *node;
5193         int batch = 0;
5194 
5195 restart:
5196         list_for_each_entry_safe_reverse(sp, node,
5197               &kvm->arch.active_mmu_pages, link) {
5198                 int ret;
5199 
5200                 /*
5201                  * No obsolete page exists before new created page since
5202                  * active_mmu_pages is the FIFO list.
5203                  */
5204                 if (!is_obsolete_sp(kvm, sp))
5205                         break;
5206 
5207                 /*
5208                  * Since we are reversely walking the list and the invalid
5209                  * list will be moved to the head, skip the invalid page
5210                  * can help us to avoid the infinity list walking.
5211                  */
5212                 if (sp->role.invalid)
5213                         continue;
5214 
5215                 /*
5216                  * Need not flush tlb since we only zap the sp with invalid
5217                  * generation number.
5218                  */
5219                 if (batch >= BATCH_ZAP_PAGES &&
5220                       cond_resched_lock(&kvm->mmu_lock)) {
5221                         batch = 0;
5222                         goto restart;
5223                 }
5224 
5225                 ret = kvm_mmu_prepare_zap_page(kvm, sp,
5226                                 &kvm->arch.zapped_obsolete_pages);
5227                 batch += ret;
5228 
5229                 if (ret)
5230                         goto restart;
5231         }
5232 
5233         /*
5234          * Should flush tlb before free page tables since lockless-walking
5235          * may use the pages.
5236          */
5237         kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5238 }
5239 
5240 /*
5241  * Fast invalidate all shadow pages and use lock-break technique
5242  * to zap obsolete pages.
5243  *
5244  * It's required when memslot is being deleted or VM is being
5245  * destroyed, in these cases, we should ensure that KVM MMU does
5246  * not use any resource of the being-deleted slot or all slots
5247  * after calling the function.
5248  */
5249 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
5250 {
5251         spin_lock(&kvm->mmu_lock);
5252         trace_kvm_mmu_invalidate_zap_all_pages(kvm);
5253         kvm->arch.mmu_valid_gen++;
5254 
5255         /*
5256          * Notify all vcpus to reload its shadow page table
5257          * and flush TLB. Then all vcpus will switch to new
5258          * shadow page table with the new mmu_valid_gen.
5259          *
5260          * Note: we should do this under the protection of
5261          * mmu-lock, otherwise, vcpu would purge shadow page
5262          * but miss tlb flush.
5263          */
5264         kvm_reload_remote_mmus(kvm);
5265 
5266         kvm_zap_obsolete_pages(kvm);
5267         spin_unlock(&kvm->mmu_lock);
5268 }
5269 
5270 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5271 {
5272         return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5273 }
5274 
5275 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
5276 {
5277         /*
5278          * The very rare case: if the generation-number is round,
5279          * zap all shadow pages.
5280          */
5281         if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
5282                 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5283                 kvm_mmu_invalidate_zap_all_pages(kvm);
5284         }
5285 }
5286 
5287 static unsigned long
5288 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5289 {
5290         struct kvm *kvm;
5291         int nr_to_scan = sc->nr_to_scan;
5292         unsigned long freed = 0;
5293 
5294         spin_lock(&kvm_lock);
5295 
5296         list_for_each_entry(kvm, &vm_list, vm_list) {
5297                 int idx;
5298                 LIST_HEAD(invalid_list);
5299 
5300                 /*
5301                  * Never scan more than sc->nr_to_scan VM instances.
5302                  * Will not hit this condition practically since we do not try
5303                  * to shrink more than one VM and it is very unlikely to see
5304                  * !n_used_mmu_pages so many times.
5305                  */
5306                 if (!nr_to_scan--)
5307                         break;
5308                 /*
5309                  * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5310                  * here. We may skip a VM instance errorneosly, but we do not
5311                  * want to shrink a VM that only started to populate its MMU
5312                  * anyway.
5313                  */
5314                 if (!kvm->arch.n_used_mmu_pages &&
5315                       !kvm_has_zapped_obsolete_pages(kvm))
5316                         continue;
5317 
5318                 idx = srcu_read_lock(&kvm->srcu);
5319                 spin_lock(&kvm->mmu_lock);
5320 
5321                 if (kvm_has_zapped_obsolete_pages(kvm)) {
5322                         kvm_mmu_commit_zap_page(kvm,
5323                               &kvm->arch.zapped_obsolete_pages);
5324                         goto unlock;
5325                 }
5326 
5327                 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5328                         freed++;
5329                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5330 
5331 unlock:
5332                 spin_unlock(&kvm->mmu_lock);
5333                 srcu_read_unlock(&kvm->srcu, idx);
5334 
5335                 /*
5336                  * unfair on small ones
5337                  * per-vm shrinkers cry out
5338                  * sadness comes quickly
5339                  */
5340                 list_move_tail(&kvm->vm_list, &vm_list);
5341                 break;
5342         }
5343 
5344         spin_unlock(&kvm_lock);
5345         return freed;
5346 }
5347 
5348 static unsigned long
5349 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5350 {
5351         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5352 }
5353 
5354 static struct shrinker mmu_shrinker = {
5355         .count_objects = mmu_shrink_count,
5356         .scan_objects = mmu_shrink_scan,
5357         .seeks = DEFAULT_SEEKS * 10,
5358 };
5359 
5360 static void mmu_destroy_caches(void)
5361 {
5362         if (pte_list_desc_cache)
5363                 kmem_cache_destroy(pte_list_desc_cache);
5364         if (mmu_page_header_cache)
5365                 kmem_cache_destroy(mmu_page_header_cache);
5366 }
5367 
5368 int kvm_mmu_module_init(void)
5369 {
5370         kvm_mmu_clear_all_pte_masks();
5371 
5372         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5373                                             sizeof(struct pte_list_desc),
5374                                             0, 0, NULL);
5375         if (!pte_list_desc_cache)
5376                 goto nomem;
5377 
5378         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5379                                                   sizeof(struct kvm_mmu_page),
5380                                                   0, 0, NULL);
5381         if (!mmu_page_header_cache)
5382                 goto nomem;
5383 
5384         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5385                 goto nomem;
5386 
5387         register_shrinker(&mmu_shrinker);
5388 
5389         return 0;
5390 
5391 nomem:
5392         mmu_destroy_caches();
5393         return -ENOMEM;
5394 }
5395 
5396 /*
5397  * Caculate mmu pages needed for kvm.
5398  */
5399 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5400 {
5401         unsigned int nr_mmu_pages;
5402         unsigned int  nr_pages = 0;
5403         struct kvm_memslots *slots;
5404         struct kvm_memory_slot *memslot;
5405         int i;
5406 
5407         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5408                 slots = __kvm_memslots(kvm, i);
5409 
5410                 kvm_for_each_memslot(memslot, slots)
5411                         nr_pages += memslot->npages;
5412         }
5413 
5414         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5415         nr_mmu_pages = max(nr_mmu_pages,
5416                            (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5417 
5418         return nr_mmu_pages;
5419 }
5420 
5421 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5422 {
5423         kvm_mmu_unload(vcpu);
5424         free_mmu_pages(vcpu);
5425         mmu_free_memory_caches(vcpu);
5426 }
5427 
5428 void kvm_mmu_module_exit(void)
5429 {
5430         mmu_destroy_caches();
5431         percpu_counter_destroy(&kvm_total_used_mmu_pages);
5432         unregister_shrinker(&mmu_shrinker);
5433         mmu_audit_disable();
5434 }
5435 

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