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TOMOYO Linux Cross Reference
Linux/arch/x86/kvm/vmx.c

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  1 /*
  2  * Kernel-based Virtual Machine driver for Linux
  3  *
  4  * This module enables machines with Intel VT-x extensions to run virtual
  5  * machines without emulation or binary translation.
  6  *
  7  * Copyright (C) 2006 Qumranet, Inc.
  8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  9  *
 10  * Authors:
 11  *   Avi Kivity   <avi@qumranet.com>
 12  *   Yaniv Kamay  <yaniv@qumranet.com>
 13  *
 14  * This work is licensed under the terms of the GNU GPL, version 2.  See
 15  * the COPYING file in the top-level directory.
 16  *
 17  */
 18 
 19 #include "irq.h"
 20 #include "mmu.h"
 21 #include "cpuid.h"
 22 
 23 #include <linux/kvm_host.h>
 24 #include <linux/module.h>
 25 #include <linux/kernel.h>
 26 #include <linux/mm.h>
 27 #include <linux/highmem.h>
 28 #include <linux/sched.h>
 29 #include <linux/moduleparam.h>
 30 #include <linux/mod_devicetable.h>
 31 #include <linux/ftrace_event.h>
 32 #include <linux/slab.h>
 33 #include <linux/tboot.h>
 34 #include <linux/hrtimer.h>
 35 #include "kvm_cache_regs.h"
 36 #include "x86.h"
 37 
 38 #include <asm/io.h>
 39 #include <asm/desc.h>
 40 #include <asm/vmx.h>
 41 #include <asm/virtext.h>
 42 #include <asm/mce.h>
 43 #include <asm/i387.h>
 44 #include <asm/xcr.h>
 45 #include <asm/perf_event.h>
 46 #include <asm/debugreg.h>
 47 #include <asm/kexec.h>
 48 #include <asm/apic.h>
 49 
 50 #include "trace.h"
 51 
 52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
 53 #define __ex_clear(x, reg) \
 54         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
 55 
 56 MODULE_AUTHOR("Qumranet");
 57 MODULE_LICENSE("GPL");
 58 
 59 static const struct x86_cpu_id vmx_cpu_id[] = {
 60         X86_FEATURE_MATCH(X86_FEATURE_VMX),
 61         {}
 62 };
 63 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
 64 
 65 static bool __read_mostly enable_vpid = 1;
 66 module_param_named(vpid, enable_vpid, bool, 0444);
 67 
 68 static bool __read_mostly flexpriority_enabled = 1;
 69 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
 70 
 71 static bool __read_mostly enable_ept = 1;
 72 module_param_named(ept, enable_ept, bool, S_IRUGO);
 73 
 74 static bool __read_mostly enable_unrestricted_guest = 1;
 75 module_param_named(unrestricted_guest,
 76                         enable_unrestricted_guest, bool, S_IRUGO);
 77 
 78 static bool __read_mostly enable_ept_ad_bits = 1;
 79 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
 80 
 81 static bool __read_mostly emulate_invalid_guest_state = true;
 82 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 83 
 84 static bool __read_mostly vmm_exclusive = 1;
 85 module_param(vmm_exclusive, bool, S_IRUGO);
 86 
 87 static bool __read_mostly fasteoi = 1;
 88 module_param(fasteoi, bool, S_IRUGO);
 89 
 90 static bool __read_mostly enable_apicv = 1;
 91 module_param(enable_apicv, bool, S_IRUGO);
 92 
 93 static bool __read_mostly enable_shadow_vmcs = 1;
 94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 95 /*
 96  * If nested=1, nested virtualization is supported, i.e., guests may use
 97  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 98  * use VMX instructions.
 99  */
100 static bool __read_mostly nested = 0;
101 module_param(nested, bool, S_IRUGO);
102 
103 static u64 __read_mostly host_xss;
104 
105 static bool __read_mostly enable_pml = 1;
106 module_param_named(pml, enable_pml, bool, S_IRUGO);
107 
108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
110 #define KVM_VM_CR0_ALWAYS_ON                                            \
111         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
112 #define KVM_CR4_GUEST_OWNED_BITS                                      \
113         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
114          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
115 
116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118 
119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120 
121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122 
123 /*
124  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125  * ple_gap:    upper bound on the amount of time between two successive
126  *             executions of PAUSE in a loop. Also indicate if ple enabled.
127  *             According to test, this time is usually smaller than 128 cycles.
128  * ple_window: upper bound on the amount of time a guest is allowed to execute
129  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
130  *             less than 2^12 cycles
131  * Time is measured based on a counter that runs at the same rate as the TSC,
132  * refer SDM volume 3b section 21.6.13 & 22.1.3.
133  */
134 #define KVM_VMX_DEFAULT_PLE_GAP           128
135 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
139                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140 
141 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142 module_param(ple_gap, int, S_IRUGO);
143 
144 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145 module_param(ple_window, int, S_IRUGO);
146 
147 /* Default doubles per-vcpu window every exit. */
148 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149 module_param(ple_window_grow, int, S_IRUGO);
150 
151 /* Default resets per-vcpu window every exit to ple_window. */
152 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153 module_param(ple_window_shrink, int, S_IRUGO);
154 
155 /* Default is to compute the maximum so we can never overflow. */
156 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158 module_param(ple_window_max, int, S_IRUGO);
159 
160 extern const ulong vmx_return;
161 
162 #define NR_AUTOLOAD_MSRS 8
163 #define VMCS02_POOL_SIZE 1
164 
165 struct vmcs {
166         u32 revision_id;
167         u32 abort;
168         char data[0];
169 };
170 
171 /*
172  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174  * loaded on this CPU (so we can clear them if the CPU goes down).
175  */
176 struct loaded_vmcs {
177         struct vmcs *vmcs;
178         int cpu;
179         int launched;
180         struct list_head loaded_vmcss_on_cpu_link;
181 };
182 
183 struct shared_msr_entry {
184         unsigned index;
185         u64 data;
186         u64 mask;
187 };
188 
189 /*
190  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195  * More than one of these structures may exist, if L1 runs multiple L2 guests.
196  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197  * underlying hardware which will be used to run L2.
198  * This structure is packed to ensure that its layout is identical across
199  * machines (necessary for live migration).
200  * If there are changes in this struct, VMCS12_REVISION must be changed.
201  */
202 typedef u64 natural_width;
203 struct __packed vmcs12 {
204         /* According to the Intel spec, a VMCS region must start with the
205          * following two fields. Then follow implementation-specific data.
206          */
207         u32 revision_id;
208         u32 abort;
209 
210         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211         u32 padding[7]; /* room for future expansion */
212 
213         u64 io_bitmap_a;
214         u64 io_bitmap_b;
215         u64 msr_bitmap;
216         u64 vm_exit_msr_store_addr;
217         u64 vm_exit_msr_load_addr;
218         u64 vm_entry_msr_load_addr;
219         u64 tsc_offset;
220         u64 virtual_apic_page_addr;
221         u64 apic_access_addr;
222         u64 posted_intr_desc_addr;
223         u64 ept_pointer;
224         u64 eoi_exit_bitmap0;
225         u64 eoi_exit_bitmap1;
226         u64 eoi_exit_bitmap2;
227         u64 eoi_exit_bitmap3;
228         u64 xss_exit_bitmap;
229         u64 guest_physical_address;
230         u64 vmcs_link_pointer;
231         u64 guest_ia32_debugctl;
232         u64 guest_ia32_pat;
233         u64 guest_ia32_efer;
234         u64 guest_ia32_perf_global_ctrl;
235         u64 guest_pdptr0;
236         u64 guest_pdptr1;
237         u64 guest_pdptr2;
238         u64 guest_pdptr3;
239         u64 guest_bndcfgs;
240         u64 host_ia32_pat;
241         u64 host_ia32_efer;
242         u64 host_ia32_perf_global_ctrl;
243         u64 padding64[8]; /* room for future expansion */
244         /*
245          * To allow migration of L1 (complete with its L2 guests) between
246          * machines of different natural widths (32 or 64 bit), we cannot have
247          * unsigned long fields with no explict size. We use u64 (aliased
248          * natural_width) instead. Luckily, x86 is little-endian.
249          */
250         natural_width cr0_guest_host_mask;
251         natural_width cr4_guest_host_mask;
252         natural_width cr0_read_shadow;
253         natural_width cr4_read_shadow;
254         natural_width cr3_target_value0;
255         natural_width cr3_target_value1;
256         natural_width cr3_target_value2;
257         natural_width cr3_target_value3;
258         natural_width exit_qualification;
259         natural_width guest_linear_address;
260         natural_width guest_cr0;
261         natural_width guest_cr3;
262         natural_width guest_cr4;
263         natural_width guest_es_base;
264         natural_width guest_cs_base;
265         natural_width guest_ss_base;
266         natural_width guest_ds_base;
267         natural_width guest_fs_base;
268         natural_width guest_gs_base;
269         natural_width guest_ldtr_base;
270         natural_width guest_tr_base;
271         natural_width guest_gdtr_base;
272         natural_width guest_idtr_base;
273         natural_width guest_dr7;
274         natural_width guest_rsp;
275         natural_width guest_rip;
276         natural_width guest_rflags;
277         natural_width guest_pending_dbg_exceptions;
278         natural_width guest_sysenter_esp;
279         natural_width guest_sysenter_eip;
280         natural_width host_cr0;
281         natural_width host_cr3;
282         natural_width host_cr4;
283         natural_width host_fs_base;
284         natural_width host_gs_base;
285         natural_width host_tr_base;
286         natural_width host_gdtr_base;
287         natural_width host_idtr_base;
288         natural_width host_ia32_sysenter_esp;
289         natural_width host_ia32_sysenter_eip;
290         natural_width host_rsp;
291         natural_width host_rip;
292         natural_width paddingl[8]; /* room for future expansion */
293         u32 pin_based_vm_exec_control;
294         u32 cpu_based_vm_exec_control;
295         u32 exception_bitmap;
296         u32 page_fault_error_code_mask;
297         u32 page_fault_error_code_match;
298         u32 cr3_target_count;
299         u32 vm_exit_controls;
300         u32 vm_exit_msr_store_count;
301         u32 vm_exit_msr_load_count;
302         u32 vm_entry_controls;
303         u32 vm_entry_msr_load_count;
304         u32 vm_entry_intr_info_field;
305         u32 vm_entry_exception_error_code;
306         u32 vm_entry_instruction_len;
307         u32 tpr_threshold;
308         u32 secondary_vm_exec_control;
309         u32 vm_instruction_error;
310         u32 vm_exit_reason;
311         u32 vm_exit_intr_info;
312         u32 vm_exit_intr_error_code;
313         u32 idt_vectoring_info_field;
314         u32 idt_vectoring_error_code;
315         u32 vm_exit_instruction_len;
316         u32 vmx_instruction_info;
317         u32 guest_es_limit;
318         u32 guest_cs_limit;
319         u32 guest_ss_limit;
320         u32 guest_ds_limit;
321         u32 guest_fs_limit;
322         u32 guest_gs_limit;
323         u32 guest_ldtr_limit;
324         u32 guest_tr_limit;
325         u32 guest_gdtr_limit;
326         u32 guest_idtr_limit;
327         u32 guest_es_ar_bytes;
328         u32 guest_cs_ar_bytes;
329         u32 guest_ss_ar_bytes;
330         u32 guest_ds_ar_bytes;
331         u32 guest_fs_ar_bytes;
332         u32 guest_gs_ar_bytes;
333         u32 guest_ldtr_ar_bytes;
334         u32 guest_tr_ar_bytes;
335         u32 guest_interruptibility_info;
336         u32 guest_activity_state;
337         u32 guest_sysenter_cs;
338         u32 host_ia32_sysenter_cs;
339         u32 vmx_preemption_timer_value;
340         u32 padding32[7]; /* room for future expansion */
341         u16 virtual_processor_id;
342         u16 posted_intr_nv;
343         u16 guest_es_selector;
344         u16 guest_cs_selector;
345         u16 guest_ss_selector;
346         u16 guest_ds_selector;
347         u16 guest_fs_selector;
348         u16 guest_gs_selector;
349         u16 guest_ldtr_selector;
350         u16 guest_tr_selector;
351         u16 guest_intr_status;
352         u16 host_es_selector;
353         u16 host_cs_selector;
354         u16 host_ss_selector;
355         u16 host_ds_selector;
356         u16 host_fs_selector;
357         u16 host_gs_selector;
358         u16 host_tr_selector;
359 };
360 
361 /*
362  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365  */
366 #define VMCS12_REVISION 0x11e57ed0
367 
368 /*
369  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371  * current implementation, 4K are reserved to avoid future complications.
372  */
373 #define VMCS12_SIZE 0x1000
374 
375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
376 struct vmcs02_list {
377         struct list_head list;
378         gpa_t vmptr;
379         struct loaded_vmcs vmcs02;
380 };
381 
382 /*
383  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385  */
386 struct nested_vmx {
387         /* Has the level1 guest done vmxon? */
388         bool vmxon;
389         gpa_t vmxon_ptr;
390 
391         /* The guest-physical address of the current VMCS L1 keeps for L2 */
392         gpa_t current_vmptr;
393         /* The host-usable pointer to the above */
394         struct page *current_vmcs12_page;
395         struct vmcs12 *current_vmcs12;
396         struct vmcs *current_shadow_vmcs;
397         /*
398          * Indicates if the shadow vmcs must be updated with the
399          * data hold by vmcs12
400          */
401         bool sync_shadow_vmcs;
402 
403         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404         struct list_head vmcs02_pool;
405         int vmcs02_num;
406         u64 vmcs01_tsc_offset;
407         /* L2 must run next, and mustn't decide to exit to L1. */
408         bool nested_run_pending;
409         /*
410          * Guest pages referred to in vmcs02 with host-physical pointers, so
411          * we must keep them pinned while L2 runs.
412          */
413         struct page *apic_access_page;
414         struct page *virtual_apic_page;
415         struct page *pi_desc_page;
416         struct pi_desc *pi_desc;
417         bool pi_pending;
418         u16 posted_intr_nv;
419         u64 msr_ia32_feature_control;
420 
421         struct hrtimer preemption_timer;
422         bool preemption_timer_expired;
423 
424         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425         u64 vmcs01_debugctl;
426 
427         u32 nested_vmx_procbased_ctls_low;
428         u32 nested_vmx_procbased_ctls_high;
429         u32 nested_vmx_true_procbased_ctls_low;
430         u32 nested_vmx_secondary_ctls_low;
431         u32 nested_vmx_secondary_ctls_high;
432         u32 nested_vmx_pinbased_ctls_low;
433         u32 nested_vmx_pinbased_ctls_high;
434         u32 nested_vmx_exit_ctls_low;
435         u32 nested_vmx_exit_ctls_high;
436         u32 nested_vmx_true_exit_ctls_low;
437         u32 nested_vmx_entry_ctls_low;
438         u32 nested_vmx_entry_ctls_high;
439         u32 nested_vmx_true_entry_ctls_low;
440         u32 nested_vmx_misc_low;
441         u32 nested_vmx_misc_high;
442         u32 nested_vmx_ept_caps;
443 };
444 
445 #define POSTED_INTR_ON  0
446 /* Posted-Interrupt Descriptor */
447 struct pi_desc {
448         u32 pir[8];     /* Posted interrupt requested */
449         u32 control;    /* bit 0 of control is outstanding notification bit */
450         u32 rsvd[7];
451 } __aligned(64);
452 
453 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454 {
455         return test_and_set_bit(POSTED_INTR_ON,
456                         (unsigned long *)&pi_desc->control);
457 }
458 
459 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460 {
461         return test_and_clear_bit(POSTED_INTR_ON,
462                         (unsigned long *)&pi_desc->control);
463 }
464 
465 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466 {
467         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468 }
469 
470 struct vcpu_vmx {
471         struct kvm_vcpu       vcpu;
472         unsigned long         host_rsp;
473         u8                    fail;
474         bool                  nmi_known_unmasked;
475         u32                   exit_intr_info;
476         u32                   idt_vectoring_info;
477         ulong                 rflags;
478         struct shared_msr_entry *guest_msrs;
479         int                   nmsrs;
480         int                   save_nmsrs;
481         unsigned long         host_idt_base;
482 #ifdef CONFIG_X86_64
483         u64                   msr_host_kernel_gs_base;
484         u64                   msr_guest_kernel_gs_base;
485 #endif
486         u32 vm_entry_controls_shadow;
487         u32 vm_exit_controls_shadow;
488         /*
489          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490          * non-nested (L1) guest, it always points to vmcs01. For a nested
491          * guest (L2), it points to a different VMCS.
492          */
493         struct loaded_vmcs    vmcs01;
494         struct loaded_vmcs   *loaded_vmcs;
495         bool                  __launched; /* temporary, used in vmx_vcpu_run */
496         struct msr_autoload {
497                 unsigned nr;
498                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500         } msr_autoload;
501         struct {
502                 int           loaded;
503                 u16           fs_sel, gs_sel, ldt_sel;
504 #ifdef CONFIG_X86_64
505                 u16           ds_sel, es_sel;
506 #endif
507                 int           gs_ldt_reload_needed;
508                 int           fs_reload_needed;
509                 u64           msr_host_bndcfgs;
510                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
511         } host_state;
512         struct {
513                 int vm86_active;
514                 ulong save_rflags;
515                 struct kvm_segment segs[8];
516         } rmode;
517         struct {
518                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
519                 struct kvm_save_segment {
520                         u16 selector;
521                         unsigned long base;
522                         u32 limit;
523                         u32 ar;
524                 } seg[8];
525         } segment_cache;
526         int vpid;
527         bool emulation_required;
528 
529         /* Support for vnmi-less CPUs */
530         int soft_vnmi_blocked;
531         ktime_t entry_time;
532         s64 vnmi_blocked_time;
533         u32 exit_reason;
534 
535         bool rdtscp_enabled;
536 
537         /* Posted interrupt descriptor */
538         struct pi_desc pi_desc;
539 
540         /* Support for a guest hypervisor (nested VMX) */
541         struct nested_vmx nested;
542 
543         /* Dynamic PLE window. */
544         int ple_window;
545         bool ple_window_dirty;
546 
547         /* Support for PML */
548 #define PML_ENTITY_NUM          512
549         struct page *pml_pg;
550 };
551 
552 enum segment_cache_field {
553         SEG_FIELD_SEL = 0,
554         SEG_FIELD_BASE = 1,
555         SEG_FIELD_LIMIT = 2,
556         SEG_FIELD_AR = 3,
557 
558         SEG_FIELD_NR = 4
559 };
560 
561 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562 {
563         return container_of(vcpu, struct vcpu_vmx, vcpu);
564 }
565 
566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
568 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
569                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
570 
571 
572 static unsigned long shadow_read_only_fields[] = {
573         /*
574          * We do NOT shadow fields that are modified when L0
575          * traps and emulates any vmx instruction (e.g. VMPTRLD,
576          * VMXON...) executed by L1.
577          * For example, VM_INSTRUCTION_ERROR is read
578          * by L1 if a vmx instruction fails (part of the error path).
579          * Note the code assumes this logic. If for some reason
580          * we start shadowing these fields then we need to
581          * force a shadow sync when L0 emulates vmx instructions
582          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583          * by nested_vmx_failValid)
584          */
585         VM_EXIT_REASON,
586         VM_EXIT_INTR_INFO,
587         VM_EXIT_INSTRUCTION_LEN,
588         IDT_VECTORING_INFO_FIELD,
589         IDT_VECTORING_ERROR_CODE,
590         VM_EXIT_INTR_ERROR_CODE,
591         EXIT_QUALIFICATION,
592         GUEST_LINEAR_ADDRESS,
593         GUEST_PHYSICAL_ADDRESS
594 };
595 static int max_shadow_read_only_fields =
596         ARRAY_SIZE(shadow_read_only_fields);
597 
598 static unsigned long shadow_read_write_fields[] = {
599         TPR_THRESHOLD,
600         GUEST_RIP,
601         GUEST_RSP,
602         GUEST_CR0,
603         GUEST_CR3,
604         GUEST_CR4,
605         GUEST_INTERRUPTIBILITY_INFO,
606         GUEST_RFLAGS,
607         GUEST_CS_SELECTOR,
608         GUEST_CS_AR_BYTES,
609         GUEST_CS_LIMIT,
610         GUEST_CS_BASE,
611         GUEST_ES_BASE,
612         GUEST_BNDCFGS,
613         CR0_GUEST_HOST_MASK,
614         CR0_READ_SHADOW,
615         CR4_READ_SHADOW,
616         TSC_OFFSET,
617         EXCEPTION_BITMAP,
618         CPU_BASED_VM_EXEC_CONTROL,
619         VM_ENTRY_EXCEPTION_ERROR_CODE,
620         VM_ENTRY_INTR_INFO_FIELD,
621         VM_ENTRY_INSTRUCTION_LEN,
622         VM_ENTRY_EXCEPTION_ERROR_CODE,
623         HOST_FS_BASE,
624         HOST_GS_BASE,
625         HOST_FS_SELECTOR,
626         HOST_GS_SELECTOR
627 };
628 static int max_shadow_read_write_fields =
629         ARRAY_SIZE(shadow_read_write_fields);
630 
631 static const unsigned short vmcs_field_to_offset_table[] = {
632         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
633         FIELD(POSTED_INTR_NV, posted_intr_nv),
634         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
642         FIELD(GUEST_INTR_STATUS, guest_intr_status),
643         FIELD(HOST_ES_SELECTOR, host_es_selector),
644         FIELD(HOST_CS_SELECTOR, host_cs_selector),
645         FIELD(HOST_SS_SELECTOR, host_ss_selector),
646         FIELD(HOST_DS_SELECTOR, host_ds_selector),
647         FIELD(HOST_FS_SELECTOR, host_fs_selector),
648         FIELD(HOST_GS_SELECTOR, host_gs_selector),
649         FIELD(HOST_TR_SELECTOR, host_tr_selector),
650         FIELD64(IO_BITMAP_A, io_bitmap_a),
651         FIELD64(IO_BITMAP_B, io_bitmap_b),
652         FIELD64(MSR_BITMAP, msr_bitmap),
653         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656         FIELD64(TSC_OFFSET, tsc_offset),
657         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
659         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
660         FIELD64(EPT_POINTER, ept_pointer),
661         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
665         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
666         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672         FIELD64(GUEST_PDPTR0, guest_pdptr0),
673         FIELD64(GUEST_PDPTR1, guest_pdptr1),
674         FIELD64(GUEST_PDPTR2, guest_pdptr2),
675         FIELD64(GUEST_PDPTR3, guest_pdptr3),
676         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
677         FIELD64(HOST_IA32_PAT, host_ia32_pat),
678         FIELD64(HOST_IA32_EFER, host_ia32_efer),
679         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682         FIELD(EXCEPTION_BITMAP, exception_bitmap),
683         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685         FIELD(CR3_TARGET_COUNT, cr3_target_count),
686         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694         FIELD(TPR_THRESHOLD, tpr_threshold),
695         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697         FIELD(VM_EXIT_REASON, vm_exit_reason),
698         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704         FIELD(GUEST_ES_LIMIT, guest_es_limit),
705         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
726         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
727         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735         FIELD(EXIT_QUALIFICATION, exit_qualification),
736         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737         FIELD(GUEST_CR0, guest_cr0),
738         FIELD(GUEST_CR3, guest_cr3),
739         FIELD(GUEST_CR4, guest_cr4),
740         FIELD(GUEST_ES_BASE, guest_es_base),
741         FIELD(GUEST_CS_BASE, guest_cs_base),
742         FIELD(GUEST_SS_BASE, guest_ss_base),
743         FIELD(GUEST_DS_BASE, guest_ds_base),
744         FIELD(GUEST_FS_BASE, guest_fs_base),
745         FIELD(GUEST_GS_BASE, guest_gs_base),
746         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747         FIELD(GUEST_TR_BASE, guest_tr_base),
748         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750         FIELD(GUEST_DR7, guest_dr7),
751         FIELD(GUEST_RSP, guest_rsp),
752         FIELD(GUEST_RIP, guest_rip),
753         FIELD(GUEST_RFLAGS, guest_rflags),
754         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757         FIELD(HOST_CR0, host_cr0),
758         FIELD(HOST_CR3, host_cr3),
759         FIELD(HOST_CR4, host_cr4),
760         FIELD(HOST_FS_BASE, host_fs_base),
761         FIELD(HOST_GS_BASE, host_gs_base),
762         FIELD(HOST_TR_BASE, host_tr_base),
763         FIELD(HOST_GDTR_BASE, host_gdtr_base),
764         FIELD(HOST_IDTR_BASE, host_idtr_base),
765         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767         FIELD(HOST_RSP, host_rsp),
768         FIELD(HOST_RIP, host_rip),
769 };
770 
771 static inline short vmcs_field_to_offset(unsigned long field)
772 {
773         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774 
775         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776             vmcs_field_to_offset_table[field] == 0)
777                 return -ENOENT;
778 
779         return vmcs_field_to_offset_table[field];
780 }
781 
782 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783 {
784         return to_vmx(vcpu)->nested.current_vmcs12;
785 }
786 
787 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788 {
789         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
790         if (is_error_page(page))
791                 return NULL;
792 
793         return page;
794 }
795 
796 static void nested_release_page(struct page *page)
797 {
798         kvm_release_page_dirty(page);
799 }
800 
801 static void nested_release_page_clean(struct page *page)
802 {
803         kvm_release_page_clean(page);
804 }
805 
806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
807 static u64 construct_eptp(unsigned long root_hpa);
808 static void kvm_cpu_vmxon(u64 addr);
809 static void kvm_cpu_vmxoff(void);
810 static bool vmx_mpx_supported(void);
811 static bool vmx_xsaves_supported(void);
812 static int vmx_vm_has_apicv(struct kvm *kvm);
813 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
814 static void vmx_set_segment(struct kvm_vcpu *vcpu,
815                             struct kvm_segment *var, int seg);
816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
817                             struct kvm_segment *var, int seg);
818 static bool guest_state_valid(struct kvm_vcpu *vcpu);
819 static u32 vmx_segment_access_rights(struct kvm_segment *var);
820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
821 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
822 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
823 static int alloc_identity_pagetable(struct kvm *kvm);
824 
825 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
827 /*
828  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830  */
831 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
832 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
833 
834 static unsigned long *vmx_io_bitmap_a;
835 static unsigned long *vmx_io_bitmap_b;
836 static unsigned long *vmx_msr_bitmap_legacy;
837 static unsigned long *vmx_msr_bitmap_longmode;
838 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
840 static unsigned long *vmx_msr_bitmap_nested;
841 static unsigned long *vmx_vmread_bitmap;
842 static unsigned long *vmx_vmwrite_bitmap;
843 
844 static bool cpu_has_load_ia32_efer;
845 static bool cpu_has_load_perf_global_ctrl;
846 
847 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848 static DEFINE_SPINLOCK(vmx_vpid_lock);
849 
850 static struct vmcs_config {
851         int size;
852         int order;
853         u32 revision_id;
854         u32 pin_based_exec_ctrl;
855         u32 cpu_based_exec_ctrl;
856         u32 cpu_based_2nd_exec_ctrl;
857         u32 vmexit_ctrl;
858         u32 vmentry_ctrl;
859 } vmcs_config;
860 
861 static struct vmx_capability {
862         u32 ept;
863         u32 vpid;
864 } vmx_capability;
865 
866 #define VMX_SEGMENT_FIELD(seg)                                  \
867         [VCPU_SREG_##seg] = {                                   \
868                 .selector = GUEST_##seg##_SELECTOR,             \
869                 .base = GUEST_##seg##_BASE,                     \
870                 .limit = GUEST_##seg##_LIMIT,                   \
871                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
872         }
873 
874 static const struct kvm_vmx_segment_field {
875         unsigned selector;
876         unsigned base;
877         unsigned limit;
878         unsigned ar_bytes;
879 } kvm_vmx_segment_fields[] = {
880         VMX_SEGMENT_FIELD(CS),
881         VMX_SEGMENT_FIELD(DS),
882         VMX_SEGMENT_FIELD(ES),
883         VMX_SEGMENT_FIELD(FS),
884         VMX_SEGMENT_FIELD(GS),
885         VMX_SEGMENT_FIELD(SS),
886         VMX_SEGMENT_FIELD(TR),
887         VMX_SEGMENT_FIELD(LDTR),
888 };
889 
890 static u64 host_efer;
891 
892 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
893 
894 /*
895  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
896  * away by decrementing the array size.
897  */
898 static const u32 vmx_msr_index[] = {
899 #ifdef CONFIG_X86_64
900         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
901 #endif
902         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
903 };
904 
905 static inline bool is_page_fault(u32 intr_info)
906 {
907         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908                              INTR_INFO_VALID_MASK)) ==
909                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
910 }
911 
912 static inline bool is_no_device(u32 intr_info)
913 {
914         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915                              INTR_INFO_VALID_MASK)) ==
916                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
917 }
918 
919 static inline bool is_invalid_opcode(u32 intr_info)
920 {
921         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922                              INTR_INFO_VALID_MASK)) ==
923                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
924 }
925 
926 static inline bool is_external_interrupt(u32 intr_info)
927 {
928         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
930 }
931 
932 static inline bool is_machine_check(u32 intr_info)
933 {
934         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935                              INTR_INFO_VALID_MASK)) ==
936                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
937 }
938 
939 static inline bool cpu_has_vmx_msr_bitmap(void)
940 {
941         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
942 }
943 
944 static inline bool cpu_has_vmx_tpr_shadow(void)
945 {
946         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
947 }
948 
949 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
950 {
951         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
952 }
953 
954 static inline bool cpu_has_secondary_exec_ctrls(void)
955 {
956         return vmcs_config.cpu_based_exec_ctrl &
957                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
958 }
959 
960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
961 {
962         return vmcs_config.cpu_based_2nd_exec_ctrl &
963                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
964 }
965 
966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967 {
968         return vmcs_config.cpu_based_2nd_exec_ctrl &
969                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
970 }
971 
972 static inline bool cpu_has_vmx_apic_register_virt(void)
973 {
974         return vmcs_config.cpu_based_2nd_exec_ctrl &
975                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
976 }
977 
978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979 {
980         return vmcs_config.cpu_based_2nd_exec_ctrl &
981                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
982 }
983 
984 static inline bool cpu_has_vmx_posted_intr(void)
985 {
986         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
987 }
988 
989 static inline bool cpu_has_vmx_apicv(void)
990 {
991         return cpu_has_vmx_apic_register_virt() &&
992                 cpu_has_vmx_virtual_intr_delivery() &&
993                 cpu_has_vmx_posted_intr();
994 }
995 
996 static inline bool cpu_has_vmx_flexpriority(void)
997 {
998         return cpu_has_vmx_tpr_shadow() &&
999                 cpu_has_vmx_virtualize_apic_accesses();
1000 }
1001 
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1003 {
1004         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1005 }
1006 
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1008 {
1009         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1010 }
1011 
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1013 {
1014         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1015 }
1016 
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1018 {
1019         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020 }
1021 
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1023 {
1024         return vmx_capability.ept & VMX_EPT_AD_BIT;
1025 }
1026 
1027 static inline bool cpu_has_vmx_invept_context(void)
1028 {
1029         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1030 }
1031 
1032 static inline bool cpu_has_vmx_invept_global(void)
1033 {
1034         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1035 }
1036 
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1038 {
1039         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040 }
1041 
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1043 {
1044         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045 }
1046 
1047 static inline bool cpu_has_vmx_ept(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_ENABLE_EPT;
1051 }
1052 
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057 }
1058 
1059 static inline bool cpu_has_vmx_ple(void)
1060 {
1061         return vmcs_config.cpu_based_2nd_exec_ctrl &
1062                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063 }
1064 
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1066 {
1067         return flexpriority_enabled && irqchip_in_kernel(kvm);
1068 }
1069 
1070 static inline bool cpu_has_vmx_vpid(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_ENABLE_VPID;
1074 }
1075 
1076 static inline bool cpu_has_vmx_rdtscp(void)
1077 {
1078         return vmcs_config.cpu_based_2nd_exec_ctrl &
1079                 SECONDARY_EXEC_RDTSCP;
1080 }
1081 
1082 static inline bool cpu_has_vmx_invpcid(void)
1083 {
1084         return vmcs_config.cpu_based_2nd_exec_ctrl &
1085                 SECONDARY_EXEC_ENABLE_INVPCID;
1086 }
1087 
1088 static inline bool cpu_has_virtual_nmis(void)
1089 {
1090         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091 }
1092 
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1094 {
1095         return vmcs_config.cpu_based_2nd_exec_ctrl &
1096                 SECONDARY_EXEC_WBINVD_EXITING;
1097 }
1098 
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1100 {
1101         u64 vmx_msr;
1102         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103         /* check if the cpu supports writing r/o exit information fields */
1104         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105                 return false;
1106 
1107         return vmcs_config.cpu_based_2nd_exec_ctrl &
1108                 SECONDARY_EXEC_SHADOW_VMCS;
1109 }
1110 
1111 static inline bool cpu_has_vmx_pml(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114 }
1115 
1116 static inline bool report_flexpriority(void)
1117 {
1118         return flexpriority_enabled;
1119 }
1120 
1121 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122 {
1123         return vmcs12->cpu_based_vm_exec_control & bit;
1124 }
1125 
1126 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127 {
1128         return (vmcs12->cpu_based_vm_exec_control &
1129                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130                 (vmcs12->secondary_vm_exec_control & bit);
1131 }
1132 
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1134 {
1135         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136 }
1137 
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139 {
1140         return vmcs12->pin_based_vm_exec_control &
1141                 PIN_BASED_VMX_PREEMPTION_TIMER;
1142 }
1143 
1144 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145 {
1146         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147 }
1148 
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150 {
1151         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152                 vmx_xsaves_supported();
1153 }
1154 
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156 {
1157         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158 }
1159 
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161 {
1162         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163 }
1164 
1165 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166 {
1167         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168 }
1169 
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171 {
1172         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173 }
1174 
1175 static inline bool is_exception(u32 intr_info)
1176 {
1177         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179 }
1180 
1181 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182                               u32 exit_intr_info,
1183                               unsigned long exit_qualification);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185                         struct vmcs12 *vmcs12,
1186                         u32 reason, unsigned long qualification);
1187 
1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1189 {
1190         int i;
1191 
1192         for (i = 0; i < vmx->nmsrs; ++i)
1193                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1194                         return i;
1195         return -1;
1196 }
1197 
1198 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199 {
1200     struct {
1201         u64 vpid : 16;
1202         u64 rsvd : 48;
1203         u64 gva;
1204     } operand = { vpid, 0, gva };
1205 
1206     asm volatile (__ex(ASM_VMX_INVVPID)
1207                   /* CF==1 or ZF==1 --> rc = -1 */
1208                   "; ja 1f ; ud2 ; 1:"
1209                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1210 }
1211 
1212 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213 {
1214         struct {
1215                 u64 eptp, gpa;
1216         } operand = {eptp, gpa};
1217 
1218         asm volatile (__ex(ASM_VMX_INVEPT)
1219                         /* CF==1 or ZF==1 --> rc = -1 */
1220                         "; ja 1f ; ud2 ; 1:\n"
1221                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1222 }
1223 
1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1225 {
1226         int i;
1227 
1228         i = __find_msr_index(vmx, msr);
1229         if (i >= 0)
1230                 return &vmx->guest_msrs[i];
1231         return NULL;
1232 }
1233 
1234 static void vmcs_clear(struct vmcs *vmcs)
1235 {
1236         u64 phys_addr = __pa(vmcs);
1237         u8 error;
1238 
1239         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1240                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1241                       : "cc", "memory");
1242         if (error)
1243                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244                        vmcs, phys_addr);
1245 }
1246 
1247 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248 {
1249         vmcs_clear(loaded_vmcs->vmcs);
1250         loaded_vmcs->cpu = -1;
1251         loaded_vmcs->launched = 0;
1252 }
1253 
1254 static void vmcs_load(struct vmcs *vmcs)
1255 {
1256         u64 phys_addr = __pa(vmcs);
1257         u8 error;
1258 
1259         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1260                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1261                         : "cc", "memory");
1262         if (error)
1263                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1264                        vmcs, phys_addr);
1265 }
1266 
1267 #ifdef CONFIG_KEXEC
1268 /*
1269  * This bitmap is used to indicate whether the vmclear
1270  * operation is enabled on all cpus. All disabled by
1271  * default.
1272  */
1273 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274 
1275 static inline void crash_enable_local_vmclear(int cpu)
1276 {
1277         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278 }
1279 
1280 static inline void crash_disable_local_vmclear(int cpu)
1281 {
1282         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283 }
1284 
1285 static inline int crash_local_vmclear_enabled(int cpu)
1286 {
1287         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288 }
1289 
1290 static void crash_vmclear_local_loaded_vmcss(void)
1291 {
1292         int cpu = raw_smp_processor_id();
1293         struct loaded_vmcs *v;
1294 
1295         if (!crash_local_vmclear_enabled(cpu))
1296                 return;
1297 
1298         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299                             loaded_vmcss_on_cpu_link)
1300                 vmcs_clear(v->vmcs);
1301 }
1302 #else
1303 static inline void crash_enable_local_vmclear(int cpu) { }
1304 static inline void crash_disable_local_vmclear(int cpu) { }
1305 #endif /* CONFIG_KEXEC */
1306 
1307 static void __loaded_vmcs_clear(void *arg)
1308 {
1309         struct loaded_vmcs *loaded_vmcs = arg;
1310         int cpu = raw_smp_processor_id();
1311 
1312         if (loaded_vmcs->cpu != cpu)
1313                 return; /* vcpu migration can race with cpu offline */
1314         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1315                 per_cpu(current_vmcs, cpu) = NULL;
1316         crash_disable_local_vmclear(cpu);
1317         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1318 
1319         /*
1320          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321          * is before setting loaded_vmcs->vcpu to -1 which is done in
1322          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323          * then adds the vmcs into percpu list before it is deleted.
1324          */
1325         smp_wmb();
1326 
1327         loaded_vmcs_init(loaded_vmcs);
1328         crash_enable_local_vmclear(cpu);
1329 }
1330 
1331 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1332 {
1333         int cpu = loaded_vmcs->cpu;
1334 
1335         if (cpu != -1)
1336                 smp_call_function_single(cpu,
1337                          __loaded_vmcs_clear, loaded_vmcs, 1);
1338 }
1339 
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1341 {
1342         if (vmx->vpid == 0)
1343                 return;
1344 
1345         if (cpu_has_vmx_invvpid_single())
1346                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1347 }
1348 
1349 static inline void vpid_sync_vcpu_global(void)
1350 {
1351         if (cpu_has_vmx_invvpid_global())
1352                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353 }
1354 
1355 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356 {
1357         if (cpu_has_vmx_invvpid_single())
1358                 vpid_sync_vcpu_single(vmx);
1359         else
1360                 vpid_sync_vcpu_global();
1361 }
1362 
1363 static inline void ept_sync_global(void)
1364 {
1365         if (cpu_has_vmx_invept_global())
1366                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367 }
1368 
1369 static inline void ept_sync_context(u64 eptp)
1370 {
1371         if (enable_ept) {
1372                 if (cpu_has_vmx_invept_context())
1373                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374                 else
1375                         ept_sync_global();
1376         }
1377 }
1378 
1379 static __always_inline unsigned long vmcs_readl(unsigned long field)
1380 {
1381         unsigned long value;
1382 
1383         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384                       : "=a"(value) : "d"(field) : "cc");
1385         return value;
1386 }
1387 
1388 static __always_inline u16 vmcs_read16(unsigned long field)
1389 {
1390         return vmcs_readl(field);
1391 }
1392 
1393 static __always_inline u32 vmcs_read32(unsigned long field)
1394 {
1395         return vmcs_readl(field);
1396 }
1397 
1398 static __always_inline u64 vmcs_read64(unsigned long field)
1399 {
1400 #ifdef CONFIG_X86_64
1401         return vmcs_readl(field);
1402 #else
1403         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404 #endif
1405 }
1406 
1407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408 {
1409         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411         dump_stack();
1412 }
1413 
1414 static void vmcs_writel(unsigned long field, unsigned long value)
1415 {
1416         u8 error;
1417 
1418         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1419                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1420         if (unlikely(error))
1421                 vmwrite_error(field, value);
1422 }
1423 
1424 static void vmcs_write16(unsigned long field, u16 value)
1425 {
1426         vmcs_writel(field, value);
1427 }
1428 
1429 static void vmcs_write32(unsigned long field, u32 value)
1430 {
1431         vmcs_writel(field, value);
1432 }
1433 
1434 static void vmcs_write64(unsigned long field, u64 value)
1435 {
1436         vmcs_writel(field, value);
1437 #ifndef CONFIG_X86_64
1438         asm volatile ("");
1439         vmcs_writel(field+1, value >> 32);
1440 #endif
1441 }
1442 
1443 static void vmcs_clear_bits(unsigned long field, u32 mask)
1444 {
1445         vmcs_writel(field, vmcs_readl(field) & ~mask);
1446 }
1447 
1448 static void vmcs_set_bits(unsigned long field, u32 mask)
1449 {
1450         vmcs_writel(field, vmcs_readl(field) | mask);
1451 }
1452 
1453 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454 {
1455         vmcs_write32(VM_ENTRY_CONTROLS, val);
1456         vmx->vm_entry_controls_shadow = val;
1457 }
1458 
1459 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460 {
1461         if (vmx->vm_entry_controls_shadow != val)
1462                 vm_entry_controls_init(vmx, val);
1463 }
1464 
1465 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466 {
1467         return vmx->vm_entry_controls_shadow;
1468 }
1469 
1470 
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472 {
1473         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474 }
1475 
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477 {
1478         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479 }
1480 
1481 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482 {
1483         vmcs_write32(VM_EXIT_CONTROLS, val);
1484         vmx->vm_exit_controls_shadow = val;
1485 }
1486 
1487 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488 {
1489         if (vmx->vm_exit_controls_shadow != val)
1490                 vm_exit_controls_init(vmx, val);
1491 }
1492 
1493 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494 {
1495         return vmx->vm_exit_controls_shadow;
1496 }
1497 
1498 
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500 {
1501         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502 }
1503 
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505 {
1506         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507 }
1508 
1509 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510 {
1511         vmx->segment_cache.bitmask = 0;
1512 }
1513 
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515                                        unsigned field)
1516 {
1517         bool ret;
1518         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519 
1520         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522                 vmx->segment_cache.bitmask = 0;
1523         }
1524         ret = vmx->segment_cache.bitmask & mask;
1525         vmx->segment_cache.bitmask |= mask;
1526         return ret;
1527 }
1528 
1529 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530 {
1531         u16 *p = &vmx->segment_cache.seg[seg].selector;
1532 
1533         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535         return *p;
1536 }
1537 
1538 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539 {
1540         ulong *p = &vmx->segment_cache.seg[seg].base;
1541 
1542         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544         return *p;
1545 }
1546 
1547 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548 {
1549         u32 *p = &vmx->segment_cache.seg[seg].limit;
1550 
1551         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553         return *p;
1554 }
1555 
1556 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557 {
1558         u32 *p = &vmx->segment_cache.seg[seg].ar;
1559 
1560         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562         return *p;
1563 }
1564 
1565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566 {
1567         u32 eb;
1568 
1569         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571         if ((vcpu->guest_debug &
1572              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574                 eb |= 1u << BP_VECTOR;
1575         if (to_vmx(vcpu)->rmode.vm86_active)
1576                 eb = ~0;
1577         if (enable_ept)
1578                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1579         if (vcpu->fpu_active)
1580                 eb &= ~(1u << NM_VECTOR);
1581 
1582         /* When we are running a nested L2 guest and L1 specified for it a
1583          * certain exception bitmap, we must trap the same exceptions and pass
1584          * them to L1. When running L2, we will only handle the exceptions
1585          * specified above if L1 did not want them.
1586          */
1587         if (is_guest_mode(vcpu))
1588                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589 
1590         vmcs_write32(EXCEPTION_BITMAP, eb);
1591 }
1592 
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594                 unsigned long entry, unsigned long exit)
1595 {
1596         vm_entry_controls_clearbit(vmx, entry);
1597         vm_exit_controls_clearbit(vmx, exit);
1598 }
1599 
1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601 {
1602         unsigned i;
1603         struct msr_autoload *m = &vmx->msr_autoload;
1604 
1605         switch (msr) {
1606         case MSR_EFER:
1607                 if (cpu_has_load_ia32_efer) {
1608                         clear_atomic_switch_msr_special(vmx,
1609                                         VM_ENTRY_LOAD_IA32_EFER,
1610                                         VM_EXIT_LOAD_IA32_EFER);
1611                         return;
1612                 }
1613                 break;
1614         case MSR_CORE_PERF_GLOBAL_CTRL:
1615                 if (cpu_has_load_perf_global_ctrl) {
1616                         clear_atomic_switch_msr_special(vmx,
1617                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619                         return;
1620                 }
1621                 break;
1622         }
1623 
1624         for (i = 0; i < m->nr; ++i)
1625                 if (m->guest[i].index == msr)
1626                         break;
1627 
1628         if (i == m->nr)
1629                 return;
1630         --m->nr;
1631         m->guest[i] = m->guest[m->nr];
1632         m->host[i] = m->host[m->nr];
1633         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635 }
1636 
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638                 unsigned long entry, unsigned long exit,
1639                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640                 u64 guest_val, u64 host_val)
1641 {
1642         vmcs_write64(guest_val_vmcs, guest_val);
1643         vmcs_write64(host_val_vmcs, host_val);
1644         vm_entry_controls_setbit(vmx, entry);
1645         vm_exit_controls_setbit(vmx, exit);
1646 }
1647 
1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649                                   u64 guest_val, u64 host_val)
1650 {
1651         unsigned i;
1652         struct msr_autoload *m = &vmx->msr_autoload;
1653 
1654         switch (msr) {
1655         case MSR_EFER:
1656                 if (cpu_has_load_ia32_efer) {
1657                         add_atomic_switch_msr_special(vmx,
1658                                         VM_ENTRY_LOAD_IA32_EFER,
1659                                         VM_EXIT_LOAD_IA32_EFER,
1660                                         GUEST_IA32_EFER,
1661                                         HOST_IA32_EFER,
1662                                         guest_val, host_val);
1663                         return;
1664                 }
1665                 break;
1666         case MSR_CORE_PERF_GLOBAL_CTRL:
1667                 if (cpu_has_load_perf_global_ctrl) {
1668                         add_atomic_switch_msr_special(vmx,
1669                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1672                                         HOST_IA32_PERF_GLOBAL_CTRL,
1673                                         guest_val, host_val);
1674                         return;
1675                 }
1676                 break;
1677         }
1678 
1679         for (i = 0; i < m->nr; ++i)
1680                 if (m->guest[i].index == msr)
1681                         break;
1682 
1683         if (i == NR_AUTOLOAD_MSRS) {
1684                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1685                                 "Can't add msr %x\n", msr);
1686                 return;
1687         } else if (i == m->nr) {
1688                 ++m->nr;
1689                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691         }
1692 
1693         m->guest[i].index = msr;
1694         m->guest[i].value = guest_val;
1695         m->host[i].index = msr;
1696         m->host[i].value = host_val;
1697 }
1698 
1699 static void reload_tss(void)
1700 {
1701         /*
1702          * VT restores TR but not its size.  Useless.
1703          */
1704         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1705         struct desc_struct *descs;
1706 
1707         descs = (void *)gdt->address;
1708         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709         load_TR_desc();
1710 }
1711 
1712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1713 {
1714         u64 guest_efer;
1715         u64 ignore_bits;
1716 
1717         guest_efer = vmx->vcpu.arch.efer;
1718 
1719         /*
1720          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1721          * outside long mode
1722          */
1723         ignore_bits = EFER_NX | EFER_SCE;
1724 #ifdef CONFIG_X86_64
1725         ignore_bits |= EFER_LMA | EFER_LME;
1726         /* SCE is meaningful only in long mode on Intel */
1727         if (guest_efer & EFER_LMA)
1728                 ignore_bits &= ~(u64)EFER_SCE;
1729 #endif
1730         guest_efer &= ~ignore_bits;
1731         guest_efer |= host_efer & ignore_bits;
1732         vmx->guest_msrs[efer_offset].data = guest_efer;
1733         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1734 
1735         clear_atomic_switch_msr(vmx, MSR_EFER);
1736 
1737         /*
1738          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739          * On CPUs that support "load IA32_EFER", always switch EFER
1740          * atomically, since it's faster than switching it manually.
1741          */
1742         if (cpu_has_load_ia32_efer ||
1743             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1744                 guest_efer = vmx->vcpu.arch.efer;
1745                 if (!(guest_efer & EFER_LMA))
1746                         guest_efer &= ~EFER_LME;
1747                 if (guest_efer != host_efer)
1748                         add_atomic_switch_msr(vmx, MSR_EFER,
1749                                               guest_efer, host_efer);
1750                 return false;
1751         }
1752 
1753         return true;
1754 }
1755 
1756 static unsigned long segment_base(u16 selector)
1757 {
1758         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1759         struct desc_struct *d;
1760         unsigned long table_base;
1761         unsigned long v;
1762 
1763         if (!(selector & ~3))
1764                 return 0;
1765 
1766         table_base = gdt->address;
1767 
1768         if (selector & 4) {           /* from ldt */
1769                 u16 ldt_selector = kvm_read_ldt();
1770 
1771                 if (!(ldt_selector & ~3))
1772                         return 0;
1773 
1774                 table_base = segment_base(ldt_selector);
1775         }
1776         d = (struct desc_struct *)(table_base + (selector & ~7));
1777         v = get_desc_base(d);
1778 #ifdef CONFIG_X86_64
1779        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781 #endif
1782         return v;
1783 }
1784 
1785 static inline unsigned long kvm_read_tr_base(void)
1786 {
1787         u16 tr;
1788         asm("str %0" : "=g"(tr));
1789         return segment_base(tr);
1790 }
1791 
1792 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         int i;
1796 
1797         if (vmx->host_state.loaded)
1798                 return;
1799 
1800         vmx->host_state.loaded = 1;
1801         /*
1802          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1803          * allow segment selectors with cpl > 0 or ti == 1.
1804          */
1805         vmx->host_state.ldt_sel = kvm_read_ldt();
1806         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1807         savesegment(fs, vmx->host_state.fs_sel);
1808         if (!(vmx->host_state.fs_sel & 7)) {
1809                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1810                 vmx->host_state.fs_reload_needed = 0;
1811         } else {
1812                 vmcs_write16(HOST_FS_SELECTOR, 0);
1813                 vmx->host_state.fs_reload_needed = 1;
1814         }
1815         savesegment(gs, vmx->host_state.gs_sel);
1816         if (!(vmx->host_state.gs_sel & 7))
1817                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1818         else {
1819                 vmcs_write16(HOST_GS_SELECTOR, 0);
1820                 vmx->host_state.gs_ldt_reload_needed = 1;
1821         }
1822 
1823 #ifdef CONFIG_X86_64
1824         savesegment(ds, vmx->host_state.ds_sel);
1825         savesegment(es, vmx->host_state.es_sel);
1826 #endif
1827 
1828 #ifdef CONFIG_X86_64
1829         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831 #else
1832         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1834 #endif
1835 
1836 #ifdef CONFIG_X86_64
1837         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838         if (is_long_mode(&vmx->vcpu))
1839                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1840 #endif
1841         if (boot_cpu_has(X86_FEATURE_MPX))
1842                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1843         for (i = 0; i < vmx->save_nmsrs; ++i)
1844                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1845                                    vmx->guest_msrs[i].data,
1846                                    vmx->guest_msrs[i].mask);
1847 }
1848 
1849 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1850 {
1851         if (!vmx->host_state.loaded)
1852                 return;
1853 
1854         ++vmx->vcpu.stat.host_state_reload;
1855         vmx->host_state.loaded = 0;
1856 #ifdef CONFIG_X86_64
1857         if (is_long_mode(&vmx->vcpu))
1858                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859 #endif
1860         if (vmx->host_state.gs_ldt_reload_needed) {
1861                 kvm_load_ldt(vmx->host_state.ldt_sel);
1862 #ifdef CONFIG_X86_64
1863                 load_gs_index(vmx->host_state.gs_sel);
1864 #else
1865                 loadsegment(gs, vmx->host_state.gs_sel);
1866 #endif
1867         }
1868         if (vmx->host_state.fs_reload_needed)
1869                 loadsegment(fs, vmx->host_state.fs_sel);
1870 #ifdef CONFIG_X86_64
1871         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872                 loadsegment(ds, vmx->host_state.ds_sel);
1873                 loadsegment(es, vmx->host_state.es_sel);
1874         }
1875 #endif
1876         reload_tss();
1877 #ifdef CONFIG_X86_64
1878         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1879 #endif
1880         if (vmx->host_state.msr_host_bndcfgs)
1881                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1882         /*
1883          * If the FPU is not active (through the host task or
1884          * the guest vcpu), then restore the cr0.TS bit.
1885          */
1886         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887                 stts();
1888         load_gdt(this_cpu_ptr(&host_gdt));
1889 }
1890 
1891 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892 {
1893         preempt_disable();
1894         __vmx_load_host_state(vmx);
1895         preempt_enable();
1896 }
1897 
1898 /*
1899  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900  * vcpu mutex is already taken.
1901  */
1902 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1903 {
1904         struct vcpu_vmx *vmx = to_vmx(vcpu);
1905         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1906 
1907         if (!vmm_exclusive)
1908                 kvm_cpu_vmxon(phys_addr);
1909         else if (vmx->loaded_vmcs->cpu != cpu)
1910                 loaded_vmcs_clear(vmx->loaded_vmcs);
1911 
1912         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914                 vmcs_load(vmx->loaded_vmcs->vmcs);
1915         }
1916 
1917         if (vmx->loaded_vmcs->cpu != cpu) {
1918                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1919                 unsigned long sysenter_esp;
1920 
1921                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1922                 local_irq_disable();
1923                 crash_disable_local_vmclear(cpu);
1924 
1925                 /*
1926                  * Read loaded_vmcs->cpu should be before fetching
1927                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928                  * See the comments in __loaded_vmcs_clear().
1929                  */
1930                 smp_rmb();
1931 
1932                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1934                 crash_enable_local_vmclear(cpu);
1935                 local_irq_enable();
1936 
1937                 /*
1938                  * Linux uses per-cpu TSS and GDT, so set these when switching
1939                  * processors.
1940                  */
1941                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1942                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1943 
1944                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1946                 vmx->loaded_vmcs->cpu = cpu;
1947         }
1948 }
1949 
1950 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951 {
1952         __vmx_load_host_state(to_vmx(vcpu));
1953         if (!vmm_exclusive) {
1954                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955                 vcpu->cpu = -1;
1956                 kvm_cpu_vmxoff();
1957         }
1958 }
1959 
1960 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961 {
1962         ulong cr0;
1963 
1964         if (vcpu->fpu_active)
1965                 return;
1966         vcpu->fpu_active = 1;
1967         cr0 = vmcs_readl(GUEST_CR0);
1968         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970         vmcs_writel(GUEST_CR0, cr0);
1971         update_exception_bitmap(vcpu);
1972         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1973         if (is_guest_mode(vcpu))
1974                 vcpu->arch.cr0_guest_owned_bits &=
1975                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1976         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1977 }
1978 
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980 
1981 /*
1982  * Return the cr0 value that a nested guest would read. This is a combination
1983  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984  * its hypervisor (cr0_read_shadow).
1985  */
1986 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987 {
1988         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990 }
1991 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992 {
1993         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995 }
1996 
1997 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998 {
1999         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000          * set this *before* calling this function.
2001          */
2002         vmx_decache_cr0_guest_bits(vcpu);
2003         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2004         update_exception_bitmap(vcpu);
2005         vcpu->arch.cr0_guest_owned_bits = 0;
2006         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2007         if (is_guest_mode(vcpu)) {
2008                 /*
2009                  * L1's specified read shadow might not contain the TS bit,
2010                  * so now that we turned on shadowing of this bit, we need to
2011                  * set this bit of the shadow. Like in nested_vmx_run we need
2012                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013                  * up-to-date here because we just decached cr0.TS (and we'll
2014                  * only update vmcs12->guest_cr0 on nested exit).
2015                  */
2016                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018                         (vcpu->arch.cr0 & X86_CR0_TS);
2019                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020         } else
2021                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2022 }
2023 
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025 {
2026         unsigned long rflags, save_rflags;
2027 
2028         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030                 rflags = vmcs_readl(GUEST_RFLAGS);
2031                 if (to_vmx(vcpu)->rmode.vm86_active) {
2032                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035                 }
2036                 to_vmx(vcpu)->rflags = rflags;
2037         }
2038         return to_vmx(vcpu)->rflags;
2039 }
2040 
2041 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042 {
2043         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044         to_vmx(vcpu)->rflags = rflags;
2045         if (to_vmx(vcpu)->rmode.vm86_active) {
2046                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2047                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2048         }
2049         vmcs_writel(GUEST_RFLAGS, rflags);
2050 }
2051 
2052 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2053 {
2054         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055         int ret = 0;
2056 
2057         if (interruptibility & GUEST_INTR_STATE_STI)
2058                 ret |= KVM_X86_SHADOW_INT_STI;
2059         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2060                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2061 
2062         return ret;
2063 }
2064 
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066 {
2067         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068         u32 interruptibility = interruptibility_old;
2069 
2070         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071 
2072         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2073                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2074         else if (mask & KVM_X86_SHADOW_INT_STI)
2075                 interruptibility |= GUEST_INTR_STATE_STI;
2076 
2077         if ((interruptibility != interruptibility_old))
2078                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079 }
2080 
2081 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082 {
2083         unsigned long rip;
2084 
2085         rip = kvm_rip_read(vcpu);
2086         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2087         kvm_rip_write(vcpu, rip);
2088 
2089         /* skipping an emulated instruction also counts */
2090         vmx_set_interrupt_shadow(vcpu, 0);
2091 }
2092 
2093 /*
2094  * KVM wants to inject page-faults which it got to the guest. This function
2095  * checks whether in a nested guest, we need to inject them to L1 or L2.
2096  */
2097 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2098 {
2099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100 
2101         if (!(vmcs12->exception_bitmap & (1u << nr)))
2102                 return 0;
2103 
2104         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105                           vmcs_read32(VM_EXIT_INTR_INFO),
2106                           vmcs_readl(EXIT_QUALIFICATION));
2107         return 1;
2108 }
2109 
2110 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2111                                 bool has_error_code, u32 error_code,
2112                                 bool reinject)
2113 {
2114         struct vcpu_vmx *vmx = to_vmx(vcpu);
2115         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2116 
2117         if (!reinject && is_guest_mode(vcpu) &&
2118             nested_vmx_check_exception(vcpu, nr))
2119                 return;
2120 
2121         if (has_error_code) {
2122                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2123                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124         }
2125 
2126         if (vmx->rmode.vm86_active) {
2127                 int inc_eip = 0;
2128                 if (kvm_exception_is_soft(nr))
2129                         inc_eip = vcpu->arch.event_exit_inst_len;
2130                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2131                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2132                 return;
2133         }
2134 
2135         if (kvm_exception_is_soft(nr)) {
2136                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137                              vmx->vcpu.arch.event_exit_inst_len);
2138                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139         } else
2140                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141 
2142         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2143 }
2144 
2145 static bool vmx_rdtscp_supported(void)
2146 {
2147         return cpu_has_vmx_rdtscp();
2148 }
2149 
2150 static bool vmx_invpcid_supported(void)
2151 {
2152         return cpu_has_vmx_invpcid() && enable_ept;
2153 }
2154 
2155 /*
2156  * Swap MSR entry in host/guest MSR entry array.
2157  */
2158 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2159 {
2160         struct shared_msr_entry tmp;
2161 
2162         tmp = vmx->guest_msrs[to];
2163         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164         vmx->guest_msrs[from] = tmp;
2165 }
2166 
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168 {
2169         unsigned long *msr_bitmap;
2170 
2171         if (is_guest_mode(vcpu))
2172                 msr_bitmap = vmx_msr_bitmap_nested;
2173         else if (irqchip_in_kernel(vcpu->kvm) &&
2174                 apic_x2apic_mode(vcpu->arch.apic)) {
2175                 if (is_long_mode(vcpu))
2176                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177                 else
2178                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179         } else {
2180                 if (is_long_mode(vcpu))
2181                         msr_bitmap = vmx_msr_bitmap_longmode;
2182                 else
2183                         msr_bitmap = vmx_msr_bitmap_legacy;
2184         }
2185 
2186         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187 }
2188 
2189 /*
2190  * Set up the vmcs to automatically save and restore system
2191  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2192  * mode, as fiddling with msrs is very expensive.
2193  */
2194 static void setup_msrs(struct vcpu_vmx *vmx)
2195 {
2196         int save_nmsrs, index;
2197 
2198         save_nmsrs = 0;
2199 #ifdef CONFIG_X86_64
2200         if (is_long_mode(&vmx->vcpu)) {
2201                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2202                 if (index >= 0)
2203                         move_msr_up(vmx, index, save_nmsrs++);
2204                 index = __find_msr_index(vmx, MSR_LSTAR);
2205                 if (index >= 0)
2206                         move_msr_up(vmx, index, save_nmsrs++);
2207                 index = __find_msr_index(vmx, MSR_CSTAR);
2208                 if (index >= 0)
2209                         move_msr_up(vmx, index, save_nmsrs++);
2210                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211                 if (index >= 0 && vmx->rdtscp_enabled)
2212                         move_msr_up(vmx, index, save_nmsrs++);
2213                 /*
2214                  * MSR_STAR is only needed on long mode guests, and only
2215                  * if efer.sce is enabled.
2216                  */
2217                 index = __find_msr_index(vmx, MSR_STAR);
2218                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2219                         move_msr_up(vmx, index, save_nmsrs++);
2220         }
2221 #endif
2222         index = __find_msr_index(vmx, MSR_EFER);
2223         if (index >= 0 && update_transition_efer(vmx, index))
2224                 move_msr_up(vmx, index, save_nmsrs++);
2225 
2226         vmx->save_nmsrs = save_nmsrs;
2227 
2228         if (cpu_has_vmx_msr_bitmap())
2229                 vmx_set_msr_bitmap(&vmx->vcpu);
2230 }
2231 
2232 /*
2233  * reads and returns guest's timestamp counter "register"
2234  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2235  */
2236 static u64 guest_read_tsc(void)
2237 {
2238         u64 host_tsc, tsc_offset;
2239 
2240         rdtscll(host_tsc);
2241         tsc_offset = vmcs_read64(TSC_OFFSET);
2242         return host_tsc + tsc_offset;
2243 }
2244 
2245 /*
2246  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247  * counter, even if a nested guest (L2) is currently running.
2248  */
2249 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2250 {
2251         u64 tsc_offset;
2252 
2253         tsc_offset = is_guest_mode(vcpu) ?
2254                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255                 vmcs_read64(TSC_OFFSET);
2256         return host_tsc + tsc_offset;
2257 }
2258 
2259 /*
2260  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2261  * software catchup for faster rates on slower CPUs.
2262  */
2263 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2264 {
2265         if (!scale)
2266                 return;
2267 
2268         if (user_tsc_khz > tsc_khz) {
2269                 vcpu->arch.tsc_catchup = 1;
2270                 vcpu->arch.tsc_always_catchup = 1;
2271         } else
2272                 WARN(1, "user requested TSC rate below hardware speed\n");
2273 }
2274 
2275 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276 {
2277         return vmcs_read64(TSC_OFFSET);
2278 }
2279 
2280 /*
2281  * writes 'offset' into guest's timestamp counter offset register
2282  */
2283 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2284 {
2285         if (is_guest_mode(vcpu)) {
2286                 /*
2287                  * We're here if L1 chose not to trap WRMSR to TSC. According
2288                  * to the spec, this should set L1's TSC; The offset that L1
2289                  * set for L2 remains unchanged, and still needs to be added
2290                  * to the newly set TSC to get L2's TSC.
2291                  */
2292                 struct vmcs12 *vmcs12;
2293                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294                 /* recalculate vmcs02.TSC_OFFSET: */
2295                 vmcs12 = get_vmcs12(vcpu);
2296                 vmcs_write64(TSC_OFFSET, offset +
2297                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298                          vmcs12->tsc_offset : 0));
2299         } else {
2300                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301                                            vmcs_read64(TSC_OFFSET), offset);
2302                 vmcs_write64(TSC_OFFSET, offset);
2303         }
2304 }
2305 
2306 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2307 {
2308         u64 offset = vmcs_read64(TSC_OFFSET);
2309 
2310         vmcs_write64(TSC_OFFSET, offset + adjustment);
2311         if (is_guest_mode(vcpu)) {
2312                 /* Even when running L2, the adjustment needs to apply to L1 */
2313                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2314         } else
2315                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316                                            offset + adjustment);
2317 }
2318 
2319 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320 {
2321         return target_tsc - native_read_tsc();
2322 }
2323 
2324 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325 {
2326         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328 }
2329 
2330 /*
2331  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333  * all guests if the "nested" module option is off, and can also be disabled
2334  * for a single guest by disabling its VMX cpuid bit.
2335  */
2336 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337 {
2338         return nested && guest_cpuid_has_vmx(vcpu);
2339 }
2340 
2341 /*
2342  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343  * returned for the various VMX controls MSRs when nested VMX is enabled.
2344  * The same values should also be used to verify that vmcs12 control fields are
2345  * valid during nested entry from L1 to L2.
2346  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348  * bit in the high half is on if the corresponding bit in the control field
2349  * may be on. See also vmx_control_verify().
2350  */
2351 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2352 {
2353         /*
2354          * Note that as a general rule, the high half of the MSRs (bits in
2355          * the control fields which may be 1) should be initialized by the
2356          * intersection of the underlying hardware's MSR (i.e., features which
2357          * can be supported) and the list of features we want to expose -
2358          * because they are known to be properly supported in our code.
2359          * Also, usually, the low half of the MSRs (bits which must be 1) can
2360          * be set to 0, meaning that L1 may turn off any of these bits. The
2361          * reason is that if one of these bits is necessary, it will appear
2362          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363          * fields of vmcs01 and vmcs02, will turn these bits off - and
2364          * nested_vmx_exit_handled() will not pass related exits to L1.
2365          * These rules have exceptions below.
2366          */
2367 
2368         /* pin-based controls */
2369         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2370                 vmx->nested.nested_vmx_pinbased_ctls_low,
2371                 vmx->nested.nested_vmx_pinbased_ctls_high);
2372         vmx->nested.nested_vmx_pinbased_ctls_low |=
2373                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374         vmx->nested.nested_vmx_pinbased_ctls_high &=
2375                 PIN_BASED_EXT_INTR_MASK |
2376                 PIN_BASED_NMI_EXITING |
2377                 PIN_BASED_VIRTUAL_NMIS;
2378         vmx->nested.nested_vmx_pinbased_ctls_high |=
2379                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2380                 PIN_BASED_VMX_PREEMPTION_TIMER;
2381         if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2382                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383                         PIN_BASED_POSTED_INTR;
2384 
2385         /* exit controls */
2386         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2387                 vmx->nested.nested_vmx_exit_ctls_low,
2388                 vmx->nested.nested_vmx_exit_ctls_high);
2389         vmx->nested.nested_vmx_exit_ctls_low =
2390                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2391 
2392         vmx->nested.nested_vmx_exit_ctls_high &=
2393 #ifdef CONFIG_X86_64
2394                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2395 #endif
2396                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2397         vmx->nested.nested_vmx_exit_ctls_high |=
2398                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2399                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2400                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401 
2402         if (vmx_mpx_supported())
2403                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2404 
2405         /* We support free control of debug control saving. */
2406         vmx->nested.nested_vmx_true_exit_ctls_low =
2407                 vmx->nested.nested_vmx_exit_ctls_low &
2408                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409 
2410         /* entry controls */
2411         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2412                 vmx->nested.nested_vmx_entry_ctls_low,
2413                 vmx->nested.nested_vmx_entry_ctls_high);
2414         vmx->nested.nested_vmx_entry_ctls_low =
2415                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416         vmx->nested.nested_vmx_entry_ctls_high &=
2417 #ifdef CONFIG_X86_64
2418                 VM_ENTRY_IA32E_MODE |
2419 #endif
2420                 VM_ENTRY_LOAD_IA32_PAT;
2421         vmx->nested.nested_vmx_entry_ctls_high |=
2422                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2423         if (vmx_mpx_supported())
2424                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2425 
2426         /* We support free control of debug control loading. */
2427         vmx->nested.nested_vmx_true_entry_ctls_low =
2428                 vmx->nested.nested_vmx_entry_ctls_low &
2429                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430 
2431         /* cpu-based controls */
2432         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2433                 vmx->nested.nested_vmx_procbased_ctls_low,
2434                 vmx->nested.nested_vmx_procbased_ctls_high);
2435         vmx->nested.nested_vmx_procbased_ctls_low =
2436                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437         vmx->nested.nested_vmx_procbased_ctls_high &=
2438                 CPU_BASED_VIRTUAL_INTR_PENDING |
2439                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2440                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442                 CPU_BASED_CR3_STORE_EXITING |
2443 #ifdef CONFIG_X86_64
2444                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445 #endif
2446                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2447                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2448                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2449                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2450                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2451         /*
2452          * We can allow some features even when not supported by the
2453          * hardware. For example, L1 can specify an MSR bitmap - and we
2454          * can use it to avoid exits to L1 - even when L0 runs L2
2455          * without MSR bitmaps.
2456          */
2457         vmx->nested.nested_vmx_procbased_ctls_high |=
2458                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2459                 CPU_BASED_USE_MSR_BITMAPS;
2460 
2461         /* We support free control of CR3 access interception. */
2462         vmx->nested.nested_vmx_true_procbased_ctls_low =
2463                 vmx->nested.nested_vmx_procbased_ctls_low &
2464                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465 
2466         /* secondary cpu-based controls */
2467         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2468                 vmx->nested.nested_vmx_secondary_ctls_low,
2469                 vmx->nested.nested_vmx_secondary_ctls_high);
2470         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471         vmx->nested.nested_vmx_secondary_ctls_high &=
2472                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2473                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2474                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2475                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2476                 SECONDARY_EXEC_WBINVD_EXITING |
2477                 SECONDARY_EXEC_XSAVES;
2478 
2479         if (enable_ept) {
2480                 /* nested EPT: emulate EPT also to L1 */
2481                 vmx->nested.nested_vmx_secondary_ctls_high |=
2482                         SECONDARY_EXEC_ENABLE_EPT;
2483                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2484                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2485                          VMX_EPT_INVEPT_BIT;
2486                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2487                 /*
2488                  * For nested guests, we don't do anything specific
2489                  * for single context invalidation. Hence, only advertise
2490                  * support for global context invalidation.
2491                  */
2492                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2493         } else
2494                 vmx->nested.nested_vmx_ept_caps = 0;
2495 
2496         if (enable_unrestricted_guest)
2497                 vmx->nested.nested_vmx_secondary_ctls_high |=
2498                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2499 
2500         /* miscellaneous data */
2501         rdmsr(MSR_IA32_VMX_MISC,
2502                 vmx->nested.nested_vmx_misc_low,
2503                 vmx->nested.nested_vmx_misc_high);
2504         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2505         vmx->nested.nested_vmx_misc_low |=
2506                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2507                 VMX_MISC_ACTIVITY_HLT;
2508         vmx->nested.nested_vmx_misc_high = 0;
2509 }
2510 
2511 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2512 {
2513         /*
2514          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2515          */
2516         return ((control & high) | low) == control;
2517 }
2518 
2519 static inline u64 vmx_control_msr(u32 low, u32 high)
2520 {
2521         return low | ((u64)high << 32);
2522 }
2523 
2524 /* Returns 0 on success, non-0 otherwise. */
2525 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2526 {
2527         struct vcpu_vmx *vmx = to_vmx(vcpu);
2528 
2529         switch (msr_index) {
2530         case MSR_IA32_VMX_BASIC:
2531                 /*
2532                  * This MSR reports some information about VMX support. We
2533                  * should return information about the VMX we emulate for the
2534                  * guest, and the VMCS structure we give it - not about the
2535                  * VMX support of the underlying hardware.
2536                  */
2537                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2538                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2539                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2540                 break;
2541         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2542         case MSR_IA32_VMX_PINBASED_CTLS:
2543                 *pdata = vmx_control_msr(
2544                         vmx->nested.nested_vmx_pinbased_ctls_low,
2545                         vmx->nested.nested_vmx_pinbased_ctls_high);
2546                 break;
2547         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2548                 *pdata = vmx_control_msr(
2549                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2550                         vmx->nested.nested_vmx_procbased_ctls_high);
2551                 break;
2552         case MSR_IA32_VMX_PROCBASED_CTLS:
2553                 *pdata = vmx_control_msr(
2554                         vmx->nested.nested_vmx_procbased_ctls_low,
2555                         vmx->nested.nested_vmx_procbased_ctls_high);
2556                 break;
2557         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2558                 *pdata = vmx_control_msr(
2559                         vmx->nested.nested_vmx_true_exit_ctls_low,
2560                         vmx->nested.nested_vmx_exit_ctls_high);
2561                 break;
2562         case MSR_IA32_VMX_EXIT_CTLS:
2563                 *pdata = vmx_control_msr(
2564                         vmx->nested.nested_vmx_exit_ctls_low,
2565                         vmx->nested.nested_vmx_exit_ctls_high);
2566                 break;
2567         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2568                 *pdata = vmx_control_msr(
2569                         vmx->nested.nested_vmx_true_entry_ctls_low,
2570                         vmx->nested.nested_vmx_entry_ctls_high);
2571                 break;
2572         case MSR_IA32_VMX_ENTRY_CTLS:
2573                 *pdata = vmx_control_msr(
2574                         vmx->nested.nested_vmx_entry_ctls_low,
2575                         vmx->nested.nested_vmx_entry_ctls_high);
2576                 break;
2577         case MSR_IA32_VMX_MISC:
2578                 *pdata = vmx_control_msr(
2579                         vmx->nested.nested_vmx_misc_low,
2580                         vmx->nested.nested_vmx_misc_high);
2581                 break;
2582         /*
2583          * These MSRs specify bits which the guest must keep fixed (on or off)
2584          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2585          * We picked the standard core2 setting.
2586          */
2587 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2588 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2589         case MSR_IA32_VMX_CR0_FIXED0:
2590                 *pdata = VMXON_CR0_ALWAYSON;
2591                 break;
2592         case MSR_IA32_VMX_CR0_FIXED1:
2593                 *pdata = -1ULL;
2594                 break;
2595         case MSR_IA32_VMX_CR4_FIXED0:
2596                 *pdata = VMXON_CR4_ALWAYSON;
2597                 break;
2598         case MSR_IA32_VMX_CR4_FIXED1:
2599                 *pdata = -1ULL;
2600                 break;
2601         case MSR_IA32_VMX_VMCS_ENUM:
2602                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2603                 break;
2604         case MSR_IA32_VMX_PROCBASED_CTLS2:
2605                 *pdata = vmx_control_msr(
2606                         vmx->nested.nested_vmx_secondary_ctls_low,
2607                         vmx->nested.nested_vmx_secondary_ctls_high);
2608                 break;
2609         case MSR_IA32_VMX_EPT_VPID_CAP:
2610                 /* Currently, no nested vpid support */
2611                 *pdata = vmx->nested.nested_vmx_ept_caps;
2612                 break;
2613         default:
2614                 return 1;
2615         }
2616 
2617         return 0;
2618 }
2619 
2620 /*
2621  * Reads an msr value (of 'msr_index') into 'pdata'.
2622  * Returns 0 on success, non-0 otherwise.
2623  * Assumes vcpu_load() was already called.
2624  */
2625 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2626 {
2627         u64 data;
2628         struct shared_msr_entry *msr;
2629 
2630         if (!pdata) {
2631                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2632                 return -EINVAL;
2633         }
2634 
2635         switch (msr_index) {
2636 #ifdef CONFIG_X86_64
2637         case MSR_FS_BASE:
2638                 data = vmcs_readl(GUEST_FS_BASE);
2639                 break;
2640         case MSR_GS_BASE:
2641                 data = vmcs_readl(GUEST_GS_BASE);
2642                 break;
2643         case MSR_KERNEL_GS_BASE:
2644                 vmx_load_host_state(to_vmx(vcpu));
2645                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2646                 break;
2647 #endif
2648         case MSR_EFER:
2649                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2650         case MSR_IA32_TSC:
2651                 data = guest_read_tsc();
2652                 break;
2653         case MSR_IA32_SYSENTER_CS:
2654                 data = vmcs_read32(GUEST_SYSENTER_CS);
2655                 break;
2656         case MSR_IA32_SYSENTER_EIP:
2657                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2658                 break;
2659         case MSR_IA32_SYSENTER_ESP:
2660                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2661                 break;
2662         case MSR_IA32_BNDCFGS:
2663                 if (!vmx_mpx_supported())
2664                         return 1;
2665                 data = vmcs_read64(GUEST_BNDCFGS);
2666                 break;
2667         case MSR_IA32_FEATURE_CONTROL:
2668                 if (!nested_vmx_allowed(vcpu))
2669                         return 1;
2670                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2671                 break;
2672         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2673                 if (!nested_vmx_allowed(vcpu))
2674                         return 1;
2675                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2676         case MSR_IA32_XSS:
2677                 if (!vmx_xsaves_supported())
2678                         return 1;
2679                 data = vcpu->arch.ia32_xss;
2680                 break;
2681         case MSR_TSC_AUX:
2682                 if (!to_vmx(vcpu)->rdtscp_enabled)
2683                         return 1;
2684                 /* Otherwise falls through */
2685         default:
2686                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2687                 if (msr) {
2688                         data = msr->data;
2689                         break;
2690                 }
2691                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2692         }
2693 
2694         *pdata = data;
2695         return 0;
2696 }
2697 
2698 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2699 
2700 /*
2701  * Writes msr value into into the appropriate "register".
2702  * Returns 0 on success, non-0 otherwise.
2703  * Assumes vcpu_load() was already called.
2704  */
2705 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2706 {
2707         struct vcpu_vmx *vmx = to_vmx(vcpu);
2708         struct shared_msr_entry *msr;
2709         int ret = 0;
2710         u32 msr_index = msr_info->index;
2711         u64 data = msr_info->data;
2712 
2713         switch (msr_index) {
2714         case MSR_EFER:
2715                 ret = kvm_set_msr_common(vcpu, msr_info);
2716                 break;
2717 #ifdef CONFIG_X86_64
2718         case MSR_FS_BASE:
2719                 vmx_segment_cache_clear(vmx);
2720                 vmcs_writel(GUEST_FS_BASE, data);
2721                 break;
2722         case MSR_GS_BASE:
2723                 vmx_segment_cache_clear(vmx);
2724                 vmcs_writel(GUEST_GS_BASE, data);
2725                 break;
2726         case MSR_KERNEL_GS_BASE:
2727                 vmx_load_host_state(vmx);
2728                 vmx->msr_guest_kernel_gs_base = data;
2729                 break;
2730 #endif
2731         case MSR_IA32_SYSENTER_CS:
2732                 vmcs_write32(GUEST_SYSENTER_CS, data);
2733                 break;
2734         case MSR_IA32_SYSENTER_EIP:
2735                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2736                 break;
2737         case MSR_IA32_SYSENTER_ESP:
2738                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2739                 break;
2740         case MSR_IA32_BNDCFGS:
2741                 if (!vmx_mpx_supported())
2742                         return 1;
2743                 vmcs_write64(GUEST_BNDCFGS, data);
2744                 break;
2745         case MSR_IA32_TSC:
2746                 kvm_write_tsc(vcpu, msr_info);
2747                 break;
2748         case MSR_IA32_CR_PAT:
2749                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2750                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2751                                 return 1;
2752                         vmcs_write64(GUEST_IA32_PAT, data);
2753                         vcpu->arch.pat = data;
2754                         break;
2755                 }
2756                 ret = kvm_set_msr_common(vcpu, msr_info);
2757                 break;
2758         case MSR_IA32_TSC_ADJUST:
2759                 ret = kvm_set_msr_common(vcpu, msr_info);
2760                 break;
2761         case MSR_IA32_FEATURE_CONTROL:
2762                 if (!nested_vmx_allowed(vcpu) ||
2763                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2764                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2765                         return 1;
2766                 vmx->nested.msr_ia32_feature_control = data;
2767                 if (msr_info->host_initiated && data == 0)
2768                         vmx_leave_nested(vcpu);
2769                 break;
2770         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2771                 return 1; /* they are read-only */
2772         case MSR_IA32_XSS:
2773                 if (!vmx_xsaves_supported())
2774                         return 1;
2775                 /*
2776                  * The only supported bit as of Skylake is bit 8, but
2777                  * it is not supported on KVM.
2778                  */
2779                 if (data != 0)
2780                         return 1;
2781                 vcpu->arch.ia32_xss = data;
2782                 if (vcpu->arch.ia32_xss != host_xss)
2783                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2784                                 vcpu->arch.ia32_xss, host_xss);
2785                 else
2786                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2787                 break;
2788         case MSR_TSC_AUX:
2789                 if (!vmx->rdtscp_enabled)
2790                         return 1;
2791                 /* Check reserved bit, higher 32 bits should be zero */
2792                 if ((data >> 32) != 0)
2793                         return 1;
2794                 /* Otherwise falls through */
2795         default:
2796                 msr = find_msr_entry(vmx, msr_index);
2797                 if (msr) {
2798                         u64 old_msr_data = msr->data;
2799                         msr->data = data;
2800                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2801                                 preempt_disable();
2802                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2803                                                          msr->mask);
2804                                 preempt_enable();
2805                                 if (ret)
2806                                         msr->data = old_msr_data;
2807                         }
2808                         break;
2809                 }
2810                 ret = kvm_set_msr_common(vcpu, msr_info);
2811         }
2812 
2813         return ret;
2814 }
2815 
2816 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2817 {
2818         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2819         switch (reg) {
2820         case VCPU_REGS_RSP:
2821                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2822                 break;
2823         case VCPU_REGS_RIP:
2824                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2825                 break;
2826         case VCPU_EXREG_PDPTR:
2827                 if (enable_ept)
2828                         ept_save_pdptrs(vcpu);
2829                 break;
2830         default:
2831                 break;
2832         }
2833 }
2834 
2835 static __init int cpu_has_kvm_support(void)
2836 {
2837         return cpu_has_vmx();
2838 }
2839 
2840 static __init int vmx_disabled_by_bios(void)
2841 {
2842         u64 msr;
2843 
2844         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2845         if (msr & FEATURE_CONTROL_LOCKED) {
2846                 /* launched w/ TXT and VMX disabled */
2847                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2848                         && tboot_enabled())
2849                         return 1;
2850                 /* launched w/o TXT and VMX only enabled w/ TXT */
2851                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2852                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2853                         && !tboot_enabled()) {
2854                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2855                                 "activate TXT before enabling KVM\n");
2856                         return 1;
2857                 }
2858                 /* launched w/o TXT and VMX disabled */
2859                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2860                         && !tboot_enabled())
2861                         return 1;
2862         }
2863 
2864         return 0;
2865 }
2866 
2867 static void kvm_cpu_vmxon(u64 addr)
2868 {
2869         asm volatile (ASM_VMX_VMXON_RAX
2870                         : : "a"(&addr), "m"(addr)
2871                         : "memory", "cc");
2872 }
2873 
2874 static int hardware_enable(void)
2875 {
2876         int cpu = raw_smp_processor_id();
2877         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2878         u64 old, test_bits;
2879 
2880         if (cr4_read_shadow() & X86_CR4_VMXE)
2881                 return -EBUSY;
2882 
2883         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2884 
2885         /*
2886          * Now we can enable the vmclear operation in kdump
2887          * since the loaded_vmcss_on_cpu list on this cpu
2888          * has been initialized.
2889          *
2890          * Though the cpu is not in VMX operation now, there
2891          * is no problem to enable the vmclear operation
2892          * for the loaded_vmcss_on_cpu list is empty!
2893          */
2894         crash_enable_local_vmclear(cpu);
2895 
2896         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2897 
2898         test_bits = FEATURE_CONTROL_LOCKED;
2899         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2900         if (tboot_enabled())
2901                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2902 
2903         if ((old & test_bits) != test_bits) {
2904                 /* enable and lock */
2905                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2906         }
2907         cr4_set_bits(X86_CR4_VMXE);
2908 
2909         if (vmm_exclusive) {
2910                 kvm_cpu_vmxon(phys_addr);
2911                 ept_sync_global();
2912         }
2913 
2914         native_store_gdt(this_cpu_ptr(&host_gdt));
2915 
2916         return 0;
2917 }
2918 
2919 static void vmclear_local_loaded_vmcss(void)
2920 {
2921         int cpu = raw_smp_processor_id();
2922         struct loaded_vmcs *v, *n;
2923 
2924         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2925                                  loaded_vmcss_on_cpu_link)
2926                 __loaded_vmcs_clear(v);
2927 }
2928 
2929 
2930 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2931  * tricks.
2932  */
2933 static void kvm_cpu_vmxoff(void)
2934 {
2935         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2936 }
2937 
2938 static void hardware_disable(void)
2939 {
2940         if (vmm_exclusive) {
2941                 vmclear_local_loaded_vmcss();
2942                 kvm_cpu_vmxoff();
2943         }
2944         cr4_clear_bits(X86_CR4_VMXE);
2945 }
2946 
2947 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2948                                       u32 msr, u32 *result)
2949 {
2950         u32 vmx_msr_low, vmx_msr_high;
2951         u32 ctl = ctl_min | ctl_opt;
2952 
2953         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2954 
2955         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2956         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2957 
2958         /* Ensure minimum (required) set of control bits are supported. */
2959         if (ctl_min & ~ctl)
2960                 return -EIO;
2961 
2962         *result = ctl;
2963         return 0;
2964 }
2965 
2966 static __init bool allow_1_setting(u32 msr, u32 ctl)
2967 {
2968         u32 vmx_msr_low, vmx_msr_high;
2969 
2970         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2971         return vmx_msr_high & ctl;
2972 }
2973 
2974 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2975 {
2976         u32 vmx_msr_low, vmx_msr_high;
2977         u32 min, opt, min2, opt2;
2978         u32 _pin_based_exec_control = 0;
2979         u32 _cpu_based_exec_control = 0;
2980         u32 _cpu_based_2nd_exec_control = 0;
2981         u32 _vmexit_control = 0;
2982         u32 _vmentry_control = 0;
2983 
2984         min = CPU_BASED_HLT_EXITING |
2985 #ifdef CONFIG_X86_64
2986               CPU_BASED_CR8_LOAD_EXITING |
2987               CPU_BASED_CR8_STORE_EXITING |
2988 #endif
2989               CPU_BASED_CR3_LOAD_EXITING |
2990               CPU_BASED_CR3_STORE_EXITING |
2991               CPU_BASED_USE_IO_BITMAPS |
2992               CPU_BASED_MOV_DR_EXITING |
2993               CPU_BASED_USE_TSC_OFFSETING |
2994               CPU_BASED_MWAIT_EXITING |
2995               CPU_BASED_MONITOR_EXITING |
2996               CPU_BASED_INVLPG_EXITING |
2997               CPU_BASED_RDPMC_EXITING;
2998 
2999         opt = CPU_BASED_TPR_SHADOW |
3000               CPU_BASED_USE_MSR_BITMAPS |
3001               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3002         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3003                                 &_cpu_based_exec_control) < 0)
3004                 return -EIO;
3005 #ifdef CONFIG_X86_64
3006         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3007                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3008                                            ~CPU_BASED_CR8_STORE_EXITING;
3009 #endif
3010         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3011                 min2 = 0;
3012                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3013                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3014                         SECONDARY_EXEC_WBINVD_EXITING |
3015                         SECONDARY_EXEC_ENABLE_VPID |
3016                         SECONDARY_EXEC_ENABLE_EPT |
3017                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3018                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3019                         SECONDARY_EXEC_RDTSCP |
3020                         SECONDARY_EXEC_ENABLE_INVPCID |
3021                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3022                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3023                         SECONDARY_EXEC_SHADOW_VMCS |
3024                         SECONDARY_EXEC_XSAVES |
3025                         SECONDARY_EXEC_ENABLE_PML;
3026                 if (adjust_vmx_controls(min2, opt2,
3027                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3028                                         &_cpu_based_2nd_exec_control) < 0)
3029                         return -EIO;
3030         }
3031 #ifndef CONFIG_X86_64
3032         if (!(_cpu_based_2nd_exec_control &
3033                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3034                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3035 #endif
3036 
3037         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3038                 _cpu_based_2nd_exec_control &= ~(
3039                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3040                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3041                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3042 
3043         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3044                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3045                    enabled */
3046                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3047                                              CPU_BASED_CR3_STORE_EXITING |
3048                                              CPU_BASED_INVLPG_EXITING);
3049                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3050                       vmx_capability.ept, vmx_capability.vpid);
3051         }
3052 
3053         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3054 #ifdef CONFIG_X86_64
3055         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3056 #endif
3057         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3058                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3059         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3060                                 &_vmexit_control) < 0)
3061                 return -EIO;
3062 
3063         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3064         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3065         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3066                                 &_pin_based_exec_control) < 0)
3067                 return -EIO;
3068 
3069         if (!(_cpu_based_2nd_exec_control &
3070                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3071                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3072                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3073 
3074         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3075         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3076         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3077                                 &_vmentry_control) < 0)
3078                 return -EIO;
3079 
3080         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3081 
3082         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3083         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3084                 return -EIO;
3085 
3086 #ifdef CONFIG_X86_64
3087         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3088         if (vmx_msr_high & (1u<<16))
3089                 return -EIO;
3090 #endif
3091 
3092         /* Require Write-Back (WB) memory type for VMCS accesses. */
3093         if (((vmx_msr_high >> 18) & 15) != 6)
3094                 return -EIO;
3095 
3096         vmcs_conf->size = vmx_msr_high & 0x1fff;
3097         vmcs_conf->order = get_order(vmcs_config.size);
3098         vmcs_conf->revision_id = vmx_msr_low;
3099 
3100         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3101         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3102         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3103         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3104         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3105 
3106         cpu_has_load_ia32_efer =
3107                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3108                                 VM_ENTRY_LOAD_IA32_EFER)
3109                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3110                                    VM_EXIT_LOAD_IA32_EFER);
3111 
3112         cpu_has_load_perf_global_ctrl =
3113                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3114                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3115                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3116                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3117 
3118         /*
3119          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3120          * but due to arrata below it can't be used. Workaround is to use
3121          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3122          *
3123          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3124          *
3125          * AAK155             (model 26)
3126          * AAP115             (model 30)
3127          * AAT100             (model 37)
3128          * BC86,AAY89,BD102   (model 44)
3129          * BA97               (model 46)
3130          *
3131          */
3132         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3133                 switch (boot_cpu_data.x86_model) {
3134                 case 26:
3135                 case 30:
3136                 case 37:
3137                 case 44:
3138                 case 46:
3139                         cpu_has_load_perf_global_ctrl = false;
3140                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3141                                         "does not work properly. Using workaround\n");
3142                         break;
3143                 default:
3144                         break;
3145                 }
3146         }
3147 
3148         if (cpu_has_xsaves)
3149                 rdmsrl(MSR_IA32_XSS, host_xss);
3150 
3151         return 0;
3152 }
3153 
3154 static struct vmcs *alloc_vmcs_cpu(int cpu)
3155 {
3156         int node = cpu_to_node(cpu);
3157         struct page *pages;
3158         struct vmcs *vmcs;
3159 
3160         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3161         if (!pages)
3162                 return NULL;
3163         vmcs = page_address(pages);
3164         memset(vmcs, 0, vmcs_config.size);
3165         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3166         return vmcs;
3167 }
3168 
3169 static struct vmcs *alloc_vmcs(void)
3170 {
3171         return alloc_vmcs_cpu(raw_smp_processor_id());
3172 }
3173 
3174 static void free_vmcs(struct vmcs *vmcs)
3175 {
3176         free_pages((unsigned long)vmcs, vmcs_config.order);
3177 }
3178 
3179 /*
3180  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3181  */
3182 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3183 {
3184         if (!loaded_vmcs->vmcs)
3185                 return;
3186         loaded_vmcs_clear(loaded_vmcs);
3187         free_vmcs(loaded_vmcs->vmcs);
3188         loaded_vmcs->vmcs = NULL;
3189 }
3190 
3191 static void free_kvm_area(void)
3192 {
3193         int cpu;
3194 
3195         for_each_possible_cpu(cpu) {
3196                 free_vmcs(per_cpu(vmxarea, cpu));
3197                 per_cpu(vmxarea, cpu) = NULL;
3198         }
3199 }
3200 
3201 static void init_vmcs_shadow_fields(void)
3202 {
3203         int i, j;
3204 
3205         /* No checks for read only fields yet */
3206 
3207         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3208                 switch (shadow_read_write_fields[i]) {
3209                 case GUEST_BNDCFGS:
3210                         if (!vmx_mpx_supported())
3211                                 continue;
3212                         break;
3213                 default:
3214                         break;
3215                 }
3216 
3217                 if (j < i)
3218                         shadow_read_write_fields[j] =
3219                                 shadow_read_write_fields[i];
3220                 j++;
3221         }
3222         max_shadow_read_write_fields = j;
3223 
3224         /* shadowed fields guest access without vmexit */
3225         for (i = 0; i < max_shadow_read_write_fields; i++) {
3226                 clear_bit(shadow_read_write_fields[i],
3227                           vmx_vmwrite_bitmap);
3228                 clear_bit(shadow_read_write_fields[i],
3229                           vmx_vmread_bitmap);
3230         }
3231         for (i = 0; i < max_shadow_read_only_fields; i++)
3232                 clear_bit(shadow_read_only_fields[i],
3233                           vmx_vmread_bitmap);
3234 }
3235 
3236 static __init int alloc_kvm_area(void)
3237 {
3238         int cpu;
3239 
3240         for_each_possible_cpu(cpu) {
3241                 struct vmcs *vmcs;
3242 
3243                 vmcs = alloc_vmcs_cpu(cpu);
3244                 if (!vmcs) {
3245                         free_kvm_area();
3246                         return -ENOMEM;
3247                 }
3248 
3249                 per_cpu(vmxarea, cpu) = vmcs;
3250         }
3251         return 0;
3252 }
3253 
3254 static bool emulation_required(struct kvm_vcpu *vcpu)
3255 {
3256         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3257 }
3258 
3259 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3260                 struct kvm_segment *save)
3261 {
3262         if (!emulate_invalid_guest_state) {
3263                 /*
3264                  * CS and SS RPL should be equal during guest entry according
3265                  * to VMX spec, but in reality it is not always so. Since vcpu
3266                  * is in the middle of the transition from real mode to
3267                  * protected mode it is safe to assume that RPL 0 is a good
3268                  * default value.
3269                  */
3270                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3271                         save->selector &= ~SELECTOR_RPL_MASK;
3272                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3273                 save->s = 1;
3274         }
3275         vmx_set_segment(vcpu, save, seg);
3276 }
3277 
3278 static void enter_pmode(struct kvm_vcpu *vcpu)
3279 {
3280         unsigned long flags;
3281         struct vcpu_vmx *vmx = to_vmx(vcpu);
3282 
3283         /*
3284          * Update real mode segment cache. It may be not up-to-date if sement
3285          * register was written while vcpu was in a guest mode.
3286          */
3287         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3288         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3289         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3290         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3291         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3292         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3293 
3294         vmx->rmode.vm86_active = 0;
3295 
3296         vmx_segment_cache_clear(vmx);
3297 
3298         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3299 
3300         flags = vmcs_readl(GUEST_RFLAGS);
3301         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3302         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3303         vmcs_writel(GUEST_RFLAGS, flags);
3304 
3305         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3306                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3307 
3308         update_exception_bitmap(vcpu);
3309 
3310         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3311         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3312         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3313         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3314         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3315         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3316 }
3317 
3318 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3319 {
3320         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3321         struct kvm_segment var = *save;
3322 
3323         var.dpl = 0x3;
3324         if (seg == VCPU_SREG_CS)
3325                 var.type = 0x3;
3326 
3327         if (!emulate_invalid_guest_state) {
3328                 var.selector = var.base >> 4;
3329                 var.base = var.base & 0xffff0;
3330                 var.limit = 0xffff;
3331                 var.g = 0;
3332                 var.db = 0;
3333                 var.present = 1;
3334                 var.s = 1;
3335                 var.l = 0;
3336                 var.unusable = 0;
3337                 var.type = 0x3;
3338                 var.avl = 0;
3339                 if (save->base & 0xf)
3340                         printk_once(KERN_WARNING "kvm: segment base is not "
3341                                         "paragraph aligned when entering "
3342                                         "protected mode (seg=%d)", seg);
3343         }
3344 
3345         vmcs_write16(sf->selector, var.selector);
3346         vmcs_write32(sf->base, var.base);
3347         vmcs_write32(sf->limit, var.limit);
3348         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3349 }
3350 
3351 static void enter_rmode(struct kvm_vcpu *vcpu)
3352 {
3353         unsigned long flags;
3354         struct vcpu_vmx *vmx = to_vmx(vcpu);
3355 
3356         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3357         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3358         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3359         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3360         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3361         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3362         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3363 
3364         vmx->rmode.vm86_active = 1;
3365 
3366         /*
3367          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3368          * vcpu. Warn the user that an update is overdue.
3369          */
3370         if (!vcpu->kvm->arch.tss_addr)
3371                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3372                              "called before entering vcpu\n");
3373 
3374         vmx_segment_cache_clear(vmx);
3375 
3376         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3377         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3378         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3379 
3380         flags = vmcs_readl(GUEST_RFLAGS);
3381         vmx->rmode.save_rflags = flags;
3382 
3383         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3384 
3385         vmcs_writel(GUEST_RFLAGS, flags);
3386         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3387         update_exception_bitmap(vcpu);
3388 
3389         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3390         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3391         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3392         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3393         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3394         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3395 
3396         kvm_mmu_reset_context(vcpu);
3397 }
3398 
3399 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3400 {
3401         struct vcpu_vmx *vmx = to_vmx(vcpu);
3402         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3403 
3404         if (!msr)
3405                 return;
3406 
3407         /*
3408          * Force kernel_gs_base reloading before EFER changes, as control
3409          * of this msr depends on is_long_mode().
3410          */
3411         vmx_load_host_state(to_vmx(vcpu));
3412         vcpu->arch.efer = efer;
3413         if (efer & EFER_LMA) {
3414                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3415                 msr->data = efer;
3416         } else {
3417                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3418 
3419                 msr->data = efer & ~EFER_LME;
3420         }
3421         setup_msrs(vmx);
3422 }
3423 
3424 #ifdef CONFIG_X86_64
3425 
3426 static void enter_lmode(struct kvm_vcpu *vcpu)
3427 {
3428         u32 guest_tr_ar;
3429 
3430         vmx_segment_cache_clear(to_vmx(vcpu));
3431 
3432         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3433         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3434                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3435                                      __func__);
3436                 vmcs_write32(GUEST_TR_AR_BYTES,
3437                              (guest_tr_ar & ~AR_TYPE_MASK)
3438                              | AR_TYPE_BUSY_64_TSS);
3439         }
3440         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3441 }
3442 
3443 static void exit_lmode(struct kvm_vcpu *vcpu)
3444 {
3445         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3446         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3447 }
3448 
3449 #endif
3450 
3451 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3452 {
3453         vpid_sync_context(to_vmx(vcpu));
3454         if (enable_ept) {
3455                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3456                         return;
3457                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3458         }
3459 }
3460 
3461 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3462 {
3463         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3464 
3465         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3466         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3467 }
3468 
3469 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3470 {
3471         if (enable_ept && is_paging(vcpu))
3472                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3473         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3474 }
3475 
3476 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3477 {
3478         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3479 
3480         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3481         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3482 }
3483 
3484 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3485 {
3486         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3487 
3488         if (!test_bit(VCPU_EXREG_PDPTR,
3489                       (unsigned long *)&vcpu->arch.regs_dirty))
3490                 return;
3491 
3492         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3493                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3494                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3495                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3496                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3497         }
3498 }
3499 
3500 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3501 {
3502         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3503 
3504         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3505                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3506                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3507                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3508                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3509         }
3510 
3511         __set_bit(VCPU_EXREG_PDPTR,
3512                   (unsigned long *)&vcpu->arch.regs_avail);
3513         __set_bit(VCPU_EXREG_PDPTR,
3514                   (unsigned long *)&vcpu->arch.regs_dirty);
3515 }
3516 
3517 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3518 
3519 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3520                                         unsigned long cr0,
3521                                         struct kvm_vcpu *vcpu)
3522 {
3523         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3524                 vmx_decache_cr3(vcpu);
3525         if (!(cr0 & X86_CR0_PG)) {
3526                 /* From paging/starting to nonpaging */
3527                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3528                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3529                              (CPU_BASED_CR3_LOAD_EXITING |
3530                               CPU_BASED_CR3_STORE_EXITING));
3531                 vcpu->arch.cr0 = cr0;
3532                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3533         } else if (!is_paging(vcpu)) {
3534                 /* From nonpaging to paging */
3535                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3536                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3537                              ~(CPU_BASED_CR3_LOAD_EXITING |
3538                                CPU_BASED_CR3_STORE_EXITING));
3539                 vcpu->arch.cr0 = cr0;
3540                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3541         }
3542 
3543         if (!(cr0 & X86_CR0_WP))
3544                 *hw_cr0 &= ~X86_CR0_WP;
3545 }
3546 
3547 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3548 {
3549         struct vcpu_vmx *vmx = to_vmx(vcpu);
3550         unsigned long hw_cr0;
3551 
3552         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3553         if (enable_unrestricted_guest)
3554                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3555         else {
3556                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3557 
3558                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3559                         enter_pmode(vcpu);
3560 
3561                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3562                         enter_rmode(vcpu);
3563         }
3564 
3565 #ifdef CONFIG_X86_64
3566         if (vcpu->arch.efer & EFER_LME) {
3567                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3568                         enter_lmode(vcpu);
3569                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3570                         exit_lmode(vcpu);
3571         }
3572 #endif
3573 
3574         if (enable_ept)
3575                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3576 
3577         if (!vcpu->fpu_active)
3578                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3579 
3580         vmcs_writel(CR0_READ_SHADOW, cr0);
3581         vmcs_writel(GUEST_CR0, hw_cr0);
3582         vcpu->arch.cr0 = cr0;
3583 
3584         /* depends on vcpu->arch.cr0 to be set to a new value */
3585         vmx->emulation_required = emulation_required(vcpu);
3586 }
3587 
3588 static u64 construct_eptp(unsigned long root_hpa)
3589 {
3590         u64 eptp;
3591 
3592         /* TODO write the value reading from MSR */
3593         eptp = VMX_EPT_DEFAULT_MT |
3594                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3595         if (enable_ept_ad_bits)
3596                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3597         eptp |= (root_hpa & PAGE_MASK);
3598 
3599         return eptp;
3600 }
3601 
3602 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3603 {
3604         unsigned long guest_cr3;
3605         u64 eptp;
3606 
3607         guest_cr3 = cr3;
3608         if (enable_ept) {
3609                 eptp = construct_eptp(cr3);
3610                 vmcs_write64(EPT_POINTER, eptp);
3611                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3612                         guest_cr3 = kvm_read_cr3(vcpu);
3613                 else
3614                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3615                 ept_load_pdptrs(vcpu);
3616         }
3617 
3618         vmx_flush_tlb(vcpu);
3619         vmcs_writel(GUEST_CR3, guest_cr3);
3620 }
3621 
3622 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3623 {
3624         /*
3625          * Pass through host's Machine Check Enable value to hw_cr4, which
3626          * is in force while we are in guest mode.  Do not let guests control
3627          * this bit, even if host CR4.MCE == 0.
3628          */
3629         unsigned long hw_cr4 =
3630                 (cr4_read_shadow() & X86_CR4_MCE) |
3631                 (cr4 & ~X86_CR4_MCE) |
3632                 (to_vmx(vcpu)->rmode.vm86_active ?
3633                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3634 
3635         if (cr4 & X86_CR4_VMXE) {
3636                 /*
3637                  * To use VMXON (and later other VMX instructions), a guest
3638                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3639                  * So basically the check on whether to allow nested VMX
3640                  * is here.
3641                  */
3642                 if (!nested_vmx_allowed(vcpu))
3643                         return 1;
3644         }
3645         if (to_vmx(vcpu)->nested.vmxon &&
3646             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3647                 return 1;
3648 
3649         vcpu->arch.cr4 = cr4;
3650         if (enable_ept) {
3651                 if (!is_paging(vcpu)) {
3652                         hw_cr4 &= ~X86_CR4_PAE;
3653                         hw_cr4 |= X86_CR4_PSE;
3654                         /*
3655                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3656                          * in hardware. However KVM always uses paging mode to
3657                          * emulate guest non-paging mode with TDP.
3658                          * To emulate this behavior, SMEP/SMAP needs to be
3659                          * manually disabled when guest switches to non-paging
3660                          * mode.
3661                          */
3662                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3663                 } else if (!(cr4 & X86_CR4_PAE)) {
3664                         hw_cr4 &= ~X86_CR4_PAE;
3665                 }
3666         }
3667 
3668         vmcs_writel(CR4_READ_SHADOW, cr4);
3669         vmcs_writel(GUEST_CR4, hw_cr4);
3670         return 0;
3671 }
3672 
3673 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3674                             struct kvm_segment *var, int seg)
3675 {
3676         struct vcpu_vmx *vmx = to_vmx(vcpu);
3677         u32 ar;
3678 
3679         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3680                 *var = vmx->rmode.segs[seg];
3681                 if (seg == VCPU_SREG_TR
3682                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3683                         return;
3684                 var->base = vmx_read_guest_seg_base(vmx, seg);
3685                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3686                 return;
3687         }
3688         var->base = vmx_read_guest_seg_base(vmx, seg);
3689         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3690         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3691         ar = vmx_read_guest_seg_ar(vmx, seg);
3692         var->unusable = (ar >> 16) & 1;
3693         var->type = ar & 15;
3694         var->s = (ar >> 4) & 1;
3695         var->dpl = (ar >> 5) & 3;
3696         /*
3697          * Some userspaces do not preserve unusable property. Since usable
3698          * segment has to be present according to VMX spec we can use present
3699          * property to amend userspace bug by making unusable segment always
3700          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3701          * segment as unusable.
3702          */
3703         var->present = !var->unusable;
3704         var->avl = (ar >> 12) & 1;
3705         var->l = (ar >> 13) & 1;
3706         var->db = (ar >> 14) & 1;
3707         var->g = (ar >> 15) & 1;
3708 }
3709 
3710 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3711 {
3712         struct kvm_segment s;
3713 
3714         if (to_vmx(vcpu)->rmode.vm86_active) {
3715                 vmx_get_segment(vcpu, &s, seg);
3716                 return s.base;
3717         }
3718         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3719 }
3720 
3721 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3722 {
3723         struct vcpu_vmx *vmx = to_vmx(vcpu);
3724 
3725         if (unlikely(vmx->rmode.vm86_active))
3726                 return 0;
3727         else {
3728                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3729                 return AR_DPL(ar);
3730         }
3731 }
3732 
3733 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3734 {
3735         u32 ar;
3736 
3737         if (var->unusable || !var->present)
3738                 ar = 1 << 16;
3739         else {
3740                 ar = var->type & 15;
3741                 ar |= (var->s & 1) << 4;
3742                 ar |= (var->dpl & 3) << 5;
3743                 ar |= (var->present & 1) << 7;
3744                 ar |= (var->avl & 1) << 12;
3745                 ar |= (var->l & 1) << 13;
3746                 ar |= (var->db & 1) << 14;
3747                 ar |= (var->g & 1) << 15;
3748         }
3749 
3750         return ar;
3751 }
3752 
3753 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3754                             struct kvm_segment *var, int seg)
3755 {
3756         struct vcpu_vmx *vmx = to_vmx(vcpu);
3757         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3758 
3759         vmx_segment_cache_clear(vmx);
3760 
3761         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3762                 vmx->rmode.segs[seg] = *var;
3763                 if (seg == VCPU_SREG_TR)
3764                         vmcs_write16(sf->selector, var->selector);
3765                 else if (var->s)
3766                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3767                 goto out;
3768         }
3769 
3770         vmcs_writel(sf->base, var->base);
3771         vmcs_write32(sf->limit, var->limit);
3772         vmcs_write16(sf->selector, var->selector);
3773 
3774         /*
3775          *   Fix the "Accessed" bit in AR field of segment registers for older
3776          * qemu binaries.
3777          *   IA32 arch specifies that at the time of processor reset the
3778          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3779          * is setting it to 0 in the userland code. This causes invalid guest
3780          * state vmexit when "unrestricted guest" mode is turned on.
3781          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3782          * tree. Newer qemu binaries with that qemu fix would not need this
3783          * kvm hack.
3784          */
3785         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3786                 var->type |= 0x1; /* Accessed */
3787 
3788         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3789 
3790 out:
3791         vmx->emulation_required = emulation_required(vcpu);
3792 }
3793 
3794 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3795 {
3796         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3797 
3798         *db = (ar >> 14) & 1;
3799         *l = (ar >> 13) & 1;
3800 }
3801 
3802 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3803 {
3804         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3805         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3806 }
3807 
3808 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3809 {
3810         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3811         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3812 }
3813 
3814 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3815 {
3816         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3817         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3818 }
3819 
3820 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3821 {
3822         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3823         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3824 }
3825 
3826 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3827 {
3828         struct kvm_segment var;
3829         u32 ar;
3830 
3831         vmx_get_segment(vcpu, &var, seg);
3832         var.dpl = 0x3;
3833         if (seg == VCPU_SREG_CS)
3834                 var.type = 0x3;
3835         ar = vmx_segment_access_rights(&var);
3836 
3837         if (var.base != (var.selector << 4))
3838                 return false;
3839         if (var.limit != 0xffff)
3840                 return false;
3841         if (ar != 0xf3)
3842                 return false;
3843 
3844         return true;
3845 }
3846 
3847 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3848 {
3849         struct kvm_segment cs;
3850         unsigned int cs_rpl;
3851 
3852         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3853         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3854 
3855         if (cs.unusable)
3856                 return false;
3857         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3858                 return false;
3859         if (!cs.s)
3860                 return false;
3861         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3862                 if (cs.dpl > cs_rpl)
3863                         return false;
3864         } else {
3865                 if (cs.dpl != cs_rpl)
3866                         return false;
3867         }
3868         if (!cs.present)
3869                 return false;
3870 
3871         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3872         return true;
3873 }
3874 
3875 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3876 {
3877         struct kvm_segment ss;
3878         unsigned int ss_rpl;
3879 
3880         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3881         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3882 
3883         if (ss.unusable)
3884                 return true;
3885         if (ss.type != 3 && ss.type != 7)
3886                 return false;
3887         if (!ss.s)
3888                 return false;
3889         if (ss.dpl != ss_rpl) /* DPL != RPL */
3890                 return false;
3891         if (!ss.present)
3892                 return false;
3893 
3894         return true;
3895 }
3896 
3897 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3898 {
3899         struct kvm_segment var;
3900         unsigned int rpl;
3901 
3902         vmx_get_segment(vcpu, &var, seg);
3903         rpl = var.selector & SELECTOR_RPL_MASK;
3904 
3905         if (var.unusable)
3906                 return true;
3907         if (!var.s)
3908                 return false;
3909         if (!var.present)
3910                 return false;
3911         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3912                 if (var.dpl < rpl) /* DPL < RPL */
3913                         return false;
3914         }
3915 
3916         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3917          * rights flags
3918          */
3919         return true;
3920 }
3921 
3922 static bool tr_valid(struct kvm_vcpu *vcpu)
3923 {
3924         struct kvm_segment tr;
3925 
3926         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3927 
3928         if (tr.unusable)
3929                 return false;
3930         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3931                 return false;
3932         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3933                 return false;
3934         if (!tr.present)
3935                 return false;
3936 
3937         return true;
3938 }
3939 
3940 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3941 {
3942         struct kvm_segment ldtr;
3943 
3944         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3945 
3946         if (ldtr.unusable)
3947                 return true;
3948         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3949                 return false;
3950         if (ldtr.type != 2)
3951                 return false;
3952         if (!ldtr.present)
3953                 return false;
3954 
3955         return true;
3956 }
3957 
3958 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3959 {
3960         struct kvm_segment cs, ss;
3961 
3962         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3963         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3964 
3965         return ((cs.selector & SELECTOR_RPL_MASK) ==
3966                  (ss.selector & SELECTOR_RPL_MASK));
3967 }
3968 
3969 /*
3970  * Check if guest state is valid. Returns true if valid, false if
3971  * not.
3972  * We assume that registers are always usable
3973  */
3974 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3975 {
3976         if (enable_unrestricted_guest)
3977                 return true;
3978 
3979         /* real mode guest state checks */
3980         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3981                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3982                         return false;
3983                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3984                         return false;
3985                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3986                         return false;
3987                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3988                         return false;
3989                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3990                         return false;
3991                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3992                         return false;
3993         } else {
3994         /* protected mode guest state checks */
3995                 if (!cs_ss_rpl_check(vcpu))
3996                         return false;
3997                 if (!code_segment_valid(vcpu))
3998                         return false;
3999                 if (!stack_segment_valid(vcpu))
4000                         return false;
4001                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4002                         return false;
4003                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4004                         return false;
4005                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4006                         return false;
4007                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4008                         return false;
4009                 if (!tr_valid(vcpu))
4010                         return false;
4011                 if (!ldtr_valid(vcpu))
4012                         return false;
4013         }
4014         /* TODO:
4015          * - Add checks on RIP
4016          * - Add checks on RFLAGS
4017          */
4018 
4019         return true;
4020 }
4021 
4022 static int init_rmode_tss(struct kvm *kvm)
4023 {
4024         gfn_t fn;
4025         u16 data = 0;
4026         int idx, r;
4027 
4028         idx = srcu_read_lock(&kvm->srcu);
4029         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4030         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4031         if (r < 0)
4032                 goto out;
4033         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4034         r = kvm_write_guest_page(kvm, fn++, &data,
4035                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4036         if (r < 0)
4037                 goto out;
4038         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4039         if (r < 0)
4040                 goto out;
4041         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4042         if (r < 0)
4043                 goto out;
4044         data = ~0;
4045         r = kvm_write_guest_page(kvm, fn, &data,
4046                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4047                                  sizeof(u8));
4048 out:
4049         srcu_read_unlock(&kvm->srcu, idx);
4050         return r;
4051 }
4052 
4053 static int init_rmode_identity_map(struct kvm *kvm)
4054 {
4055         int i, idx, r = 0;
4056         pfn_t identity_map_pfn;
4057         u32 tmp;
4058 
4059         if (!enable_ept)
4060                 return 0;
4061 
4062         /* Protect kvm->arch.ept_identity_pagetable_done. */
4063         mutex_lock(&kvm->slots_lock);
4064 
4065         if (likely(kvm->arch.ept_identity_pagetable_done))
4066                 goto out2;
4067 
4068         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4069 
4070         r = alloc_identity_pagetable(kvm);
4071         if (r < 0)
4072                 goto out2;
4073 
4074         idx = srcu_read_lock(&kvm->srcu);
4075         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4076         if (r < 0)
4077                 goto out;
4078         /* Set up identity-mapping pagetable for EPT in real mode */
4079         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4080                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4081                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4082                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4083                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4084                 if (r < 0)
4085                         goto out;
4086         }
4087         kvm->arch.ept_identity_pagetable_done = true;
4088 
4089 out:
4090         srcu_read_unlock(&kvm->srcu, idx);
4091 
4092 out2:
4093         mutex_unlock(&kvm->slots_lock);
4094         return r;
4095 }
4096 
4097 static void seg_setup(int seg)
4098 {
4099         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4100         unsigned int ar;
4101 
4102         vmcs_write16(sf->selector, 0);
4103         vmcs_writel(sf->base, 0);
4104         vmcs_write32(sf->limit, 0xffff);
4105         ar = 0x93;
4106         if (seg == VCPU_SREG_CS)
4107                 ar |= 0x08; /* code segment */
4108 
4109         vmcs_write32(sf->ar_bytes, ar);
4110 }
4111 
4112 static int alloc_apic_access_page(struct kvm *kvm)
4113 {
4114         struct page *page;
4115         struct kvm_userspace_memory_region kvm_userspace_mem;
4116         int r = 0;
4117 
4118         mutex_lock(&kvm->slots_lock);
4119         if (kvm->arch.apic_access_page_done)
4120                 goto out;
4121         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4122         kvm_userspace_mem.flags = 0;
4123         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4124         kvm_userspace_mem.memory_size = PAGE_SIZE;
4125         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4126         if (r)
4127                 goto out;
4128 
4129         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4130         if (is_error_page(page)) {
4131                 r = -EFAULT;
4132                 goto out;
4133         }
4134 
4135         /*
4136          * Do not pin the page in memory, so that memory hot-unplug
4137          * is able to migrate it.
4138          */
4139         put_page(page);
4140         kvm->arch.apic_access_page_done = true;
4141 out:
4142         mutex_unlock(&kvm->slots_lock);
4143         return r;
4144 }
4145 
4146 static int alloc_identity_pagetable(struct kvm *kvm)
4147 {
4148         /* Called with kvm->slots_lock held. */
4149 
4150         struct kvm_userspace_memory_region kvm_userspace_mem;
4151         int r = 0;
4152 
4153         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4154 
4155         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4156         kvm_userspace_mem.flags = 0;
4157         kvm_userspace_mem.guest_phys_addr =
4158                 kvm->arch.ept_identity_map_addr;
4159         kvm_userspace_mem.memory_size = PAGE_SIZE;
4160         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4161 
4162         return r;
4163 }
4164 
4165 static void allocate_vpid(struct vcpu_vmx *vmx)
4166 {
4167         int vpid;
4168 
4169         vmx->vpid = 0;
4170         if (!enable_vpid)
4171                 return;
4172         spin_lock(&vmx_vpid_lock);
4173         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4174         if (vpid < VMX_NR_VPIDS) {
4175                 vmx->vpid = vpid;
4176                 __set_bit(vpid, vmx_vpid_bitmap);
4177         }
4178         spin_unlock(&vmx_vpid_lock);
4179 }
4180 
4181 static void free_vpid(struct vcpu_vmx *vmx)
4182 {
4183         if (!enable_vpid)
4184                 return;
4185         spin_lock(&vmx_vpid_lock);
4186         if (vmx->vpid != 0)
4187                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4188         spin_unlock(&vmx_vpid_lock);
4189 }
4190 
4191 #define MSR_TYPE_R      1
4192 #define MSR_TYPE_W      2
4193 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4194                                                 u32 msr, int type)
4195 {
4196         int f = sizeof(unsigned long);
4197 
4198         if (!cpu_has_vmx_msr_bitmap())
4199                 return;
4200 
4201         /*
4202          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4203          * have the write-low and read-high bitmap offsets the wrong way round.
4204          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4205          */
4206         if (msr <= 0x1fff) {
4207                 if (type & MSR_TYPE_R)
4208                         /* read-low */
4209                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4210 
4211                 if (type & MSR_TYPE_W)
4212                         /* write-low */
4213                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4214 
4215         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4216                 msr &= 0x1fff;
4217                 if (type & MSR_TYPE_R)
4218                         /* read-high */
4219                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4220 
4221                 if (type & MSR_TYPE_W)
4222                         /* write-high */
4223                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4224 
4225         }
4226 }
4227 
4228 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4229                                                 u32 msr, int type)
4230 {
4231         int f = sizeof(unsigned long);
4232 
4233         if (!cpu_has_vmx_msr_bitmap())
4234                 return;
4235 
4236         /*
4237          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4238          * have the write-low and read-high bitmap offsets the wrong way round.
4239          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4240          */
4241         if (msr <= 0x1fff) {
4242                 if (type & MSR_TYPE_R)
4243                         /* read-low */
4244                         __set_bit(msr, msr_bitmap + 0x000 / f);
4245 
4246                 if (type & MSR_TYPE_W)
4247                         /* write-low */
4248                         __set_bit(msr, msr_bitmap + 0x800 / f);
4249 
4250         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4251                 msr &= 0x1fff;
4252                 if (type & MSR_TYPE_R)
4253                         /* read-high */
4254                         __set_bit(msr, msr_bitmap + 0x400 / f);
4255 
4256                 if (type & MSR_TYPE_W)
4257                         /* write-high */
4258                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4259 
4260         }
4261 }
4262 
4263 /*
4264  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4265  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4266  */
4267 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4268                                                unsigned long *msr_bitmap_nested,
4269                                                u32 msr, int type)
4270 {
4271         int f = sizeof(unsigned long);
4272 
4273         if (!cpu_has_vmx_msr_bitmap()) {
4274                 WARN_ON(1);
4275                 return;
4276         }
4277 
4278         /*
4279          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4280          * have the write-low and read-high bitmap offsets the wrong way round.
4281          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4282          */
4283         if (msr <= 0x1fff) {
4284                 if (type & MSR_TYPE_R &&
4285                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4286                         /* read-low */
4287                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4288 
4289                 if (type & MSR_TYPE_W &&
4290                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4291                         /* write-low */
4292                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4293 
4294         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4295                 msr &= 0x1fff;
4296                 if (type & MSR_TYPE_R &&
4297                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4298                         /* read-high */
4299                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4300 
4301                 if (type & MSR_TYPE_W &&
4302                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4303                         /* write-high */
4304                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4305 
4306         }
4307 }
4308 
4309 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4310 {
4311         if (!longmode_only)
4312                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4313                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4314         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4315                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4316 }
4317 
4318 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4319 {
4320         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4321                         msr, MSR_TYPE_R);
4322         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4323                         msr, MSR_TYPE_R);
4324 }
4325 
4326 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4327 {
4328         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4329                         msr, MSR_TYPE_R);
4330         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4331                         msr, MSR_TYPE_R);
4332 }
4333 
4334 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4335 {
4336         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4337                         msr, MSR_TYPE_W);
4338         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4339                         msr, MSR_TYPE_W);
4340 }
4341 
4342 static int vmx_vm_has_apicv(struct kvm *kvm)
4343 {
4344         return enable_apicv && irqchip_in_kernel(kvm);
4345 }
4346 
4347 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4348 {
4349         struct vcpu_vmx *vmx = to_vmx(vcpu);
4350         int max_irr;
4351         void *vapic_page;
4352         u16 status;
4353 
4354         if (vmx->nested.pi_desc &&
4355             vmx->nested.pi_pending) {
4356                 vmx->nested.pi_pending = false;
4357                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4358                         return 0;
4359 
4360                 max_irr = find_last_bit(
4361                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4362 
4363                 if (max_irr == 256)
4364                         return 0;
4365 
4366                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4367                 if (!vapic_page) {
4368                         WARN_ON(1);
4369                         return -ENOMEM;
4370                 }
4371                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4372                 kunmap(vmx->nested.virtual_apic_page);
4373 
4374                 status = vmcs_read16(GUEST_INTR_STATUS);
4375                 if ((u8)max_irr > ((u8)status & 0xff)) {
4376                         status &= ~0xff;
4377                         status |= (u8)max_irr;
4378                         vmcs_write16(GUEST_INTR_STATUS, status);
4379                 }
4380         }
4381         return 0;
4382 }
4383 
4384 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4385 {
4386 #ifdef CONFIG_SMP
4387         if (vcpu->mode == IN_GUEST_MODE) {
4388                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4389                                 POSTED_INTR_VECTOR);
4390                 return true;
4391         }
4392 #endif
4393         return false;
4394 }
4395 
4396 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4397                                                 int vector)
4398 {
4399         struct vcpu_vmx *vmx = to_vmx(vcpu);
4400 
4401         if (is_guest_mode(vcpu) &&
4402             vector == vmx->nested.posted_intr_nv) {
4403                 /* the PIR and ON have been set by L1. */
4404                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4405                 /*
4406                  * If a posted intr is not recognized by hardware,
4407                  * we will accomplish it in the next vmentry.
4408                  */
4409                 vmx->nested.pi_pending = true;
4410                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4411                 return 0;
4412         }
4413         return -1;
4414 }
4415 /*
4416  * Send interrupt to vcpu via posted interrupt way.
4417  * 1. If target vcpu is running(non-root mode), send posted interrupt
4418  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4419  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4420  * interrupt from PIR in next vmentry.
4421  */
4422 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4423 {
4424         struct vcpu_vmx *vmx = to_vmx(vcpu);
4425         int r;
4426 
4427         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4428         if (!r)
4429                 return;
4430 
4431         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4432                 return;
4433 
4434         r = pi_test_and_set_on(&vmx->pi_desc);
4435         kvm_make_request(KVM_REQ_EVENT, vcpu);
4436         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4437                 kvm_vcpu_kick(vcpu);
4438 }
4439 
4440 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4441 {
4442         struct vcpu_vmx *vmx = to_vmx(vcpu);
4443 
4444         if (!pi_test_and_clear_on(&vmx->pi_desc))
4445                 return;
4446 
4447         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4448 }
4449 
4450 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4451 {
4452         return;
4453 }
4454 
4455 /*
4456  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4457  * will not change in the lifetime of the guest.
4458  * Note that host-state that does change is set elsewhere. E.g., host-state
4459  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4460  */
4461 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4462 {
4463         u32 low32, high32;
4464         unsigned long tmpl;
4465         struct desc_ptr dt;
4466         unsigned long cr4;
4467 
4468         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4469         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4470 
4471         /* Save the most likely value for this task's CR4 in the VMCS. */
4472         cr4 = cr4_read_shadow();
4473         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4474         vmx->host_state.vmcs_host_cr4 = cr4;
4475 
4476         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4477 #ifdef CONFIG_X86_64
4478         /*
4479          * Load null selectors, so we can avoid reloading them in
4480          * __vmx_load_host_state(), in case userspace uses the null selectors
4481          * too (the expected case).
4482          */
4483         vmcs_write16(HOST_DS_SELECTOR, 0);
4484         vmcs_write16(HOST_ES_SELECTOR, 0);
4485 #else
4486         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4487         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4488 #endif
4489         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4490         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4491 
4492         native_store_idt(&dt);
4493         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4494         vmx->host_idt_base = dt.address;
4495 
4496         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4497 
4498         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4499         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4500         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4501         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4502 
4503         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4504                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4505                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4506         }
4507 }
4508 
4509 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4510 {
4511         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4512         if (enable_ept)
4513                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4514         if (is_guest_mode(&vmx->vcpu))
4515                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4516                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4517         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4518 }
4519 
4520 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4521 {
4522         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4523 
4524         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4525                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4526         return pin_based_exec_ctrl;
4527 }
4528 
4529 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4530 {
4531         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4532 
4533         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4534                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4535 
4536         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4537                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4538 #ifdef CONFIG_X86_64
4539                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4540                                 CPU_BASED_CR8_LOAD_EXITING;
4541 #endif
4542         }
4543         if (!enable_ept)
4544                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4545                                 CPU_BASED_CR3_LOAD_EXITING  |
4546                                 CPU_BASED_INVLPG_EXITING;
4547         return exec_control;
4548 }
4549 
4550 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4551 {
4552         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4553         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4554                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4555         if (vmx->vpid == 0)
4556                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4557         if (!enable_ept) {
4558                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4559                 enable_unrestricted_guest = 0;
4560                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4561                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4562         }
4563         if (!enable_unrestricted_guest)
4564                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4565         if (!ple_gap)
4566                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4567         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4568                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4569                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4570         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4571         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4572            (handle_vmptrld).
4573            We can NOT enable shadow_vmcs here because we don't have yet
4574            a current VMCS12
4575         */
4576         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4577         /* PML is enabled/disabled in creating/destorying vcpu */
4578         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4579 
4580         return exec_control;
4581 }
4582 
4583 static void ept_set_mmio_spte_mask(void)
4584 {
4585         /*
4586          * EPT Misconfigurations can be generated if the value of bits 2:0
4587          * of an EPT paging-structure entry is 110b (write/execute).
4588          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4589          * spte.
4590          */
4591         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4592 }
4593 
4594 #define VMX_XSS_EXIT_BITMAP 0
4595 /*
4596  * Sets up the vmcs for emulated real mode.
4597  */
4598 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4599 {
4600 #ifdef CONFIG_X86_64
4601         unsigned long a;
4602 #endif
4603         int i;
4604 
4605         /* I/O */
4606         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4607         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4608 
4609         if (enable_shadow_vmcs) {
4610                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4611                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4612         }
4613         if (cpu_has_vmx_msr_bitmap())
4614                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4615 
4616         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4617 
4618         /* Control */
4619         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4620 
4621         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4622 
4623         if (cpu_has_secondary_exec_ctrls()) {
4624                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4625                                 vmx_secondary_exec_control(vmx));
4626         }
4627 
4628         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4629                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4630                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4631                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4632                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4633 
4634                 vmcs_write16(GUEST_INTR_STATUS, 0);
4635 
4636                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4637                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4638         }
4639 
4640         if (ple_gap) {
4641                 vmcs_write32(PLE_GAP, ple_gap);
4642                 vmx->ple_window = ple_window;
4643                 vmx->ple_window_dirty = true;
4644         }
4645 
4646         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4647         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4648         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4649 
4650         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4651         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4652         vmx_set_constant_host_state(vmx);
4653 #ifdef CONFIG_X86_64
4654         rdmsrl(MSR_FS_BASE, a);
4655         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4656         rdmsrl(MSR_GS_BASE, a);
4657         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4658 #else
4659         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4660         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4661 #endif
4662 
4663         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4664         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4665         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4666         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4667         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4668 
4669         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4670                 u32 msr_low, msr_high;
4671                 u64 host_pat;
4672                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4673                 host_pat = msr_low | ((u64) msr_high << 32);
4674                 /* Write the default value follow host pat */
4675                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4676                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4677                 vmx->vcpu.arch.pat = host_pat;
4678         }
4679 
4680         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4681                 u32 index = vmx_msr_index[i];
4682                 u32 data_low, data_high;
4683                 int j = vmx->nmsrs;
4684 
4685                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4686                         continue;
4687                 if (wrmsr_safe(index, data_low, data_high) < 0)
4688                         continue;
4689                 vmx->guest_msrs[j].index = i;
4690                 vmx->guest_msrs[j].data = 0;
4691                 vmx->guest_msrs[j].mask = -1ull;
4692                 ++vmx->nmsrs;
4693         }
4694 
4695 
4696         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4697 
4698         /* 22.2.1, 20.8.1 */
4699         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4700 
4701         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4702         set_cr4_guest_host_mask(vmx);
4703 
4704         if (vmx_xsaves_supported())
4705                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4706 
4707         return 0;
4708 }
4709 
4710 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4711 {
4712         struct vcpu_vmx *vmx = to_vmx(vcpu);
4713         struct msr_data apic_base_msr;
4714 
4715         vmx->rmode.vm86_active = 0;
4716 
4717         vmx->soft_vnmi_blocked = 0;
4718 
4719         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4720         kvm_set_cr8(&vmx->vcpu, 0);
4721         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4722         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4723                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4724         apic_base_msr.host_initiated = true;
4725         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4726 
4727         vmx_segment_cache_clear(vmx);
4728 
4729         seg_setup(VCPU_SREG_CS);
4730         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4731         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4732 
4733         seg_setup(VCPU_SREG_DS);
4734         seg_setup(VCPU_SREG_ES);
4735         seg_setup(VCPU_SREG_FS);
4736         seg_setup(VCPU_SREG_GS);
4737         seg_setup(VCPU_SREG_SS);
4738 
4739         vmcs_write16(GUEST_TR_SELECTOR, 0);
4740         vmcs_writel(GUEST_TR_BASE, 0);
4741         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4742         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4743 
4744         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4745         vmcs_writel(GUEST_LDTR_BASE, 0);
4746         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4747         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4748 
4749         vmcs_write32(GUEST_SYSENTER_CS, 0);
4750         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4751         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4752 
4753         vmcs_writel(GUEST_RFLAGS, 0x02);
4754         kvm_rip_write(vcpu, 0xfff0);
4755 
4756         vmcs_writel(GUEST_GDTR_BASE, 0);
4757         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4758 
4759         vmcs_writel(GUEST_IDTR_BASE, 0);
4760         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4761 
4762         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4763         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4764         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4765 
4766         /* Special registers */
4767         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4768 
4769         setup_msrs(vmx);
4770 
4771         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4772 
4773         if (cpu_has_vmx_tpr_shadow()) {
4774                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4775                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4776                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4777                                      __pa(vmx->vcpu.arch.apic->regs));
4778                 vmcs_write32(TPR_THRESHOLD, 0);
4779         }
4780 
4781         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4782 
4783         if (vmx_vm_has_apicv(vcpu->kvm))
4784                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4785 
4786         if (vmx->vpid != 0)
4787                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4788 
4789         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4790         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4791         vmx_set_cr4(&vmx->vcpu, 0);
4792         vmx_set_efer(&vmx->vcpu, 0);
4793         vmx_fpu_activate(&vmx->vcpu);
4794         update_exception_bitmap(&vmx->vcpu);
4795 
4796         vpid_sync_context(vmx);
4797 }
4798 
4799 /*
4800  * In nested virtualization, check if L1 asked to exit on external interrupts.
4801  * For most existing hypervisors, this will always return true.
4802  */
4803 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4804 {
4805         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4806                 PIN_BASED_EXT_INTR_MASK;
4807 }
4808 
4809 /*
4810  * In nested virtualization, check if L1 has set
4811  * VM_EXIT_ACK_INTR_ON_EXIT
4812  */
4813 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4814 {
4815         return get_vmcs12(vcpu)->vm_exit_controls &
4816                 VM_EXIT_ACK_INTR_ON_EXIT;
4817 }
4818 
4819 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4820 {
4821         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4822                 PIN_BASED_NMI_EXITING;
4823 }
4824 
4825 static void enable_irq_window(struct kvm_vcpu *vcpu)
4826 {
4827         u32 cpu_based_vm_exec_control;
4828 
4829         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4830         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4831         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4832 }
4833 
4834 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4835 {
4836         u32 cpu_based_vm_exec_control;
4837 
4838         if (!cpu_has_virtual_nmis() ||
4839             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4840                 enable_irq_window(vcpu);
4841                 return;
4842         }
4843 
4844         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4845         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4846         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4847 }
4848 
4849 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4850 {
4851         struct vcpu_vmx *vmx = to_vmx(vcpu);
4852         uint32_t intr;
4853         int irq = vcpu->arch.interrupt.nr;
4854 
4855         trace_kvm_inj_virq(irq);
4856 
4857         ++vcpu->stat.irq_injections;
4858         if (vmx->rmode.vm86_active) {
4859                 int inc_eip = 0;
4860                 if (vcpu->arch.interrupt.soft)
4861                         inc_eip = vcpu->arch.event_exit_inst_len;
4862                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4863                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4864                 return;
4865         }
4866         intr = irq | INTR_INFO_VALID_MASK;
4867         if (vcpu->arch.interrupt.soft) {
4868                 intr |= INTR_TYPE_SOFT_INTR;
4869                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4870                              vmx->vcpu.arch.event_exit_inst_len);
4871         } else
4872                 intr |= INTR_TYPE_EXT_INTR;
4873         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4874 }
4875 
4876 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4877 {
4878         struct vcpu_vmx *vmx = to_vmx(vcpu);
4879 
4880         if (is_guest_mode(vcpu))
4881                 return;
4882 
4883         if (!cpu_has_virtual_nmis()) {
4884                 /*
4885                  * Tracking the NMI-blocked state in software is built upon
4886                  * finding the next open IRQ window. This, in turn, depends on
4887                  * well-behaving guests: They have to keep IRQs disabled at
4888                  * least as long as the NMI handler runs. Otherwise we may
4889                  * cause NMI nesting, maybe breaking the guest. But as this is
4890                  * highly unlikely, we can live with the residual risk.
4891                  */
4892                 vmx->soft_vnmi_blocked = 1;
4893                 vmx->vnmi_blocked_time = 0;
4894         }
4895 
4896         ++vcpu->stat.nmi_injections;
4897         vmx->nmi_known_unmasked = false;
4898         if (vmx->rmode.vm86_active) {
4899                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4900                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4901                 return;
4902         }
4903         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4904                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4905 }
4906 
4907 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4908 {
4909         if (!cpu_has_virtual_nmis())
4910                 return to_vmx(vcpu)->soft_vnmi_blocked;
4911         if (to_vmx(vcpu)->nmi_known_unmasked)
4912                 return false;
4913         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4914 }
4915 
4916 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4917 {
4918         struct vcpu_vmx *vmx = to_vmx(vcpu);
4919 
4920         if (!cpu_has_virtual_nmis()) {
4921                 if (vmx->soft_vnmi_blocked != masked) {
4922                         vmx->soft_vnmi_blocked = masked;
4923                         vmx->vnmi_blocked_time = 0;
4924                 }
4925         } else {
4926                 vmx->nmi_known_unmasked = !masked;
4927                 if (masked)
4928                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4929                                       GUEST_INTR_STATE_NMI);
4930                 else
4931                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4932                                         GUEST_INTR_STATE_NMI);
4933         }
4934 }
4935 
4936 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4937 {
4938         if (to_vmx(vcpu)->nested.nested_run_pending)
4939                 return 0;
4940 
4941         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4942                 return 0;
4943 
4944         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4945                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4946                    | GUEST_INTR_STATE_NMI));
4947 }
4948 
4949 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4950 {
4951         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4952                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4953                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4954                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4955 }
4956 
4957 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4958 {
4959         int ret;
4960         struct kvm_userspace_memory_region tss_mem = {
4961                 .slot = TSS_PRIVATE_MEMSLOT,
4962                 .guest_phys_addr = addr,
4963                 .memory_size = PAGE_SIZE * 3,
4964                 .flags = 0,
4965         };
4966 
4967         ret = kvm_set_memory_region(kvm, &tss_mem);
4968         if (ret)
4969                 return ret;
4970         kvm->arch.tss_addr = addr;
4971         return init_rmode_tss(kvm);
4972 }
4973 
4974 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4975 {
4976         switch (vec) {
4977         case BP_VECTOR:
4978                 /*
4979                  * Update instruction length as we may reinject the exception
4980                  * from user space while in guest debugging mode.
4981                  */
4982                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4983                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4984                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4985                         return false;
4986                 /* fall through */
4987         case DB_VECTOR:
4988                 if (vcpu->guest_debug &
4989                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4990                         return false;
4991                 /* fall through */
4992         case DE_VECTOR:
4993         case OF_VECTOR:
4994         case BR_VECTOR:
4995         case UD_VECTOR:
4996         case DF_VECTOR:
4997         case SS_VECTOR:
4998         case GP_VECTOR:
4999         case MF_VECTOR:
5000                 return true;
5001         break;
5002         }
5003         return false;
5004 }
5005 
5006 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5007                                   int vec, u32 err_code)
5008 {
5009         /*
5010          * Instruction with address size override prefix opcode 0x67
5011          * Cause the #SS fault with 0 error code in VM86 mode.
5012          */
5013         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5014                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5015                         if (vcpu->arch.halt_request) {
5016                                 vcpu->arch.halt_request = 0;
5017                                 return kvm_emulate_halt(vcpu);
5018                         }
5019                         return 1;
5020                 }
5021                 return 0;
5022         }
5023 
5024         /*
5025          * Forward all other exceptions that are valid in real mode.
5026          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5027          *        the required debugging infrastructure rework.
5028          */
5029         kvm_queue_exception(vcpu, vec);
5030         return 1;
5031 }
5032 
5033 /*
5034  * Trigger machine check on the host. We assume all the MSRs are already set up
5035  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5036  * We pass a fake environment to the machine check handler because we want
5037  * the guest to be always treated like user space, no matter what context
5038  * it used internally.
5039  */
5040 static void kvm_machine_check(void)
5041 {
5042 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5043         struct pt_regs regs = {
5044                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5045                 .flags = X86_EFLAGS_IF,
5046         };
5047 
5048         do_machine_check(&regs, 0);
5049 #endif
5050 }
5051 
5052 static int handle_machine_check(struct kvm_vcpu *vcpu)
5053 {
5054         /* already handled by vcpu_run */
5055         return 1;
5056 }
5057 
5058 static int handle_exception(struct kvm_vcpu *vcpu)
5059 {
5060         struct vcpu_vmx *vmx = to_vmx(vcpu);
5061         struct kvm_run *kvm_run = vcpu->run;
5062         u32 intr_info, ex_no, error_code;
5063         unsigned long cr2, rip, dr6;
5064         u32 vect_info;
5065         enum emulation_result er;
5066 
5067         vect_info = vmx->idt_vectoring_info;
5068         intr_info = vmx->exit_intr_info;
5069 
5070         if (is_machine_check(intr_info))
5071                 return handle_machine_check(vcpu);
5072 
5073         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5074                 return 1;  /* already handled by vmx_vcpu_run() */
5075 
5076         if (is_no_device(intr_info)) {
5077                 vmx_fpu_activate(vcpu);
5078                 return 1;
5079         }
5080 
5081         if (is_invalid_opcode(intr_info)) {
5082                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5083                 if (er != EMULATE_DONE)
5084                         kvm_queue_exception(vcpu, UD_VECTOR);
5085                 return 1;
5086         }
5087 
5088         error_code = 0;
5089         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5090                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5091 
5092         /*
5093          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5094          * MMIO, it is better to report an internal error.
5095          * See the comments in vmx_handle_exit.
5096          */
5097         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5098             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5099                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5100                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5101                 vcpu->run->internal.ndata = 2;
5102                 vcpu->run->internal.data[0] = vect_info;
5103                 vcpu->run->internal.data[1] = intr_info;
5104                 return 0;
5105         }
5106 
5107         if (is_page_fault(intr_info)) {
5108                 /* EPT won't cause page fault directly */
5109                 BUG_ON(enable_ept);
5110                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5111                 trace_kvm_page_fault(cr2, error_code);
5112 
5113                 if (kvm_event_needs_reinjection(vcpu))
5114                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5115                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5116         }
5117 
5118         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5119 
5120         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5121                 return handle_rmode_exception(vcpu, ex_no, error_code);
5122 
5123         switch (ex_no) {
5124         case DB_VECTOR:
5125                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5126                 if (!(vcpu->guest_debug &
5127                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5128                         vcpu->arch.dr6 &= ~15;
5129                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5130                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5131                                 skip_emulated_instruction(vcpu);
5132 
5133                         kvm_queue_exception(vcpu, DB_VECTOR);
5134                         return 1;
5135                 }
5136                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5137                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5138                 /* fall through */
5139         case BP_VECTOR:
5140                 /*
5141                  * Update instruction length as we may reinject #BP from
5142                  * user space while in guest debugging mode. Reading it for
5143                  * #DB as well causes no harm, it is not used in that case.
5144                  */
5145                 vmx->vcpu.arch.event_exit_inst_len =
5146                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5147                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5148                 rip = kvm_rip_read(vcpu);
5149                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5150                 kvm_run->debug.arch.exception = ex_no;
5151                 break;
5152         default:
5153                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5154                 kvm_run->ex.exception = ex_no;
5155                 kvm_run->ex.error_code = error_code;
5156                 break;
5157         }
5158         return 0;
5159 }
5160 
5161 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5162 {
5163         ++vcpu->stat.irq_exits;
5164         return 1;
5165 }
5166 
5167 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5168 {
5169         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5170         return 0;
5171 }
5172 
5173 static int handle_io(struct kvm_vcpu *vcpu)
5174 {
5175         unsigned long exit_qualification;
5176         int size, in, string;
5177         unsigned port;
5178 
5179         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5180         string = (exit_qualification & 16) != 0;
5181         in = (exit_qualification & 8) != 0;
5182 
5183         ++vcpu->stat.io_exits;
5184 
5185         if (string || in)
5186                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5187 
5188         port = exit_qualification >> 16;
5189         size = (exit_qualification & 7) + 1;
5190         skip_emulated_instruction(vcpu);
5191 
5192         return kvm_fast_pio_out(vcpu, size, port);
5193 }
5194 
5195 static void
5196 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5197 {
5198         /*
5199          * Patch in the VMCALL instruction:
5200          */
5201         hypercall[0] = 0x0f;
5202         hypercall[1] = 0x01;
5203         hypercall[2] = 0xc1;
5204 }
5205 
5206 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5207 {
5208         unsigned long always_on = VMXON_CR0_ALWAYSON;
5209         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5210 
5211         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5212                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5213             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5214                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5215         return (val & always_on) == always_on;
5216 }
5217 
5218 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5219 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5220 {
5221         if (is_guest_mode(vcpu)) {
5222                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5223                 unsigned long orig_val = val;
5224 
5225                 /*
5226                  * We get here when L2 changed cr0 in a way that did not change
5227                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5228                  * but did change L0 shadowed bits. So we first calculate the
5229                  * effective cr0 value that L1 would like to write into the
5230                  * hardware. It consists of the L2-owned bits from the new
5231                  * value combined with the L1-owned bits from L1's guest_cr0.
5232                  */
5233                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5234                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5235 
5236                 if (!nested_cr0_valid(vcpu, val))
5237                         return 1;
5238 
5239                 if (kvm_set_cr0(vcpu, val))
5240                         return 1;
5241                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5242                 return 0;
5243         } else {
5244                 if (to_vmx(vcpu)->nested.vmxon &&
5245                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5246                         return 1;
5247                 return kvm_set_cr0(vcpu, val);
5248         }
5249 }
5250 
5251 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5252 {
5253         if (is_guest_mode(vcpu)) {
5254                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5255                 unsigned long orig_val = val;
5256 
5257                 /* analogously to handle_set_cr0 */
5258                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5259                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5260                 if (kvm_set_cr4(vcpu, val))
5261                         return 1;
5262                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5263                 return 0;
5264         } else
5265                 return kvm_set_cr4(vcpu, val);
5266 }
5267 
5268 /* called to set cr0 as approriate for clts instruction exit. */
5269 static void handle_clts(struct kvm_vcpu *vcpu)
5270 {
5271         if (is_guest_mode(vcpu)) {
5272                 /*
5273                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5274                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5275                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5276                  */
5277                 vmcs_writel(CR0_READ_SHADOW,
5278                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5279                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5280         } else
5281                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5282 }
5283 
5284 static int handle_cr(struct kvm_vcpu *vcpu)
5285 {
5286         unsigned long exit_qualification, val;
5287         int cr;
5288         int reg;
5289         int err;
5290 
5291         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5292         cr = exit_qualification & 15;
5293         reg = (exit_qualification >> 8) & 15;
5294         switch ((exit_qualification >> 4) & 3) {
5295         case 0: /* mov to cr */
5296                 val = kvm_register_readl(vcpu, reg);
5297                 trace_kvm_cr_write(cr, val);
5298                 switch (cr) {
5299                 case 0:
5300                         err = handle_set_cr0(vcpu, val);
5301                         kvm_complete_insn_gp(vcpu, err);
5302                         return 1;
5303                 case 3:
5304                         err = kvm_set_cr3(vcpu, val);
5305                         kvm_complete_insn_gp(vcpu, err);
5306                         return 1;
5307                 case 4:
5308                         err = handle_set_cr4(vcpu, val);
5309                         kvm_complete_insn_gp(vcpu, err);
5310                         return 1;
5311                 case 8: {
5312                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5313                                 u8 cr8 = (u8)val;
5314                                 err = kvm_set_cr8(vcpu, cr8);
5315                                 kvm_complete_insn_gp(vcpu, err);
5316                                 if (irqchip_in_kernel(vcpu->kvm))
5317                                         return 1;
5318                                 if (cr8_prev <= cr8)
5319                                         return 1;
5320                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5321                                 return 0;
5322                         }
5323                 }
5324                 break;
5325         case 2: /* clts */
5326                 handle_clts(vcpu);
5327                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5328                 skip_emulated_instruction(vcpu);
5329                 vmx_fpu_activate(vcpu);
5330                 return 1;
5331         case 1: /*mov from cr*/
5332                 switch (cr) {
5333                 case 3:
5334                         val = kvm_read_cr3(vcpu);
5335                         kvm_register_write(vcpu, reg, val);
5336                         trace_kvm_cr_read(cr, val);
5337                         skip_emulated_instruction(vcpu);
5338                         return 1;
5339                 case 8:
5340                         val = kvm_get_cr8(vcpu);
5341                         kvm_register_write(vcpu, reg, val);
5342                         trace_kvm_cr_read(cr, val);
5343                         skip_emulated_instruction(vcpu);
5344                         return 1;
5345                 }
5346                 break;
5347         case 3: /* lmsw */
5348                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5349                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5350                 kvm_lmsw(vcpu, val);
5351 
5352                 skip_emulated_instruction(vcpu);
5353                 return 1;
5354         default:
5355                 break;
5356         }
5357         vcpu->run->exit_reason = 0;
5358         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5359                (int)(exit_qualification >> 4) & 3, cr);
5360         return 0;
5361 }
5362 
5363 static int handle_dr(struct kvm_vcpu *vcpu)
5364 {
5365         unsigned long exit_qualification;
5366         int dr, dr7, reg;
5367 
5368         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5369         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5370 
5371         /* First, if DR does not exist, trigger UD */
5372         if (!kvm_require_dr(vcpu, dr))
5373                 return 1;
5374 
5375         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5376         if (!kvm_require_cpl(vcpu, 0))
5377                 return 1;
5378         dr7 = vmcs_readl(GUEST_DR7);
5379         if (dr7 & DR7_GD) {
5380                 /*
5381                  * As the vm-exit takes precedence over the debug trap, we
5382                  * need to emulate the latter, either for the host or the
5383                  * guest debugging itself.
5384                  */
5385                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5386                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5387                         vcpu->run->debug.arch.dr7 = dr7;
5388                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5389                         vcpu->run->debug.arch.exception = DB_VECTOR;
5390                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5391                         return 0;
5392                 } else {
5393                         vcpu->arch.dr6 &= ~15;
5394                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5395                         kvm_queue_exception(vcpu, DB_VECTOR);
5396                         return 1;
5397                 }
5398         }
5399 
5400         if (vcpu->guest_debug == 0) {
5401                 u32 cpu_based_vm_exec_control;
5402 
5403                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5404                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5405                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5406 
5407                 /*
5408                  * No more DR vmexits; force a reload of the debug registers
5409                  * and reenter on this instruction.  The next vmexit will
5410                  * retrieve the full state of the debug registers.
5411                  */
5412                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5413                 return 1;
5414         }
5415 
5416         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5417         if (exit_qualification & TYPE_MOV_FROM_DR) {
5418                 unsigned long val;
5419 
5420                 if (kvm_get_dr(vcpu, dr, &val))
5421                         return 1;
5422                 kvm_register_write(vcpu, reg, val);
5423         } else
5424                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5425                         return 1;
5426 
5427         skip_emulated_instruction(vcpu);
5428         return 1;
5429 }
5430 
5431 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5432 {
5433         return vcpu->arch.dr6;
5434 }
5435 
5436 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5437 {
5438 }
5439 
5440 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5441 {
5442         u32 cpu_based_vm_exec_control;
5443 
5444         get_debugreg(vcpu->arch.db[0], 0);
5445         get_debugreg(vcpu->arch.db[1], 1);
5446         get_debugreg(vcpu->arch.db[2], 2);
5447         get_debugreg(vcpu->arch.db[3], 3);
5448         get_debugreg(vcpu->arch.dr6, 6);
5449         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5450 
5451         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5452 
5453         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5454         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5455         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5456 }
5457 
5458 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5459 {
5460         vmcs_writel(GUEST_DR7, val);
5461 }
5462 
5463 static int handle_cpuid(struct kvm_vcpu *vcpu)
5464 {
5465         kvm_emulate_cpuid(vcpu);
5466         return 1;
5467 }
5468 
5469 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5470 {
5471         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5472         u64 data;
5473 
5474         if (vmx_get_msr(vcpu, ecx, &data)) {
5475                 trace_kvm_msr_read_ex(ecx);
5476                 kvm_inject_gp(vcpu, 0);
5477                 return 1;
5478         }
5479 
5480         trace_kvm_msr_read(ecx, data);
5481 
5482         /* FIXME: handling of bits 32:63 of rax, rdx */
5483         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5484         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5485         skip_emulated_instruction(vcpu);
5486         return 1;
5487 }
5488 
5489 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5490 {
5491         struct msr_data msr;
5492         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5493         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5494                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5495 
5496         msr.data = data;
5497         msr.index = ecx;
5498         msr.host_initiated = false;
5499         if (kvm_set_msr(vcpu, &msr) != 0) {
5500                 trace_kvm_msr_write_ex(ecx, data);
5501                 kvm_inject_gp(vcpu, 0);
5502                 return 1;
5503         }
5504 
5505         trace_kvm_msr_write(ecx, data);
5506         skip_emulated_instruction(vcpu);
5507         return 1;
5508 }
5509 
5510 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5511 {
5512         kvm_make_request(KVM_REQ_EVENT, vcpu);
5513         return 1;
5514 }
5515 
5516 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5517 {
5518         u32 cpu_based_vm_exec_control;
5519 
5520         /* clear pending irq */
5521         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5522         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5523         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5524 
5525         kvm_make_request(KVM_REQ_EVENT, vcpu);
5526 
5527         ++vcpu->stat.irq_window_exits;
5528 
5529         /*
5530          * If the user space waits to inject interrupts, exit as soon as
5531          * possible
5532          */
5533         if (!irqchip_in_kernel(vcpu->kvm) &&
5534             vcpu->run->request_interrupt_window &&
5535             !kvm_cpu_has_interrupt(vcpu)) {
5536                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5537                 return 0;
5538         }
5539         return 1;
5540 }
5541 
5542 static int handle_halt(struct kvm_vcpu *vcpu)
5543 {
5544         skip_emulated_instruction(vcpu);
5545         return kvm_emulate_halt(vcpu);
5546 }
5547 
5548 static int handle_vmcall(struct kvm_vcpu *vcpu)
5549 {
5550         skip_emulated_instruction(vcpu);
5551         kvm_emulate_hypercall(vcpu);
5552         return 1;
5553 }
5554 
5555 static int handle_invd(struct kvm_vcpu *vcpu)
5556 {
5557         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5558 }
5559 
5560 static int handle_invlpg(struct kvm_vcpu *vcpu)
5561 {
5562         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5563 
5564         kvm_mmu_invlpg(vcpu, exit_qualification);
5565         skip_emulated_instruction(vcpu);
5566         return 1;
5567 }
5568 
5569 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5570 {
5571         int err;
5572 
5573         err = kvm_rdpmc(vcpu);
5574         kvm_complete_insn_gp(vcpu, err);
5575 
5576         return 1;
5577 }
5578 
5579 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5580 {
5581         skip_emulated_instruction(vcpu);
5582         kvm_emulate_wbinvd(vcpu);
5583         return 1;
5584 }
5585 
5586 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5587 {
5588         u64 new_bv = kvm_read_edx_eax(vcpu);
5589         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5590 
5591         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5592                 skip_emulated_instruction(vcpu);
5593         return 1;
5594 }
5595 
5596 static int handle_xsaves(struct kvm_vcpu *vcpu)
5597 {
5598         skip_emulated_instruction(vcpu);
5599         WARN(1, "this should never happen\n");
5600         return 1;
5601 }
5602 
5603 static int handle_xrstors(struct kvm_vcpu *vcpu)
5604 {
5605         skip_emulated_instruction(vcpu);
5606         WARN(1, "this should never happen\n");
5607         return 1;
5608 }
5609 
5610 static int handle_apic_access(struct kvm_vcpu *vcpu)
5611 {
5612         if (likely(fasteoi)) {
5613                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5614                 int access_type, offset;
5615 
5616                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5617                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5618                 /*
5619                  * Sane guest uses MOV to write EOI, with written value
5620                  * not cared. So make a short-circuit here by avoiding
5621                  * heavy instruction emulation.
5622                  */
5623                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5624                     (offset == APIC_EOI)) {
5625                         kvm_lapic_set_eoi(vcpu);
5626                         skip_emulated_instruction(vcpu);
5627                         return 1;
5628                 }
5629         }
5630         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5631 }
5632 
5633 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5634 {
5635         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5636         int vector = exit_qualification & 0xff;
5637 
5638         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5639         kvm_apic_set_eoi_accelerated(vcpu, vector);
5640         return 1;
5641 }
5642 
5643 static int handle_apic_write(struct kvm_vcpu *vcpu)
5644 {
5645         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5646         u32 offset = exit_qualification & 0xfff;
5647 
5648         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5649         kvm_apic_write_nodecode(vcpu, offset);
5650         return 1;
5651 }
5652 
5653 static int handle_task_switch(struct kvm_vcpu *vcpu)
5654 {
5655         struct vcpu_vmx *vmx = to_vmx(vcpu);
5656         unsigned long exit_qualification;
5657         bool has_error_code = false;
5658         u32 error_code = 0;
5659         u16 tss_selector;
5660         int reason, type, idt_v, idt_index;
5661 
5662         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5663         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5664         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5665 
5666         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5667 
5668         reason = (u32)exit_qualification >> 30;
5669         if (reason == TASK_SWITCH_GATE && idt_v) {
5670                 switch (type) {
5671                 case INTR_TYPE_NMI_INTR:
5672                         vcpu->arch.nmi_injected = false;
5673                         vmx_set_nmi_mask(vcpu, true);
5674                         break;
5675                 case INTR_TYPE_EXT_INTR:
5676                 case INTR_TYPE_SOFT_INTR:
5677                         kvm_clear_interrupt_queue(vcpu);
5678                         break;
5679                 case INTR_TYPE_HARD_EXCEPTION:
5680                         if (vmx->idt_vectoring_info &
5681                             VECTORING_INFO_DELIVER_CODE_MASK) {
5682                                 has_error_code = true;
5683                                 error_code =
5684                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5685                         }
5686                         /* fall through */
5687                 case INTR_TYPE_SOFT_EXCEPTION:
5688                         kvm_clear_exception_queue(vcpu);
5689                         break;
5690                 default:
5691                         break;
5692                 }
5693         }
5694         tss_selector = exit_qualification;
5695 
5696         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5697                        type != INTR_TYPE_EXT_INTR &&
5698                        type != INTR_TYPE_NMI_INTR))
5699                 skip_emulated_instruction(vcpu);
5700 
5701         if (kvm_task_switch(vcpu, tss_selector,
5702                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5703                             has_error_code, error_code) == EMULATE_FAIL) {
5704                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5705                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5706                 vcpu->run->internal.ndata = 0;
5707                 return 0;
5708         }
5709 
5710         /* clear all local breakpoint enable flags */
5711         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5712 
5713         /*
5714          * TODO: What about debug traps on tss switch?
5715          *       Are we supposed to inject them and update dr6?
5716          */
5717 
5718         return 1;
5719 }
5720 
5721 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5722 {
5723         unsigned long exit_qualification;
5724         gpa_t gpa;
5725         u32 error_code;
5726         int gla_validity;
5727 
5728         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5729 
5730         gla_validity = (exit_qualification >> 7) & 0x3;
5731         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5732                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5733                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5734                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5735                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5736                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5737                         (long unsigned int)exit_qualification);
5738                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5739                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5740                 return 0;
5741         }
5742 
5743         /*
5744          * EPT violation happened while executing iret from NMI,
5745          * "blocked by NMI" bit has to be set before next VM entry.
5746          * There are errata that may cause this bit to not be set:
5747          * AAK134, BY25.
5748          */
5749         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5750                         cpu_has_virtual_nmis() &&
5751                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5752                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5753 
5754         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5755         trace_kvm_page_fault(gpa, exit_qualification);
5756 
5757         /* It is a write fault? */
5758         error_code = exit_qualification & PFERR_WRITE_MASK;
5759         /* It is a fetch fault? */
5760         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5761         /* ept page table is present? */
5762         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5763 
5764         vcpu->arch.exit_qualification = exit_qualification;
5765 
5766         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5767 }
5768 
5769 static u64 ept_rsvd_mask(u64 spte, int level)
5770 {
5771         int i;
5772         u64 mask = 0;
5773 
5774         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5775                 mask |= (1ULL << i);
5776 
5777         if (level == 4)
5778                 /* bits 7:3 reserved */
5779                 mask |= 0xf8;
5780         else if (spte & (1ULL << 7))
5781                 /*
5782                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5783                  * level == 1 if the hypervisor is using the ignored bit 7.
5784                  */
5785                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5786         else if (level > 1)
5787                 /* bits 6:3 reserved */
5788                 mask |= 0x78;
5789 
5790         return mask;
5791 }
5792 
5793 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5794                                        int level)
5795 {
5796         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5797 
5798         /* 010b (write-only) */
5799         WARN_ON((spte & 0x7) == 0x2);
5800 
5801         /* 110b (write/execute) */
5802         WARN_ON((spte & 0x7) == 0x6);
5803 
5804         /* 100b (execute-only) and value not supported by logical processor */
5805         if (!cpu_has_vmx_ept_execute_only())
5806                 WARN_ON((spte & 0x7) == 0x4);
5807 
5808         /* not 000b */
5809         if ((spte & 0x7)) {
5810                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5811 
5812                 if (rsvd_bits != 0) {
5813                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5814                                          __func__, rsvd_bits);
5815                         WARN_ON(1);
5816                 }
5817 
5818                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5819                 if ((rsvd_bits & 0x38) == 0) {
5820                         u64 ept_mem_type = (spte & 0x38) >> 3;
5821 
5822                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5823                             ept_mem_type == 7) {
5824                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5825                                                 __func__, ept_mem_type);
5826                                 WARN_ON(1);
5827                         }
5828                 }
5829         }
5830 }
5831 
5832 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5833 {
5834         u64 sptes[4];
5835         int nr_sptes, i, ret;
5836         gpa_t gpa;
5837 
5838         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5839         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5840                 skip_emulated_instruction(vcpu);
5841                 return 1;
5842         }
5843 
5844         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5845         if (likely(ret == RET_MMIO_PF_EMULATE))
5846                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5847                                               EMULATE_DONE;
5848 
5849         if (unlikely(ret == RET_MMIO_PF_INVALID))
5850                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5851 
5852         if (unlikely(ret == RET_MMIO_PF_RETRY))
5853                 return 1;
5854 
5855         /* It is the real ept misconfig */
5856         printk(KERN_ERR "EPT: Misconfiguration.\n");
5857         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5858 
5859         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5860 
5861         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5862                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5863 
5864         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5865         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5866 
5867         return 0;
5868 }
5869 
5870 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5871 {
5872         u32 cpu_based_vm_exec_control;
5873 
5874         /* clear pending NMI */
5875         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5876         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5877         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5878         ++vcpu->stat.nmi_window_exits;
5879         kvm_make_request(KVM_REQ_EVENT, vcpu);
5880 
5881         return 1;
5882 }
5883 
5884 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5885 {
5886         struct vcpu_vmx *vmx = to_vmx(vcpu);
5887         enum emulation_result err = EMULATE_DONE;
5888         int ret = 1;
5889         u32 cpu_exec_ctrl;
5890         bool intr_window_requested;
5891         unsigned count = 130;
5892 
5893         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5894         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5895 
5896         while (vmx->emulation_required && count-- != 0) {
5897                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5898                         return handle_interrupt_window(&vmx->vcpu);
5899 
5900                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5901                         return 1;
5902 
5903                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5904 
5905                 if (err == EMULATE_USER_EXIT) {
5906                         ++vcpu->stat.mmio_exits;
5907                         ret = 0;
5908                         goto out;
5909                 }
5910 
5911                 if (err != EMULATE_DONE) {
5912                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5913                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5914                         vcpu->run->internal.ndata = 0;
5915                         return 0;
5916                 }
5917 
5918                 if (vcpu->arch.halt_request) {
5919                         vcpu->arch.halt_request = 0;
5920                         ret = kvm_emulate_halt(vcpu);
5921                         goto out;
5922                 }
5923 
5924                 if (signal_pending(current))
5925                         goto out;
5926                 if (need_resched())
5927                         schedule();
5928         }
5929 
5930 out:
5931         return ret;
5932 }
5933 
5934 static int __grow_ple_window(int val)
5935 {
5936         if (ple_window_grow < 1)
5937                 return ple_window;
5938 
5939         val = min(val, ple_window_actual_max);
5940 
5941         if (ple_window_grow < ple_window)
5942                 val *= ple_window_grow;
5943         else
5944                 val += ple_window_grow;
5945 
5946         return val;
5947 }
5948 
5949 static int __shrink_ple_window(int val, int modifier, int minimum)
5950 {
5951         if (modifier < 1)
5952                 return ple_window;
5953 
5954         if (modifier < ple_window)
5955                 val /= modifier;
5956         else
5957                 val -= modifier;
5958 
5959         return max(val, minimum);
5960 }
5961 
5962 static void grow_ple_window(struct kvm_vcpu *vcpu)
5963 {
5964         struct vcpu_vmx *vmx = to_vmx(vcpu);
5965         int old = vmx->ple_window;
5966 
5967         vmx->ple_window = __grow_ple_window(old);
5968 
5969         if (vmx->ple_window != old)
5970                 vmx->ple_window_dirty = true;
5971 
5972         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5973 }
5974 
5975 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5976 {
5977         struct vcpu_vmx *vmx = to_vmx(vcpu);
5978         int old = vmx->ple_window;
5979 
5980         vmx->ple_window = __shrink_ple_window(old,
5981                                               ple_window_shrink, ple_window);
5982 
5983         if (vmx->ple_window != old)
5984                 vmx->ple_window_dirty = true;
5985 
5986         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5987 }
5988 
5989 /*
5990  * ple_window_actual_max is computed to be one grow_ple_window() below
5991  * ple_window_max. (See __grow_ple_window for the reason.)
5992  * This prevents overflows, because ple_window_max is int.
5993  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5994  * this process.
5995  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5996  */
5997 static void update_ple_window_actual_max(void)
5998 {
5999         ple_window_actual_max =
6000                         __shrink_ple_window(max(ple_window_max, ple_window),
6001                                             ple_window_grow, INT_MIN);
6002 }
6003 
6004 static __init int hardware_setup(void)
6005 {
6006         int r = -ENOMEM, i, msr;
6007 
6008         rdmsrl_safe(MSR_EFER, &host_efer);
6009 
6010         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6011                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6012 
6013         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6014         if (!vmx_io_bitmap_a)
6015                 return r;
6016 
6017         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6018         if (!vmx_io_bitmap_b)
6019                 goto out;
6020 
6021         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6022         if (!vmx_msr_bitmap_legacy)
6023                 goto out1;
6024 
6025         vmx_msr_bitmap_legacy_x2apic =
6026                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6027         if (!vmx_msr_bitmap_legacy_x2apic)
6028                 goto out2;
6029 
6030         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6031         if (!vmx_msr_bitmap_longmode)
6032                 goto out3;
6033 
6034         vmx_msr_bitmap_longmode_x2apic =
6035                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6036         if (!vmx_msr_bitmap_longmode_x2apic)
6037                 goto out4;
6038 
6039         if (nested) {
6040                 vmx_msr_bitmap_nested =
6041                         (unsigned long *)__get_free_page(GFP_KERNEL);
6042                 if (!vmx_msr_bitmap_nested)
6043                         goto out5;
6044         }
6045 
6046         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6047         if (!vmx_vmread_bitmap)
6048                 goto out6;
6049 
6050         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6051         if (!vmx_vmwrite_bitmap)
6052                 goto out7;
6053 
6054         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6055         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6056 
6057         /*
6058          * Allow direct access to the PC debug port (it is often used for I/O
6059          * delays, but the vmexits simply slow things down).
6060          */
6061         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6062         clear_bit(0x80, vmx_io_bitmap_a);
6063 
6064         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6065 
6066         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6067         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6068         if (nested)
6069                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6070 
6071         if (setup_vmcs_config(&vmcs_config) < 0) {
6072                 r = -EIO;
6073                 goto out8;
6074         }
6075 
6076         if (boot_cpu_has(X86_FEATURE_NX))
6077                 kvm_enable_efer_bits(EFER_NX);
6078 
6079         if (!cpu_has_vmx_vpid())
6080                 enable_vpid = 0;
6081         if (!cpu_has_vmx_shadow_vmcs())
6082                 enable_shadow_vmcs = 0;
6083         if (enable_shadow_vmcs)
6084                 init_vmcs_shadow_fields();
6085 
6086         if (!cpu_has_vmx_ept() ||
6087             !cpu_has_vmx_ept_4levels()) {
6088                 enable_ept = 0;
6089                 enable_unrestricted_guest = 0;
6090                 enable_ept_ad_bits = 0;
6091         }
6092 
6093         if (!cpu_has_vmx_ept_ad_bits())
6094                 enable_ept_ad_bits = 0;
6095 
6096         if (!cpu_has_vmx_unrestricted_guest())
6097                 enable_unrestricted_guest = 0;
6098 
6099         if (!cpu_has_vmx_flexpriority())
6100                 flexpriority_enabled = 0;
6101 
6102         /*
6103          * set_apic_access_page_addr() is used to reload apic access
6104          * page upon invalidation.  No need to do anything if not
6105          * using the APIC_ACCESS_ADDR VMCS field.
6106          */
6107         if (!flexpriority_enabled)
6108                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6109 
6110         if (!cpu_has_vmx_tpr_shadow())
6111                 kvm_x86_ops->update_cr8_intercept = NULL;
6112 
6113         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6114                 kvm_disable_largepages();
6115 
6116         if (!cpu_has_vmx_ple())
6117                 ple_gap = 0;
6118 
6119         if (!cpu_has_vmx_apicv())
6120                 enable_apicv = 0;
6121 
6122         if (enable_apicv)
6123                 kvm_x86_ops->update_cr8_intercept = NULL;
6124         else {
6125                 kvm_x86_ops->hwapic_irr_update = NULL;
6126                 kvm_x86_ops->hwapic_isr_update = NULL;
6127                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6128                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6129         }
6130 
6131         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6132         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6133         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6134         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6135         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6136         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6137         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6138 
6139         memcpy(vmx_msr_bitmap_legacy_x2apic,
6140                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6141         memcpy(vmx_msr_bitmap_longmode_x2apic,
6142                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6143 
6144         if (enable_apicv) {
6145                 for (msr = 0x800; msr <= 0x8ff; msr++)
6146                         vmx_disable_intercept_msr_read_x2apic(msr);
6147 
6148                 /* According SDM, in x2apic mode, the whole id reg is used.
6149                  * But in KVM, it only use the highest eight bits. Need to
6150                  * intercept it */
6151                 vmx_enable_intercept_msr_read_x2apic(0x802);
6152                 /* TMCCT */
6153                 vmx_enable_intercept_msr_read_x2apic(0x839);
6154                 /* TPR */