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Linux/include/asm-ppc/system.h

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  1 /*
  2  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
  3  */
  4 #ifndef __PPC_SYSTEM_H
  5 #define __PPC_SYSTEM_H
  6 
  7 #include <linux/config.h>
  8 #include <linux/kernel.h>
  9 
 10 #include <asm/atomic.h>
 11 #include <asm/hw_irq.h>
 12 
 13 /*
 14  * Memory barrier.
 15  * The sync instruction guarantees that all memory accesses initiated
 16  * by this processor have been performed (with respect to all other
 17  * mechanisms that access memory).  The eieio instruction is a barrier
 18  * providing an ordering (separately) for (a) cacheable stores and (b)
 19  * loads and stores to non-cacheable memory (e.g. I/O devices).
 20  *
 21  * mb() prevents loads and stores being reordered across this point.
 22  * rmb() prevents loads being reordered across this point.
 23  * wmb() prevents stores being reordered across this point.
 24  * read_barrier_depends() prevents data-dependent loads being reordered
 25  *      across this point (nop on PPC).
 26  *
 27  * We can use the eieio instruction for wmb, but since it doesn't
 28  * give any ordering guarantees about loads, we have to use the
 29  * stronger but slower sync instruction for mb and rmb.
 30  */
 31 #define mb()  __asm__ __volatile__ ("sync" : : : "memory")
 32 #define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
 33 #define wmb()  __asm__ __volatile__ ("eieio" : : : "memory")
 34 #define read_barrier_depends()  do { } while(0)
 35 
 36 #define set_mb(var, value)      do { var = value; mb(); } while (0)
 37 #define set_wmb(var, value)     do { var = value; wmb(); } while (0)
 38 
 39 #ifdef CONFIG_SMP
 40 #define smp_mb()        mb()
 41 #define smp_rmb()       rmb()
 42 #define smp_wmb()       wmb()
 43 #define smp_read_barrier_depends()      read_barrier_depends()
 44 #else
 45 #define smp_mb()        barrier()
 46 #define smp_rmb()       barrier()
 47 #define smp_wmb()       barrier()
 48 #define smp_read_barrier_depends()      do { } while(0)
 49 #endif /* CONFIG_SMP */
 50 
 51 #ifdef __KERNEL__
 52 struct task_struct;
 53 struct pt_regs;
 54 
 55 extern void print_backtrace(unsigned long *);
 56 extern void show_regs(struct pt_regs * regs);
 57 extern void flush_instruction_cache(void);
 58 extern void hard_reset_now(void);
 59 extern void poweroff_now(void);
 60 #ifdef CONFIG_6xx
 61 extern long _get_L2CR(void);
 62 extern long _get_L3CR(void);
 63 extern void _set_L2CR(unsigned long);
 64 extern void _set_L3CR(unsigned long);
 65 #else
 66 #define _get_L2CR()     0L
 67 #define _get_L3CR()     0L
 68 #define _set_L2CR(val)  do { } while(0)
 69 #define _set_L3CR(val)  do { } while(0)
 70 #endif
 71 extern void via_cuda_init(void);
 72 extern void pmac_nvram_init(void);
 73 extern void read_rtc_time(void);
 74 extern void pmac_find_display(void);
 75 extern void giveup_fpu(struct task_struct *);
 76 extern void enable_kernel_fp(void);
 77 extern void giveup_altivec(struct task_struct *);
 78 extern void load_up_altivec(struct task_struct *);
 79 extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
 80 extern void cvt_df(double *from, float *to, unsigned long *fpscr);
 81 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 82 extern int abs(int);
 83 extern void cacheable_memzero(void *p, unsigned int nb);
 84 
 85 struct device_node;
 86 extern void note_scsi_host(struct device_node *, void *);
 87 
 88 extern struct task_struct *__switch_to(struct task_struct *,
 89         struct task_struct *);
 90 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 91 
 92 struct thread_struct;
 93 extern struct task_struct *_switch(struct thread_struct *prev,
 94                                    struct thread_struct *next);
 95 
 96 extern unsigned int rtas_data;
 97 
 98 extern void dump_regs(struct pt_regs *);
 99 
100 static __inline__ unsigned long
101 xchg_u32(volatile void *p, unsigned long val)
102 {
103         unsigned long prev;
104 
105         __asm__ __volatile__ ("\n\
106 1:      lwarx   %0,0,%2 \n"
107         PPC405_ERR77(0,%2)
108 "       stwcx.  %3,0,%2 \n\
109         bne-    1b"
110         : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
111         : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
112         : "cc", "memory");
113 
114         return prev;
115 }
116 
117 /*
118  * This function doesn't exist, so you'll get a linker error
119  * if something tries to do an invalid xchg().
120  */
121 extern void __xchg_called_with_bad_pointer(void);
122 
123 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
124 #define tas(ptr) (xchg((ptr),1))
125 
126 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
127 {
128         switch (size) {
129         case 4:
130                 return (unsigned long) xchg_u32(ptr, x);
131 #if 0   /* xchg_u64 doesn't exist on 32-bit PPC */
132         case 8:
133                 return (unsigned long) xchg_u64(ptr, x);
134 #endif /* 0 */
135         }
136         __xchg_called_with_bad_pointer();
137         return x;
138 
139 
140 }
141 
142 extern inline void * xchg_ptr(void * m, void * val)
143 {
144         return (void *) xchg_u32(m, (unsigned long) val);
145 }
146 
147 
148 #define __HAVE_ARCH_CMPXCHG     1
149 
150 static __inline__ unsigned long
151 __cmpxchg_u32(volatile int *p, int old, int new)
152 {
153         int prev;
154 
155         __asm__ __volatile__ ("\n\
156 1:      lwarx   %0,0,%2 \n\
157         cmpw    0,%0,%3 \n\
158         bne     2f \n"
159         PPC405_ERR77(0,%2)
160 "       stwcx.  %4,0,%2 \n\
161         bne-    1b\n"
162 #ifdef CONFIG_SMP
163 "       sync\n"
164 #endif /* CONFIG_SMP */
165 "2:"
166         : "=&r" (prev), "=m" (*p)
167         : "r" (p), "r" (old), "r" (new), "m" (*p)
168         : "cc", "memory");
169 
170         return prev;
171 }
172 
173 /* This function doesn't exist, so you'll get a linker error
174    if something tries to do an invalid cmpxchg().  */
175 extern void __cmpxchg_called_with_bad_pointer(void);
176 
177 static __inline__ unsigned long
178 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
179 {
180         switch (size) {
181         case 4:
182                 return __cmpxchg_u32(ptr, old, new);
183 #if 0   /* we don't have __cmpxchg_u64 on 32-bit PPC */
184         case 8:
185                 return __cmpxchg_u64(ptr, old, new);
186 #endif /* 0 */
187         }
188         __cmpxchg_called_with_bad_pointer();
189         return old;
190 }
191 
192 #define cmpxchg(ptr,o,n)                                                 \
193   ({                                                                     \
194      __typeof__(*(ptr)) _o_ = (o);                                       \
195      __typeof__(*(ptr)) _n_ = (n);                                       \
196      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
197                                     (unsigned long)_n_, sizeof(*(ptr))); \
198   })
199 
200 #endif /* __KERNEL__ */
201 #endif /* __PPC_SYSTEM_H */
202 

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