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TOMOYO Linux Cross Reference
Linux/include/linux/mfd/da8xx-cfgchip.h

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  1 /* SPDX-License-Identifier: GPL-2.0-or-later */
  2 /*
  3  * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
  4  *
  5  * Copyright (C) 2016 David Lechner <david@lechnology.com>
  6  */
  7 
  8 #ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
  9 #define __LINUX_MFD_DA8XX_CFGCHIP_H
 10 
 11 #include <linux/bitops.h>
 12 
 13 /* register offset (32-bit registers) */
 14 #define CFGCHIP(n)                              ((n) * 4)
 15 
 16 /* CFGCHIP0 (PLL0/EDMA3_0) register bits */
 17 #define CFGCHIP0_PLL_MASTER_LOCK                BIT(4)
 18 #define CFGCHIP0_EDMA30TC1DBS(n)                ((n) << 2)
 19 #define CFGCHIP0_EDMA30TC1DBS_MASK              CFGCHIP0_EDMA30TC1DBS(0x3)
 20 #define CFGCHIP0_EDMA30TC1DBS_16                CFGCHIP0_EDMA30TC1DBS(0x0)
 21 #define CFGCHIP0_EDMA30TC1DBS_32                CFGCHIP0_EDMA30TC1DBS(0x1)
 22 #define CFGCHIP0_EDMA30TC1DBS_64                CFGCHIP0_EDMA30TC1DBS(0x2)
 23 #define CFGCHIP0_EDMA30TC0DBS(n)                ((n) << 0)
 24 #define CFGCHIP0_EDMA30TC0DBS_MASK              CFGCHIP0_EDMA30TC0DBS(0x3)
 25 #define CFGCHIP0_EDMA30TC0DBS_16                CFGCHIP0_EDMA30TC0DBS(0x0)
 26 #define CFGCHIP0_EDMA30TC0DBS_32                CFGCHIP0_EDMA30TC0DBS(0x1)
 27 #define CFGCHIP0_EDMA30TC0DBS_64                CFGCHIP0_EDMA30TC0DBS(0x2)
 28 
 29 /* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
 30 #define CFGCHIP1_CAP2SRC(n)                     ((n) << 27)
 31 #define CFGCHIP1_CAP2SRC_MASK                   CFGCHIP1_CAP2SRC(0x1f)
 32 #define CFGCHIP1_CAP2SRC_ECAP_PIN               CFGCHIP1_CAP2SRC(0x0)
 33 #define CFGCHIP1_CAP2SRC_MCASP0_TX              CFGCHIP1_CAP2SRC(0x1)
 34 #define CFGCHIP1_CAP2SRC_MCASP0_RX              CFGCHIP1_CAP2SRC(0x2)
 35 #define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD   CFGCHIP1_CAP2SRC(0x7)
 36 #define CFGCHIP1_CAP2SRC_EMAC_C0_RX             CFGCHIP1_CAP2SRC(0x8)
 37 #define CFGCHIP1_CAP2SRC_EMAC_C0_TX             CFGCHIP1_CAP2SRC(0x9)
 38 #define CFGCHIP1_CAP2SRC_EMAC_C0_MISC           CFGCHIP1_CAP2SRC(0xa)
 39 #define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD   CFGCHIP1_CAP2SRC(0xb)
 40 #define CFGCHIP1_CAP2SRC_EMAC_C1_RX             CFGCHIP1_CAP2SRC(0xc)
 41 #define CFGCHIP1_CAP2SRC_EMAC_C1_TX             CFGCHIP1_CAP2SRC(0xd)
 42 #define CFGCHIP1_CAP2SRC_EMAC_C1_MISC           CFGCHIP1_CAP2SRC(0xe)
 43 #define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD   CFGCHIP1_CAP2SRC(0xf)
 44 #define CFGCHIP1_CAP2SRC_EMAC_C2_RX             CFGCHIP1_CAP2SRC(0x10)
 45 #define CFGCHIP1_CAP2SRC_EMAC_C2_TX             CFGCHIP1_CAP2SRC(0x11)
 46 #define CFGCHIP1_CAP2SRC_EMAC_C2_MISC           CFGCHIP1_CAP2SRC(0x12)
 47 #define CFGCHIP1_CAP1SRC(n)                     ((n) << 22)
 48 #define CFGCHIP1_CAP1SRC_MASK                   CFGCHIP1_CAP1SRC(0x1f)
 49 #define CFGCHIP1_CAP1SRC_ECAP_PIN               CFGCHIP1_CAP1SRC(0x0)
 50 #define CFGCHIP1_CAP1SRC_MCASP0_TX              CFGCHIP1_CAP1SRC(0x1)
 51 #define CFGCHIP1_CAP1SRC_MCASP0_RX              CFGCHIP1_CAP1SRC(0x2)
 52 #define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD   CFGCHIP1_CAP1SRC(0x7)
 53 #define CFGCHIP1_CAP1SRC_EMAC_C0_RX             CFGCHIP1_CAP1SRC(0x8)
 54 #define CFGCHIP1_CAP1SRC_EMAC_C0_TX             CFGCHIP1_CAP1SRC(0x9)
 55 #define CFGCHIP1_CAP1SRC_EMAC_C0_MISC           CFGCHIP1_CAP1SRC(0xa)
 56 #define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD   CFGCHIP1_CAP1SRC(0xb)
 57 #define CFGCHIP1_CAP1SRC_EMAC_C1_RX             CFGCHIP1_CAP1SRC(0xc)
 58 #define CFGCHIP1_CAP1SRC_EMAC_C1_TX             CFGCHIP1_CAP1SRC(0xd)
 59 #define CFGCHIP1_CAP1SRC_EMAC_C1_MISC           CFGCHIP1_CAP1SRC(0xe)
 60 #define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD   CFGCHIP1_CAP1SRC(0xf)
 61 #define CFGCHIP1_CAP1SRC_EMAC_C2_RX             CFGCHIP1_CAP1SRC(0x10)
 62 #define CFGCHIP1_CAP1SRC_EMAC_C2_TX             CFGCHIP1_CAP1SRC(0x11)
 63 #define CFGCHIP1_CAP1SRC_EMAC_C2_MISC           CFGCHIP1_CAP1SRC(0x12)
 64 #define CFGCHIP1_CAP0SRC(n)                     ((n) << 17)
 65 #define CFGCHIP1_CAP0SRC_MASK                   CFGCHIP1_CAP0SRC(0x1f)
 66 #define CFGCHIP1_CAP0SRC_ECAP_PIN               CFGCHIP1_CAP0SRC(0x0)
 67 #define CFGCHIP1_CAP0SRC_MCASP0_TX              CFGCHIP1_CAP0SRC(0x1)
 68 #define CFGCHIP1_CAP0SRC_MCASP0_RX              CFGCHIP1_CAP0SRC(0x2)
 69 #define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD   CFGCHIP1_CAP0SRC(0x7)
 70 #define CFGCHIP1_CAP0SRC_EMAC_C0_RX             CFGCHIP1_CAP0SRC(0x8)
 71 #define CFGCHIP1_CAP0SRC_EMAC_C0_TX             CFGCHIP1_CAP0SRC(0x9)
 72 #define CFGCHIP1_CAP0SRC_EMAC_C0_MISC           CFGCHIP1_CAP0SRC(0xa)
 73 #define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD   CFGCHIP1_CAP0SRC(0xb)
 74 #define CFGCHIP1_CAP0SRC_EMAC_C1_RX             CFGCHIP1_CAP0SRC(0xc)
 75 #define CFGCHIP1_CAP0SRC_EMAC_C1_TX             CFGCHIP1_CAP0SRC(0xd)
 76 #define CFGCHIP1_CAP0SRC_EMAC_C1_MISC           CFGCHIP1_CAP0SRC(0xe)
 77 #define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD   CFGCHIP1_CAP0SRC(0xf)
 78 #define CFGCHIP1_CAP0SRC_EMAC_C2_RX             CFGCHIP1_CAP0SRC(0x10)
 79 #define CFGCHIP1_CAP0SRC_EMAC_C2_TX             CFGCHIP1_CAP0SRC(0x11)
 80 #define CFGCHIP1_CAP0SRC_EMAC_C2_MISC           CFGCHIP1_CAP0SRC(0x12)
 81 #define CFGCHIP1_HPIBYTEAD                      BIT(16)
 82 #define CFGCHIP1_HPIENA                         BIT(15)
 83 #define CFGCHIP0_EDMA31TC0DBS(n)                ((n) << 13)
 84 #define CFGCHIP0_EDMA31TC0DBS_MASK              CFGCHIP0_EDMA31TC0DBS(0x3)
 85 #define CFGCHIP0_EDMA31TC0DBS_16                CFGCHIP0_EDMA31TC0DBS(0x0)
 86 #define CFGCHIP0_EDMA31TC0DBS_32                CFGCHIP0_EDMA31TC0DBS(0x1)
 87 #define CFGCHIP0_EDMA31TC0DBS_64                CFGCHIP0_EDMA31TC0DBS(0x2)
 88 #define CFGCHIP1_TBCLKSYNC                      BIT(12)
 89 #define CFGCHIP1_AMUTESEL0(n)                   ((n) << 0)
 90 #define CFGCHIP1_AMUTESEL0_MASK                 CFGCHIP1_AMUTESEL0(0xf)
 91 #define CFGCHIP1_AMUTESEL0_LOW                  CFGCHIP1_AMUTESEL0(0x0)
 92 #define CFGCHIP1_AMUTESEL0_BANK_0               CFGCHIP1_AMUTESEL0(0x1)
 93 #define CFGCHIP1_AMUTESEL0_BANK_1               CFGCHIP1_AMUTESEL0(0x2)
 94 #define CFGCHIP1_AMUTESEL0_BANK_2               CFGCHIP1_AMUTESEL0(0x3)
 95 #define CFGCHIP1_AMUTESEL0_BANK_3               CFGCHIP1_AMUTESEL0(0x4)
 96 #define CFGCHIP1_AMUTESEL0_BANK_4               CFGCHIP1_AMUTESEL0(0x5)
 97 #define CFGCHIP1_AMUTESEL0_BANK_5               CFGCHIP1_AMUTESEL0(0x6)
 98 #define CFGCHIP1_AMUTESEL0_BANK_6               CFGCHIP1_AMUTESEL0(0x7)
 99 #define CFGCHIP1_AMUTESEL0_BANK_7               CFGCHIP1_AMUTESEL0(0x8)
100 
101 /* CFGCHIP2 (USB PHY) register bits */
102 #define CFGCHIP2_PHYCLKGD                       BIT(17)
103 #define CFGCHIP2_VBUSSENSE                      BIT(16)
104 #define CFGCHIP2_RESET                          BIT(15)
105 #define CFGCHIP2_OTGMODE(n)                     ((n) << 13)
106 #define CFGCHIP2_OTGMODE_MASK                   CFGCHIP2_OTGMODE(0x3)
107 #define CFGCHIP2_OTGMODE_NO_OVERRIDE            CFGCHIP2_OTGMODE(0x0)
108 #define CFGCHIP2_OTGMODE_FORCE_HOST             CFGCHIP2_OTGMODE(0x1)
109 #define CFGCHIP2_OTGMODE_FORCE_DEVICE           CFGCHIP2_OTGMODE(0x2)
110 #define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW    CFGCHIP2_OTGMODE(0x3)
111 #define CFGCHIP2_USB1PHYCLKMUX                  BIT(12)
112 #define CFGCHIP2_USB2PHYCLKMUX                  BIT(11)
113 #define CFGCHIP2_PHYPWRDN                       BIT(10)
114 #define CFGCHIP2_OTGPWRDN                       BIT(9)
115 #define CFGCHIP2_DATPOL                         BIT(8)
116 #define CFGCHIP2_USB1SUSPENDM                   BIT(7)
117 #define CFGCHIP2_PHY_PLLON                      BIT(6)
118 #define CFGCHIP2_SESENDEN                       BIT(5)
119 #define CFGCHIP2_VBDTCTEN                       BIT(4)
120 #define CFGCHIP2_REFFREQ(n)                     ((n) << 0)
121 #define CFGCHIP2_REFFREQ_MASK                   CFGCHIP2_REFFREQ(0xf)
122 #define CFGCHIP2_REFFREQ_12MHZ                  CFGCHIP2_REFFREQ(0x1)
123 #define CFGCHIP2_REFFREQ_24MHZ                  CFGCHIP2_REFFREQ(0x2)
124 #define CFGCHIP2_REFFREQ_48MHZ                  CFGCHIP2_REFFREQ(0x3)
125 #define CFGCHIP2_REFFREQ_19_2MHZ                CFGCHIP2_REFFREQ(0x4)
126 #define CFGCHIP2_REFFREQ_38_4MHZ                CFGCHIP2_REFFREQ(0x5)
127 #define CFGCHIP2_REFFREQ_13MHZ                  CFGCHIP2_REFFREQ(0x6)
128 #define CFGCHIP2_REFFREQ_26MHZ                  CFGCHIP2_REFFREQ(0x7)
129 #define CFGCHIP2_REFFREQ_20MHZ                  CFGCHIP2_REFFREQ(0x8)
130 #define CFGCHIP2_REFFREQ_40MHZ                  CFGCHIP2_REFFREQ(0x9)
131 
132 /* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
133 #define CFGCHIP3_RMII_SEL                       BIT(8)
134 #define CFGCHIP3_UPP_TX_CLKSRC                  BIT(6)
135 #define CFGCHIP3_PLL1_MASTER_LOCK               BIT(5)
136 #define CFGCHIP3_ASYNC3_CLKSRC                  BIT(4)
137 #define CFGCHIP3_PRUEVTSEL                      BIT(3)
138 #define CFGCHIP3_DIV45PENA                      BIT(2)
139 #define CFGCHIP3_EMA_CLKSRC                     BIT(1)
140 
141 /* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
142 #define CFGCHIP4_AMUTECLR0                      BIT(0)
143 
144 #endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
145 

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