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TOMOYO Linux Cross Reference
Linux/include/linux/mfd/tmio.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 #ifndef MFD_TMIO_H
  3 #define MFD_TMIO_H
  4 
  5 #include <linux/device.h>
  6 #include <linux/fb.h>
  7 #include <linux/io.h>
  8 #include <linux/jiffies.h>
  9 #include <linux/mmc/card.h>
 10 #include <linux/platform_device.h>
 11 #include <linux/pm_runtime.h>
 12 
 13 #define tmio_ioread8(addr) readb(addr)
 14 #define tmio_ioread16(addr) readw(addr)
 15 #define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
 16 #define tmio_ioread32(addr) \
 17         (((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
 18 
 19 #define tmio_iowrite8(val, addr) writeb((val), (addr))
 20 #define tmio_iowrite16(val, addr) writew((val), (addr))
 21 #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
 22 #define tmio_iowrite32(val, addr) \
 23         do { \
 24                 writew((val),       (addr)); \
 25                 writew((val) >> 16, (addr) + 2); \
 26         } while (0)
 27 
 28 #define sd_config_write8(base, shift, reg, val) \
 29         tmio_iowrite8((val), (base) + ((reg) << (shift)))
 30 #define sd_config_write16(base, shift, reg, val) \
 31         tmio_iowrite16((val), (base) + ((reg) << (shift)))
 32 #define sd_config_write32(base, shift, reg, val) \
 33         do { \
 34                 tmio_iowrite16((val), (base) + ((reg) << (shift)));   \
 35                 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
 36         } while (0)
 37 
 38 /* tmio MMC platform flags */
 39 #define TMIO_MMC_WRPROTECT_DISABLE      BIT(0)
 40 /*
 41  * Some controllers can support a 2-byte block size when the bus width
 42  * is configured in 4-bit mode.
 43  */
 44 #define TMIO_MMC_BLKSZ_2BYTES           BIT(1)
 45 /*
 46  * Some controllers can support SDIO IRQ signalling.
 47  */
 48 #define TMIO_MMC_SDIO_IRQ               BIT(2)
 49 
 50 /* Some features are only available or tested on R-Car Gen2 or later */
 51 #define TMIO_MMC_MIN_RCAR2              BIT(3)
 52 
 53 /*
 54  * Some controllers require waiting for the SD bus to become
 55  * idle before writing to some registers.
 56  */
 57 #define TMIO_MMC_HAS_IDLE_WAIT          BIT(4)
 58 /*
 59  * A GPIO is used for card hotplug detection. We need an extra flag for this,
 60  * because 0 is a valid GPIO number too, and requiring users to specify
 61  * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
 62  */
 63 #define TMIO_MMC_USE_GPIO_CD            BIT(5)
 64 
 65 /*
 66  * Some controllers doesn't have over 0x100 register.
 67  * it is used to checking accessibility of
 68  * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
 69  */
 70 #define TMIO_MMC_HAVE_HIGH_REG          BIT(6)
 71 
 72 /*
 73  * Some controllers have CMD12 automatically
 74  * issue/non-issue register
 75  */
 76 #define TMIO_MMC_HAVE_CMD12_CTRL        BIT(7)
 77 
 78 /* Controller has some SDIO status bits which must be 1 */
 79 #define TMIO_MMC_SDIO_STATUS_SETBITS    BIT(8)
 80 
 81 /*
 82  * Some controllers have a 32-bit wide data port register
 83  */
 84 #define TMIO_MMC_32BIT_DATA_PORT        BIT(9)
 85 
 86 /*
 87  * Some controllers allows to set SDx actual clock
 88  */
 89 #define TMIO_MMC_CLK_ACTUAL             BIT(10)
 90 
 91 /* Some controllers have a CBSY bit */
 92 #define TMIO_MMC_HAVE_CBSY              BIT(11)
 93 
 94 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
 95 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
 96 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
 97 void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
 98 
 99 struct dma_chan;
100 
101 /*
102  * data for the MMC controller
103  */
104 struct tmio_mmc_data {
105         void                            *chan_priv_tx;
106         void                            *chan_priv_rx;
107         unsigned int                    hclk;
108         unsigned long                   capabilities;
109         unsigned long                   capabilities2;
110         unsigned long                   flags;
111         u32                             ocr_mask;       /* available voltages */
112         unsigned int                    cd_gpio;
113         int                             alignment_shift;
114         dma_addr_t                      dma_rx_offset;
115         unsigned int                    max_blk_count;
116         unsigned short                  max_segs;
117         void (*set_pwr)(struct platform_device *host, int state);
118         void (*set_clk_div)(struct platform_device *host, int state);
119 };
120 
121 /*
122  * data for the NAND controller
123  */
124 struct tmio_nand_data {
125         struct nand_bbt_descr   *badblock_pattern;
126         struct mtd_partition    *partition;
127         unsigned int            num_partitions;
128         const char *const       *part_parsers;
129 };
130 
131 #define FBIO_TMIO_ACC_WRITE     0x7C639300
132 #define FBIO_TMIO_ACC_SYNC      0x7C639301
133 
134 struct tmio_fb_data {
135         int                     (*lcd_set_power)(struct platform_device *fb_dev,
136                                                  bool on);
137         int                     (*lcd_mode)(struct platform_device *fb_dev,
138                                             const struct fb_videomode *mode);
139         int                     num_modes;
140         struct fb_videomode     *modes;
141 
142         /* in mm: size of screen */
143         int                     height;
144         int                     width;
145 };
146 
147 #endif
148 

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