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Linux/include/linux/mfd/tps65217.h

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  1 /*
  2  * linux/mfd/tps65217.h
  3  *
  4  * Functions to access TPS65217 power management chip.
  5  *
  6  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License as
 10  * published by the Free Software Foundation version 2.
 11  *
 12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 13  * kind, whether express or implied; without even the implied warranty
 14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15  * GNU General Public License for more details.
 16  */
 17 
 18 #ifndef __LINUX_MFD_TPS65217_H
 19 #define __LINUX_MFD_TPS65217_H
 20 
 21 #include <linux/i2c.h>
 22 #include <linux/regulator/driver.h>
 23 #include <linux/regulator/machine.h>
 24 
 25 /* TPS chip id list */
 26 #define TPS65217                        0xF0
 27 
 28 /* I2C ID for TPS65217 part */
 29 #define TPS65217_I2C_ID                 0x24
 30 
 31 /* All register addresses */
 32 #define TPS65217_REG_CHIPID             0X00
 33 #define TPS65217_REG_PPATH              0X01
 34 #define TPS65217_REG_INT                0X02
 35 #define TPS65217_REG_CHGCONFIG0         0X03
 36 #define TPS65217_REG_CHGCONFIG1         0X04
 37 #define TPS65217_REG_CHGCONFIG2         0X05
 38 #define TPS65217_REG_CHGCONFIG3         0X06
 39 #define TPS65217_REG_WLEDCTRL1          0X07
 40 #define TPS65217_REG_WLEDCTRL2          0X08
 41 #define TPS65217_REG_MUXCTRL            0X09
 42 #define TPS65217_REG_STATUS             0X0A
 43 #define TPS65217_REG_PASSWORD           0X0B
 44 #define TPS65217_REG_PGOOD              0X0C
 45 #define TPS65217_REG_DEFPG              0X0D
 46 #define TPS65217_REG_DEFDCDC1           0X0E
 47 #define TPS65217_REG_DEFDCDC2           0X0F
 48 #define TPS65217_REG_DEFDCDC3           0X10
 49 #define TPS65217_REG_DEFSLEW            0X11
 50 #define TPS65217_REG_DEFLDO1            0X12
 51 #define TPS65217_REG_DEFLDO2            0X13
 52 #define TPS65217_REG_DEFLS1             0X14
 53 #define TPS65217_REG_DEFLS2             0X15
 54 #define TPS65217_REG_ENABLE             0X16
 55 #define TPS65217_REG_DEFUVLO            0X18
 56 #define TPS65217_REG_SEQ1               0X19
 57 #define TPS65217_REG_SEQ2               0X1A
 58 #define TPS65217_REG_SEQ3               0X1B
 59 #define TPS65217_REG_SEQ4               0X1C
 60 #define TPS65217_REG_SEQ5               0X1D
 61 #define TPS65217_REG_SEQ6               0X1E
 62 
 63 #define TPS65217_REG_MAX                TPS65217_REG_SEQ6
 64 
 65 /* Register field definitions */
 66 #define TPS65217_CHIPID_CHIP_MASK       0xF0
 67 #define TPS65217_CHIPID_REV_MASK        0x0F
 68 
 69 #define TPS65217_PPATH_ACSINK_ENABLE    BIT(7)
 70 #define TPS65217_PPATH_USBSINK_ENABLE   BIT(6)
 71 #define TPS65217_PPATH_AC_PW_ENABLE     BIT(5)
 72 #define TPS65217_PPATH_USB_PW_ENABLE    BIT(4)
 73 #define TPS65217_PPATH_AC_CURRENT_MASK  0x0C
 74 #define TPS65217_PPATH_USB_CURRENT_MASK 0x03
 75 
 76 #define TPS65217_INT_PBM                BIT(6)
 77 #define TPS65217_INT_ACM                BIT(5)
 78 #define TPS65217_INT_USBM               BIT(4)
 79 #define TPS65217_INT_PBI                BIT(2)
 80 #define TPS65217_INT_ACI                BIT(1)
 81 #define TPS65217_INT_USBI               BIT(0)
 82 
 83 #define TPS65217_CHGCONFIG0_TREG        BIT(7)
 84 #define TPS65217_CHGCONFIG0_DPPM        BIT(6)
 85 #define TPS65217_CHGCONFIG0_TSUSP       BIT(5)
 86 #define TPS65217_CHGCONFIG0_TERMI       BIT(4)
 87 #define TPS65217_CHGCONFIG0_ACTIVE      BIT(3)
 88 #define TPS65217_CHGCONFIG0_CHGTOUT     BIT(2)
 89 #define TPS65217_CHGCONFIG0_PCHGTOUT    BIT(1)
 90 #define TPS65217_CHGCONFIG0_BATTEMP     BIT(0)
 91 
 92 #define TPS65217_CHGCONFIG1_TMR_MASK    0xC0
 93 #define TPS65217_CHGCONFIG1_TMR_ENABLE  BIT(5)
 94 #define TPS65217_CHGCONFIG1_NTC_TYPE    BIT(4)
 95 #define TPS65217_CHGCONFIG1_RESET       BIT(3)
 96 #define TPS65217_CHGCONFIG1_TERM        BIT(2)
 97 #define TPS65217_CHGCONFIG1_SUSP        BIT(1)
 98 #define TPS65217_CHGCONFIG1_CHG_EN      BIT(0)
 99 
100 #define TPS65217_CHGCONFIG2_DYNTMR      BIT(7)
101 #define TPS65217_CHGCONFIG2_VPREGHG     BIT(6)
102 #define TPS65217_CHGCONFIG2_VOREG_MASK  0x30
103 
104 #define TPS65217_CHGCONFIG3_ICHRG_MASK  0xC0
105 #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
106 #define TPS65217_CHGCONFIG2_PCHRGT      BIT(3)
107 #define TPS65217_CHGCONFIG2_TERMIF      0x06
108 #define TPS65217_CHGCONFIG2_TRANGE      BIT(0)
109 
110 #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
111 #define TPS65217_WLEDCTRL1_ISEL         BIT(2)
112 #define TPS65217_WLEDCTRL1_FDIM_MASK    0x03
113 
114 #define TPS65217_WLEDCTRL2_DUTY_MASK    0x7F
115 
116 #define TPS65217_MUXCTRL_MUX_MASK       0x07
117 
118 #define TPS65217_STATUS_OFF             BIT(7)
119 #define TPS65217_STATUS_ACPWR           BIT(3)
120 #define TPS65217_STATUS_USBPWR          BIT(2)
121 #define TPS65217_STATUS_PB              BIT(0)
122 
123 #define TPS65217_PASSWORD_REGS_UNLOCK   0x7D
124 
125 #define TPS65217_PGOOD_LDO3_PG          BIT(6)
126 #define TPS65217_PGOOD_LDO4_PG          BIT(5)
127 #define TPS65217_PGOOD_DC1_PG           BIT(4)
128 #define TPS65217_PGOOD_DC2_PG           BIT(3)
129 #define TPS65217_PGOOD_DC3_PG           BIT(2)
130 #define TPS65217_PGOOD_LDO1_PG          BIT(1)
131 #define TPS65217_PGOOD_LDO2_PG          BIT(0)
132 
133 #define TPS65217_DEFPG_LDO1PGM          BIT(3)
134 #define TPS65217_DEFPG_LDO2PGM          BIT(2)
135 #define TPS65217_DEFPG_PGDLY_MASK       0x03
136 
137 #define TPS65217_DEFDCDCX_XADJX         BIT(7)
138 #define TPS65217_DEFDCDCX_DCDC_MASK     0x3F
139 
140 #define TPS65217_DEFSLEW_GO             BIT(7)
141 #define TPS65217_DEFSLEW_GODSBL         BIT(6)
142 #define TPS65217_DEFSLEW_PFM_EN1        BIT(5)
143 #define TPS65217_DEFSLEW_PFM_EN2        BIT(4)
144 #define TPS65217_DEFSLEW_PFM_EN3        BIT(3)
145 #define TPS65217_DEFSLEW_SLEW_MASK      0x07
146 
147 #define TPS65217_DEFLDO1_LDO1_MASK      0x0F
148 
149 #define TPS65217_DEFLDO2_TRACK          BIT(6)
150 #define TPS65217_DEFLDO2_LDO2_MASK      0x3F
151 
152 #define TPS65217_DEFLDO3_LDO3_EN        BIT(5)
153 #define TPS65217_DEFLDO3_LDO3_MASK      0x1F
154 
155 #define TPS65217_DEFLDO4_LDO4_EN        BIT(5)
156 #define TPS65217_DEFLDO4_LDO4_MASK      0x1F
157 
158 #define TPS65217_ENABLE_LS1_EN          BIT(6)
159 #define TPS65217_ENABLE_LS2_EN          BIT(5)
160 #define TPS65217_ENABLE_DC1_EN          BIT(4)
161 #define TPS65217_ENABLE_DC2_EN          BIT(3)
162 #define TPS65217_ENABLE_DC3_EN          BIT(2)
163 #define TPS65217_ENABLE_LDO1_EN         BIT(1)
164 #define TPS65217_ENABLE_LDO2_EN         BIT(0)
165 
166 #define TPS65217_DEFUVLO_UVLOHYS        BIT(2)
167 #define TPS65217_DEFUVLO_UVLO_MASK      0x03
168 
169 #define TPS65217_SEQ1_DC1_SEQ_MASK      0xF0
170 #define TPS65217_SEQ1_DC2_SEQ_MASK      0x0F
171 
172 #define TPS65217_SEQ2_DC3_SEQ_MASK      0xF0
173 #define TPS65217_SEQ2_LDO1_SEQ_MASK     0x0F
174 
175 #define TPS65217_SEQ3_LDO2_SEQ_MASK     0xF0
176 #define TPS65217_SEQ3_LDO3_SEQ_MASK     0x0F
177 
178 #define TPS65217_SEQ4_LDO4_SEQ_MASK     0xF0
179 
180 #define TPS65217_SEQ5_DLY1_MASK         0xC0
181 #define TPS65217_SEQ5_DLY2_MASK         0x30
182 #define TPS65217_SEQ5_DLY3_MASK         0x0C
183 #define TPS65217_SEQ5_DLY4_MASK         0x03
184 
185 #define TPS65217_SEQ6_DLY5_MASK         0xC0
186 #define TPS65217_SEQ6_DLY6_MASK         0x30
187 #define TPS65217_SEQ6_SEQUP             BIT(2)
188 #define TPS65217_SEQ6_SEQDWN            BIT(1)
189 #define TPS65217_SEQ6_INSTDWN           BIT(0)
190 
191 #define TPS65217_MAX_REGISTER           0x1E
192 #define TPS65217_PROTECT_NONE           0
193 #define TPS65217_PROTECT_L1             1
194 #define TPS65217_PROTECT_L2             2
195 
196 
197 enum tps65217_regulator_id {
198         /* DCDC's */
199         TPS65217_DCDC_1,
200         TPS65217_DCDC_2,
201         TPS65217_DCDC_3,
202         /* LDOs */
203         TPS65217_LDO_1,
204         TPS65217_LDO_2,
205         TPS65217_LDO_3,
206         TPS65217_LDO_4,
207 };
208 
209 #define TPS65217_MAX_REG_ID             TPS65217_LDO_4
210 
211 /* Number of step-down converters available */
212 #define TPS65217_NUM_DCDC               3
213 /* Number of LDO voltage regulators available */
214 #define TPS65217_NUM_LDO                4
215 /* Number of total regulators available */
216 #define TPS65217_NUM_REGULATOR          (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
217 
218 enum tps65217_bl_isel {
219         TPS65217_BL_ISET1 = 1,
220         TPS65217_BL_ISET2,
221 };
222 
223 enum tps65217_bl_fdim {
224         TPS65217_BL_FDIM_100HZ,
225         TPS65217_BL_FDIM_200HZ,
226         TPS65217_BL_FDIM_500HZ,
227         TPS65217_BL_FDIM_1000HZ,
228 };
229 
230 struct tps65217_bl_pdata {
231         enum tps65217_bl_isel isel;
232         enum tps65217_bl_fdim fdim;
233         int dft_brightness;
234 };
235 
236 /**
237  * struct tps65217_board - packages regulator init data
238  * @tps65217_regulator_data: regulator initialization values
239  *
240  * Board data may be used to initialize regulator.
241  */
242 struct tps65217_board {
243         struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
244         struct device_node *of_node[TPS65217_NUM_REGULATOR];
245         struct tps65217_bl_pdata *bl_pdata;
246 };
247 
248 /**
249  * struct tps65217 - tps65217 sub-driver chip access routines
250  *
251  * Device data may be used to access the TPS65217 chip
252  */
253 
254 struct tps65217 {
255         struct device *dev;
256         struct tps65217_board *pdata;
257         unsigned long id;
258         struct regulator_desc desc[TPS65217_NUM_REGULATOR];
259         struct regmap *regmap;
260 };
261 
262 static inline struct tps65217 *dev_to_tps65217(struct device *dev)
263 {
264         return dev_get_drvdata(dev);
265 }
266 
267 static inline unsigned long tps65217_chip_id(struct tps65217 *tps65217)
268 {
269         return tps65217->id;
270 }
271 
272 int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
273                                         unsigned int *val);
274 int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
275                         unsigned int val, unsigned int level);
276 int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
277                 unsigned int mask, unsigned int val, unsigned int level);
278 int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
279                 unsigned int mask, unsigned int level);
280 
281 #endif /*  __LINUX_MFD_TPS65217_H */
282 

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