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TOMOYO Linux Cross Reference
Linux/include/linux/pci.h

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  1 /*
  2  *      pci.h
  3  *
  4  *      PCI defines and function prototypes
  5  *      Copyright 1994, Drew Eckhardt
  6  *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  7  *
  8  *      For more information, please consult the following manuals (look at
  9  *      http://www.pcisig.com/ for how to get them):
 10  *
 11  *      PCI BIOS Specification
 12  *      PCI Local Bus Specification
 13  *      PCI to PCI Bridge Specification
 14  *      PCI System Design Guide
 15  */
 16 #ifndef LINUX_PCI_H
 17 #define LINUX_PCI_H
 18 
 19 
 20 #include <linux/mod_devicetable.h>
 21 
 22 #include <linux/types.h>
 23 #include <linux/init.h>
 24 #include <linux/ioport.h>
 25 #include <linux/list.h>
 26 #include <linux/compiler.h>
 27 #include <linux/errno.h>
 28 #include <linux/kobject.h>
 29 #include <linux/atomic.h>
 30 #include <linux/device.h>
 31 #include <linux/io.h>
 32 #include <linux/irqreturn.h>
 33 #include <uapi/linux/pci.h>
 34 
 35 /* Include the ID list */
 36 #include <linux/pci_ids.h>
 37 
 38 /*
 39  * The PCI interface treats multi-function devices as independent
 40  * devices.  The slot/function address of each device is encoded
 41  * in a single byte as follows:
 42  *
 43  *      7:3 = slot
 44  *      2:0 = function
 45  * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h
 46  * In the interest of not exposing interfaces to user-space unnecessarily,
 47  * the following kernel only defines are being added here.
 48  */
 49 #define PCI_DEVID(bus, devfn)  ((((u16)bus) << 8) | devfn)
 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
 52 
 53 /* pci_slot represents a physical slot */
 54 struct pci_slot {
 55         struct pci_bus *bus;            /* The bus this slot is on */
 56         struct list_head list;          /* node in list of slots on this bus */
 57         struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
 58         unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
 59         struct kobject kobj;
 60 };
 61 
 62 static inline const char *pci_slot_name(const struct pci_slot *slot)
 63 {
 64         return kobject_name(&slot->kobj);
 65 }
 66 
 67 /* File state for mmap()s on /proc/bus/pci/X/Y */
 68 enum pci_mmap_state {
 69         pci_mmap_io,
 70         pci_mmap_mem
 71 };
 72 
 73 /* This defines the direction arg to the DMA mapping routines. */
 74 #define PCI_DMA_BIDIRECTIONAL   0
 75 #define PCI_DMA_TODEVICE        1
 76 #define PCI_DMA_FROMDEVICE      2
 77 #define PCI_DMA_NONE            3
 78 
 79 /*
 80  *  For PCI devices, the region numbers are assigned this way:
 81  */
 82 enum {
 83         /* #0-5: standard PCI resources */
 84         PCI_STD_RESOURCES,
 85         PCI_STD_RESOURCE_END = 5,
 86 
 87         /* #6: expansion ROM resource */
 88         PCI_ROM_RESOURCE,
 89 
 90         /* device specific resources */
 91 #ifdef CONFIG_PCI_IOV
 92         PCI_IOV_RESOURCES,
 93         PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
 94 #endif
 95 
 96         /* resources assigned to buses behind the bridge */
 97 #define PCI_BRIDGE_RESOURCE_NUM 4
 98 
 99         PCI_BRIDGE_RESOURCES,
100         PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101                                   PCI_BRIDGE_RESOURCE_NUM - 1,
102 
103         /* total resources associated with a PCI device */
104         PCI_NUM_RESOURCES,
105 
106         /* preserve this for compatibility */
107         DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
108 };
109 
110 typedef int __bitwise pci_power_t;
111 
112 #define PCI_D0          ((pci_power_t __force) 0)
113 #define PCI_D1          ((pci_power_t __force) 1)
114 #define PCI_D2          ((pci_power_t __force) 2)
115 #define PCI_D3hot       ((pci_power_t __force) 3)
116 #define PCI_D3cold      ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN     ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
119 
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names[];
122 
123 static inline const char *pci_power_name(pci_power_t state)
124 {
125         return pci_power_names[1 + (int) state];
126 }
127 
128 #define PCI_PM_D2_DELAY         200
129 #define PCI_PM_D3_WAIT          10
130 #define PCI_PM_D3COLD_WAIT      100
131 #define PCI_PM_BUS_WAIT         50
132 
133 /** The pci_channel state describes connectivity between the CPU and
134  *  the pci device.  If some PCI bus between here and the pci device
135  *  has crashed or locked up, this info is reflected here.
136  */
137 typedef unsigned int __bitwise pci_channel_state_t;
138 
139 enum pci_channel_state {
140         /* I/O channel is in normal state */
141         pci_channel_io_normal = (__force pci_channel_state_t) 1,
142 
143         /* I/O to channel is blocked */
144         pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145 
146         /* PCI card is dead */
147         pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 };
149 
150 typedef unsigned int __bitwise pcie_reset_state_t;
151 
152 enum pcie_reset_state {
153         /* Reset is NOT asserted (Use to deassert reset) */
154         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155 
156         /* Use #PERST to reset PCI-E device */
157         pcie_warm_reset = (__force pcie_reset_state_t) 2,
158 
159         /* Use PCI-E Hot Reset to reset device */
160         pcie_hot_reset = (__force pcie_reset_state_t) 3
161 };
162 
163 typedef unsigned short __bitwise pci_dev_flags_t;
164 enum pci_dev_flags {
165         /* INTX_DISABLE in PCI_COMMAND register disables MSI
166          * generation too.
167          */
168         PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
169         /* Device configuration is irrevocably lost if disabled into D3 */
170         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
171         /* Provide indication device is assigned by a Virtual Machine Manager */
172         PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
173         /* Get VPD from function 0 VPD */
174         PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
175 };
176 
177 enum pci_irq_reroute_variant {
178         INTEL_IRQ_REROUTE_VARIANT = 1,
179         MAX_IRQ_REROUTE_VARIANTS = 3
180 };
181 
182 typedef unsigned short __bitwise pci_bus_flags_t;
183 enum pci_bus_flags {
184         PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
185         PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
186 };
187 
188 /* These values come from the PCI Express Spec */
189 enum pcie_link_width {
190         PCIE_LNK_WIDTH_RESRV    = 0x00,
191         PCIE_LNK_X1             = 0x01,
192         PCIE_LNK_X2             = 0x02,
193         PCIE_LNK_X4             = 0x04,
194         PCIE_LNK_X8             = 0x08,
195         PCIE_LNK_X12            = 0x0C,
196         PCIE_LNK_X16            = 0x10,
197         PCIE_LNK_X32            = 0x20,
198         PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
199 };
200 
201 /* Based on the PCI Hotplug Spec, but some values are made up by us */
202 enum pci_bus_speed {
203         PCI_SPEED_33MHz                 = 0x00,
204         PCI_SPEED_66MHz                 = 0x01,
205         PCI_SPEED_66MHz_PCIX            = 0x02,
206         PCI_SPEED_100MHz_PCIX           = 0x03,
207         PCI_SPEED_133MHz_PCIX           = 0x04,
208         PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
209         PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
210         PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
211         PCI_SPEED_66MHz_PCIX_266        = 0x09,
212         PCI_SPEED_100MHz_PCIX_266       = 0x0a,
213         PCI_SPEED_133MHz_PCIX_266       = 0x0b,
214         AGP_UNKNOWN                     = 0x0c,
215         AGP_1X                          = 0x0d,
216         AGP_2X                          = 0x0e,
217         AGP_4X                          = 0x0f,
218         AGP_8X                          = 0x10,
219         PCI_SPEED_66MHz_PCIX_533        = 0x11,
220         PCI_SPEED_100MHz_PCIX_533       = 0x12,
221         PCI_SPEED_133MHz_PCIX_533       = 0x13,
222         PCIE_SPEED_2_5GT                = 0x14,
223         PCIE_SPEED_5_0GT                = 0x15,
224         PCIE_SPEED_8_0GT                = 0x16,
225         PCI_SPEED_UNKNOWN               = 0xff,
226 };
227 
228 struct pci_cap_saved_data {
229         char cap_nr;
230         unsigned int size;
231         u32 data[0];
232 };
233 
234 struct pci_cap_saved_state {
235         struct hlist_node next;
236         struct pci_cap_saved_data cap;
237 };
238 
239 struct pcie_link_state;
240 struct pci_vpd;
241 struct pci_sriov;
242 struct pci_ats;
243 
244 /*
245  * The pci_dev structure is used to describe PCI devices.
246  */
247 struct pci_dev {
248         struct list_head bus_list;      /* node in per-bus list */
249         struct pci_bus  *bus;           /* bus this device is on */
250         struct pci_bus  *subordinate;   /* bus this device bridges to */
251 
252         void            *sysdata;       /* hook for sys-specific extension */
253         struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
254         struct pci_slot *slot;          /* Physical slot this device is in */
255 
256         unsigned int    devfn;          /* encoded device & function index */
257         unsigned short  vendor;
258         unsigned short  device;
259         unsigned short  subsystem_vendor;
260         unsigned short  subsystem_device;
261         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
262         u8              revision;       /* PCI revision, low byte of class word */
263         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
264         u8              pcie_cap;       /* PCI-E capability offset */
265         u8              msi_cap;        /* MSI capability offset */
266         u8              msix_cap;       /* MSI-X capability offset */
267         u8              pcie_mpss:3;    /* PCI-E Max Payload Size Supported */
268         u8              rom_base_reg;   /* which config register controls the ROM */
269         u8              pin;            /* which interrupt pin this device uses */
270         u16             pcie_flags_reg; /* cached PCI-E Capabilities Register */
271 
272         struct pci_driver *driver;      /* which driver has allocated this device */
273         u64             dma_mask;       /* Mask of the bits of bus address this
274                                            device implements.  Normally this is
275                                            0xffffffff.  You only need to change
276                                            this if your device has broken DMA
277                                            or supports 64-bit transfers.  */
278 
279         struct device_dma_parameters dma_parms;
280 
281         pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
282                                            this is D0-D3, D0 being fully functional,
283                                            and D3 being off. */
284         u8              pm_cap;         /* PM capability offset */
285         unsigned int    pme_support:5;  /* Bitmask of states from which PME#
286                                            can be generated */
287         unsigned int    pme_interrupt:1;
288         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
289         unsigned int    d1_support:1;   /* Low power state D1 is supported */
290         unsigned int    d2_support:1;   /* Low power state D2 is supported */
291         unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
292         unsigned int    no_d3cold:1;    /* D3cold is forbidden */
293         unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
294         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
295                                                    decoding during bar sizing */
296         unsigned int    wakeup_prepared:1;
297         unsigned int    runtime_d3cold:1;       /* whether go through runtime
298                                                    D3cold, not set for devices
299                                                    powered on/off by the
300                                                    corresponding bridge */
301         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
302         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
303 
304 #ifdef CONFIG_PCIEASPM
305         struct pcie_link_state  *link_state;    /* ASPM link state. */
306 #endif
307 
308         pci_channel_state_t error_state;        /* current connectivity state */
309         struct  device  dev;            /* Generic device interface */
310 
311         int             cfg_size;       /* Size of configuration space */
312 
313         /*
314          * Instead of touching interrupt line and base address registers
315          * directly, use the values stored here. They might be different!
316          */
317         unsigned int    irq;
318         struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
319 
320         bool match_driver;              /* Skip attaching driver */
321         /* These fields are used by common fixups */
322         unsigned int    transparent:1;  /* Transparent PCI bridge */
323         unsigned int    multifunction:1;/* Part of multi-function device */
324         /* keep track of device state */
325         unsigned int    is_added:1;
326         unsigned int    is_busmaster:1; /* device is busmaster */
327         unsigned int    no_msi:1;       /* device may not use msi */
328         unsigned int    no_64bit_msi:1; /* device may only use 32-bit MSIs */
329         unsigned int    block_cfg_access:1;     /* config space access is blocked */
330         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
331         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
332         unsigned int    msi_enabled:1;
333         unsigned int    msix_enabled:1;
334         unsigned int    ari_enabled:1;  /* ARI forwarding */
335         unsigned int    is_managed:1;
336         unsigned int    is_pcie:1;      /* Obsolete. Will be removed.
337                                            Use pci_is_pcie() instead */
338         unsigned int    needs_freset:1; /* Dev requires fundamental reset */
339         unsigned int    state_saved:1;
340         unsigned int    is_physfn:1;
341         unsigned int    is_virtfn:1;
342         unsigned int    reset_fn:1;
343         unsigned int    is_hotplug_bridge:1;
344         unsigned int    __aer_firmware_first_valid:1;
345         unsigned int    __aer_firmware_first:1;
346         unsigned int    broken_intx_masking:1;
347         unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
348         unsigned int    non_compliant_bars:1;   /* broken BARs; ignore them */
349         pci_dev_flags_t dev_flags;
350         atomic_t        enable_cnt;     /* pci_enable_device has been called */
351 
352         u32             saved_config_space[16]; /* config space saved at suspend time */
353         struct hlist_head saved_cap_space;
354         struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
355         int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
356         struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
357         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
358 #ifdef CONFIG_PCI_MSI
359         struct list_head msi_list;
360         struct kset *msi_kset;
361 #endif
362         struct pci_vpd *vpd;
363 #ifdef CONFIG_PCI_ATS
364         union {
365                 struct pci_sriov *sriov;        /* SR-IOV capability related */
366                 struct pci_dev *physfn; /* the PF this VF is associated with */
367         };
368         struct pci_ats  *ats;   /* Address Translation Service */
369 #endif
370         phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
371         size_t romlen; /* Length of ROM if it's not from the BAR */
372 };
373 
374 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
375 {
376 #ifdef CONFIG_PCI_IOV
377         if (dev->is_virtfn)
378                 dev = dev->physfn;
379 #endif
380 
381         return dev;
382 }
383 
384 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
385 struct pci_dev * __deprecated alloc_pci_dev(void);
386 
387 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
388 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
389 
390 static inline int pci_channel_offline(struct pci_dev *pdev)
391 {
392         return (pdev->error_state != pci_channel_io_normal);
393 }
394 
395 extern struct resource busn_resource;
396 
397 struct pci_host_bridge_window {
398         struct list_head list;
399         struct resource *res;           /* host bridge aperture (CPU address) */
400         resource_size_t offset;         /* bus address + offset = CPU address */
401 };
402 
403 struct pci_host_bridge {
404         struct device dev;
405         struct pci_bus *bus;            /* root bus */
406         struct list_head windows;       /* pci_host_bridge_windows */
407         void (*release_fn)(struct pci_host_bridge *);
408         void *release_data;
409 };
410 
411 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
412 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
413                      void (*release_fn)(struct pci_host_bridge *),
414                      void *release_data);
415 
416 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
417 
418 /*
419  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
420  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
421  * buses below host bridges or subtractive decode bridges) go in the list.
422  * Use pci_bus_for_each_resource() to iterate through all the resources.
423  */
424 
425 /*
426  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
427  * and there's no way to program the bridge with the details of the window.
428  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
429  * decode bit set, because they are explicit and can be programmed with _SRS.
430  */
431 #define PCI_SUBTRACTIVE_DECODE  0x1
432 
433 struct pci_bus_resource {
434         struct list_head list;
435         struct resource *res;
436         unsigned int flags;
437 };
438 
439 #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
440 
441 struct pci_bus {
442         struct list_head node;          /* node in list of buses */
443         struct pci_bus  *parent;        /* parent bus this bridge is on */
444         struct list_head children;      /* list of child buses */
445         struct list_head devices;       /* list of devices on this bus */
446         struct pci_dev  *self;          /* bridge device as seen by parent */
447         struct list_head slots;         /* list of slots on this bus */
448         struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
449         struct list_head resources;     /* address space routed to this bus */
450         struct resource busn_res;       /* bus numbers routed to this bus */
451 
452         struct pci_ops  *ops;           /* configuration access functions */
453         struct msi_chip *msi;           /* MSI controller */
454         void            *sysdata;       /* hook for sys-specific extension */
455         struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
456 
457         unsigned char   number;         /* bus number */
458         unsigned char   primary;        /* number of primary bridge */
459         unsigned char   max_bus_speed;  /* enum pci_bus_speed */
460         unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
461 
462         char            name[48];
463 
464         unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
465         pci_bus_flags_t bus_flags;      /* Inherited by child busses */
466         struct device           *bridge;
467         struct device           dev;
468         struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
469         struct bin_attribute    *legacy_mem; /* legacy mem */
470         unsigned int            is_added:1;
471 };
472 
473 #define pci_bus_b(n)    list_entry(n, struct pci_bus, node)
474 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
475 
476 /*
477  * Returns true if the pci bus is root (behind host-pci bridge),
478  * false otherwise
479  */
480 static inline bool pci_is_root_bus(struct pci_bus *pbus)
481 {
482         return !(pbus->parent);
483 }
484 
485 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
486 {
487         dev = pci_physfn(dev);
488         if (pci_is_root_bus(dev->bus))
489                 return NULL;
490 
491         return dev->bus->self;
492 }
493 
494 #ifdef CONFIG_PCI_MSI
495 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
496 {
497         return pci_dev->msi_enabled || pci_dev->msix_enabled;
498 }
499 #else
500 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
501 #endif
502 
503 /*
504  * Error values that may be returned by PCI functions.
505  */
506 #define PCIBIOS_SUCCESSFUL              0x00
507 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
508 #define PCIBIOS_BAD_VENDOR_ID           0x83
509 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
510 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
511 #define PCIBIOS_SET_FAILED              0x88
512 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
513 
514 /*
515  * Translate above to generic errno for passing back through non-pci.
516  */
517 static inline int pcibios_err_to_errno(int err)
518 {
519         if (err <= PCIBIOS_SUCCESSFUL)
520                 return err; /* Assume already errno */
521 
522         switch (err) {
523         case PCIBIOS_FUNC_NOT_SUPPORTED:
524                 return -ENOENT;
525         case PCIBIOS_BAD_VENDOR_ID:
526                 return -EINVAL;
527         case PCIBIOS_DEVICE_NOT_FOUND:
528                 return -ENODEV;
529         case PCIBIOS_BAD_REGISTER_NUMBER:
530                 return -EFAULT;
531         case PCIBIOS_SET_FAILED:
532                 return -EIO;
533         case PCIBIOS_BUFFER_TOO_SMALL:
534                 return -ENOSPC;
535         }
536 
537         return -ENOTTY;
538 }
539 
540 /* Low-level architecture-dependent routines */
541 
542 struct pci_ops {
543         int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
544         int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
545 };
546 
547 /*
548  * ACPI needs to be able to access PCI config space before we've done a
549  * PCI bus scan and created pci_bus structures.
550  */
551 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
552                  int reg, int len, u32 *val);
553 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
554                   int reg, int len, u32 val);
555 
556 struct pci_bus_region {
557         resource_size_t start;
558         resource_size_t end;
559 };
560 
561 struct pci_dynids {
562         spinlock_t lock;            /* protects list, index */
563         struct list_head list;      /* for IDs added at runtime */
564 };
565 
566 /* ---------------------------------------------------------------- */
567 /** PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
568  *  a set of callbacks in struct pci_error_handlers, then that device driver
569  *  will be notified of PCI bus errors, and will be driven to recovery
570  *  when an error occurs.
571  */
572 
573 typedef unsigned int __bitwise pci_ers_result_t;
574 
575 enum pci_ers_result {
576         /* no result/none/not supported in device driver */
577         PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
578 
579         /* Device driver can recover without slot reset */
580         PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
581 
582         /* Device driver wants slot to be reset. */
583         PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
584 
585         /* Device has completely failed, is unrecoverable */
586         PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
587 
588         /* Device driver is fully recovered and operational */
589         PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
590 
591         /* No AER capabilities registered for the driver */
592         PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
593 };
594 
595 /* PCI bus error event callbacks */
596 struct pci_error_handlers {
597         /* PCI bus error detected on this device */
598         pci_ers_result_t (*error_detected)(struct pci_dev *dev,
599                                            enum pci_channel_state error);
600 
601         /* MMIO has been re-enabled, but not DMA */
602         pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
603 
604         /* PCI Express link has been reset */
605         pci_ers_result_t (*link_reset)(struct pci_dev *dev);
606 
607         /* PCI slot has been reset */
608         pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
609 
610         /* Device driver may resume normal operations */
611         void (*resume)(struct pci_dev *dev);
612 };
613 
614 /* ---------------------------------------------------------------- */
615 
616 struct module;
617 struct pci_driver {
618         struct list_head node;
619         const char *name;
620         const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
621         int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
622         void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
623         int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
624         int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
625         int  (*resume_early) (struct pci_dev *dev);
626         int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
627         void (*shutdown) (struct pci_dev *dev);
628         int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
629         const struct pci_error_handlers *err_handler;
630         struct device_driver    driver;
631         struct pci_dynids dynids;
632 };
633 
634 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
635 
636 /**
637  * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
638  * @_table: device table name
639  *
640  * This macro is used to create a struct pci_device_id array (a device table)
641  * in a generic manner.
642  */
643 #define DEFINE_PCI_DEVICE_TABLE(_table) \
644         const struct pci_device_id _table[]
645 
646 /**
647  * PCI_DEVICE - macro used to describe a specific pci device
648  * @vend: the 16 bit PCI Vendor ID
649  * @dev: the 16 bit PCI Device ID
650  *
651  * This macro is used to create a struct pci_device_id that matches a
652  * specific device.  The subvendor and subdevice fields will be set to
653  * PCI_ANY_ID.
654  */
655 #define PCI_DEVICE(vend,dev) \
656         .vendor = (vend), .device = (dev), \
657         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
658 
659 /**
660  * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
661  * @vend: the 16 bit PCI Vendor ID
662  * @dev: the 16 bit PCI Device ID
663  * @subvend: the 16 bit PCI Subvendor ID
664  * @subdev: the 16 bit PCI Subdevice ID
665  *
666  * This macro is used to create a struct pci_device_id that matches a
667  * specific device with subsystem information.
668  */
669 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
670         .vendor = (vend), .device = (dev), \
671         .subvendor = (subvend), .subdevice = (subdev)
672 
673 /**
674  * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
675  * @dev_class: the class, subclass, prog-if triple for this device
676  * @dev_class_mask: the class mask for this device
677  *
678  * This macro is used to create a struct pci_device_id that matches a
679  * specific PCI class.  The vendor, device, subvendor, and subdevice
680  * fields will be set to PCI_ANY_ID.
681  */
682 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
683         .class = (dev_class), .class_mask = (dev_class_mask), \
684         .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
685         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
686 
687 /**
688  * PCI_VDEVICE - macro used to describe a specific pci device in short form
689  * @vendor: the vendor name
690  * @device: the 16 bit PCI Device ID
691  *
692  * This macro is used to create a struct pci_device_id that matches a
693  * specific PCI device.  The subvendor, and subdevice fields will be set
694  * to PCI_ANY_ID. The macro allows the next field to follow as the device
695  * private data.
696  */
697 
698 #define PCI_VDEVICE(vendor, device)             \
699         PCI_VENDOR_ID_##vendor, (device),       \
700         PCI_ANY_ID, PCI_ANY_ID, 0, 0
701 
702 /* these external functions are only available when PCI support is enabled */
703 #ifdef CONFIG_PCI
704 
705 void pcie_bus_configure_settings(struct pci_bus *bus);
706 
707 enum pcie_bus_config_types {
708         PCIE_BUS_TUNE_OFF,
709         PCIE_BUS_SAFE,
710         PCIE_BUS_PERFORMANCE,
711         PCIE_BUS_PEER2PEER,
712 };
713 
714 extern enum pcie_bus_config_types pcie_bus_config;
715 
716 extern struct bus_type pci_bus_type;
717 
718 /* Do NOT directly access these two variables, unless you are arch specific pci
719  * code, or pci core code. */
720 extern struct list_head pci_root_buses; /* list of all known PCI buses */
721 /* Some device drivers need know if pci is initiated */
722 int no_pci_devices(void);
723 
724 void pcibios_resource_survey_bus(struct pci_bus *bus);
725 void pcibios_add_bus(struct pci_bus *bus);
726 void pcibios_remove_bus(struct pci_bus *bus);
727 void pcibios_fixup_bus(struct pci_bus *);
728 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
729 /* Architecture specific versions may override this (weak) */
730 char *pcibios_setup(char *str);
731 
732 /* Used only when drivers/pci/setup.c is used */
733 resource_size_t pcibios_align_resource(void *, const struct resource *,
734                                 resource_size_t,
735                                 resource_size_t);
736 void pcibios_update_irq(struct pci_dev *, int irq);
737 
738 /* Weak but can be overriden by arch */
739 void pci_fixup_cardbus(struct pci_bus *);
740 
741 /* Generic PCI functions used internally */
742 
743 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
744                              struct resource *res);
745 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
746                              struct pci_bus_region *region);
747 void pcibios_scan_specific_bus(int busn);
748 struct pci_bus *pci_find_bus(int domain, int busnr);
749 void pci_bus_add_devices(const struct pci_bus *bus);
750 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
751                                       struct pci_ops *ops, void *sysdata);
752 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
753 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
754                                     struct pci_ops *ops, void *sysdata,
755                                     struct list_head *resources);
756 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
757 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
758 void pci_bus_release_busn_res(struct pci_bus *b);
759 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
760                                              struct pci_ops *ops, void *sysdata,
761                                              struct list_head *resources);
762 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
763                                 int busnr);
764 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
765 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
766                                  const char *name,
767                                  struct hotplug_slot *hotplug);
768 void pci_destroy_slot(struct pci_slot *slot);
769 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
770 int pci_scan_slot(struct pci_bus *bus, int devfn);
771 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
772 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
773 unsigned int pci_scan_child_bus(struct pci_bus *bus);
774 int __must_check pci_bus_add_device(struct pci_dev *dev);
775 void pci_read_bridge_bases(struct pci_bus *child);
776 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
777                                           struct resource *res);
778 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
779 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
780 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
781 struct pci_dev *pci_dev_get(struct pci_dev *dev);
782 void pci_dev_put(struct pci_dev *dev);
783 void pci_remove_bus(struct pci_bus *b);
784 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
785 void pci_stop_root_bus(struct pci_bus *bus);
786 void pci_remove_root_bus(struct pci_bus *bus);
787 void pci_setup_cardbus(struct pci_bus *bus);
788 void pci_sort_breadthfirst(void);
789 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
790 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
791 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
792 
793 /* Generic PCI functions exported to card drivers */
794 
795 enum pci_lost_interrupt_reason {
796         PCI_LOST_IRQ_NO_INFORMATION = 0,
797         PCI_LOST_IRQ_DISABLE_MSI,
798         PCI_LOST_IRQ_DISABLE_MSIX,
799         PCI_LOST_IRQ_DISABLE_ACPI,
800 };
801 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
802 int pci_find_capability(struct pci_dev *dev, int cap);
803 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
804 int pci_find_ext_capability(struct pci_dev *dev, int cap);
805 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
806 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
807 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
808 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
809 
810 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
811                                 struct pci_dev *from);
812 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
813                                 unsigned int ss_vendor, unsigned int ss_device,
814                                 struct pci_dev *from);
815 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
816 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
817                                             unsigned int devfn);
818 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
819                                                    unsigned int devfn)
820 {
821         return pci_get_domain_bus_and_slot(0, bus, devfn);
822 }
823 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
824 int pci_dev_present(const struct pci_device_id *ids);
825 
826 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
827                              int where, u8 *val);
828 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
829                              int where, u16 *val);
830 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
831                               int where, u32 *val);
832 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
833                               int where, u8 val);
834 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
835                               int where, u16 val);
836 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
837                                int where, u32 val);
838 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
839 
840 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
841 {
842         return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
843 }
844 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
845 {
846         return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
847 }
848 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
849                                         u32 *val)
850 {
851         return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
852 }
853 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
854 {
855         return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
856 }
857 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
858 {
859         return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
860 }
861 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
862                                          u32 val)
863 {
864         return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
865 }
866 
867 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
868 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
869 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
870 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
871 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
872                                        u16 clear, u16 set);
873 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
874                                         u32 clear, u32 set);
875 
876 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
877                                            u16 set)
878 {
879         return pcie_capability_clear_and_set_word(dev, pos, 0, set);
880 }
881 
882 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
883                                             u32 set)
884 {
885         return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
886 }
887 
888 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
889                                              u16 clear)
890 {
891         return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
892 }
893 
894 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
895                                               u32 clear)
896 {
897         return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
898 }
899 
900 /* user-space driven config access */
901 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
902 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
903 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
904 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
905 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
906 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
907 
908 int __must_check pci_enable_device(struct pci_dev *dev);
909 int __must_check pci_enable_device_io(struct pci_dev *dev);
910 int __must_check pci_enable_device_mem(struct pci_dev *dev);
911 int __must_check pci_reenable_device(struct pci_dev *);
912 int __must_check pcim_enable_device(struct pci_dev *pdev);
913 void pcim_pin_device(struct pci_dev *pdev);
914 
915 static inline int pci_is_enabled(struct pci_dev *pdev)
916 {
917         return (atomic_read(&pdev->enable_cnt) > 0);
918 }
919 
920 static inline int pci_is_managed(struct pci_dev *pdev)
921 {
922         return pdev->is_managed;
923 }
924 
925 void pci_disable_device(struct pci_dev *dev);
926 
927 extern unsigned int pcibios_max_latency;
928 void pci_set_master(struct pci_dev *dev);
929 void pci_clear_master(struct pci_dev *dev);
930 
931 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
932 int pci_set_cacheline_size(struct pci_dev *dev);
933 #define HAVE_PCI_SET_MWI
934 int __must_check pci_set_mwi(struct pci_dev *dev);
935 int pci_try_set_mwi(struct pci_dev *dev);
936 void pci_clear_mwi(struct pci_dev *dev);
937 void pci_intx(struct pci_dev *dev, int enable);
938 bool pci_intx_mask_supported(struct pci_dev *dev);
939 bool pci_check_and_mask_intx(struct pci_dev *dev);
940 bool pci_check_and_unmask_intx(struct pci_dev *dev);
941 void pci_msi_off(struct pci_dev *dev);
942 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
943 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
944 int pci_wait_for_pending_transaction(struct pci_dev *dev);
945 int pcix_get_max_mmrbc(struct pci_dev *dev);
946 int pcix_get_mmrbc(struct pci_dev *dev);
947 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
948 int pcie_get_readrq(struct pci_dev *dev);
949 int pcie_set_readrq(struct pci_dev *dev, int rq);
950 int pcie_get_mps(struct pci_dev *dev);
951 int pcie_set_mps(struct pci_dev *dev, int mps);
952 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
953                           enum pcie_link_width *width);
954 int __pci_reset_function(struct pci_dev *dev);
955 int __pci_reset_function_locked(struct pci_dev *dev);
956 int pci_reset_function(struct pci_dev *dev);
957 int pci_probe_reset_slot(struct pci_slot *slot);
958 int pci_reset_slot(struct pci_slot *slot);
959 int pci_probe_reset_bus(struct pci_bus *bus);
960 int pci_reset_bus(struct pci_bus *bus);
961 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
962 void pci_update_resource(struct pci_dev *dev, int resno);
963 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
964 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
965 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
966 
967 /* ROM control related routines */
968 int pci_enable_rom(struct pci_dev *pdev);
969 void pci_disable_rom(struct pci_dev *pdev);
970 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
971 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
972 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
973 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
974 
975 /* Power management related routines */
976 int pci_save_state(struct pci_dev *dev);
977 void pci_restore_state(struct pci_dev *dev);
978 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
979 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
980 int pci_load_and_free_saved_state(struct pci_dev *dev,
981                                   struct pci_saved_state **state);
982 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
983 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
984 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
985 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
986 void pci_pme_active(struct pci_dev *dev, bool enable);
987 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
988                       bool runtime, bool enable);
989 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
990 pci_power_t pci_target_state(struct pci_dev *dev);
991 int pci_prepare_to_sleep(struct pci_dev *dev);
992 int pci_back_from_sleep(struct pci_dev *dev);
993 bool pci_dev_run_wake(struct pci_dev *dev);
994 bool pci_check_pme_status(struct pci_dev *dev);
995 void pci_pme_wakeup_bus(struct pci_bus *bus);
996 
997 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
998                                   bool enable)
999 {
1000         return __pci_enable_wake(dev, state, false, enable);
1001 }
1002 
1003 #define PCI_EXP_IDO_REQUEST     (1<<0)
1004 #define PCI_EXP_IDO_COMPLETION  (1<<1)
1005 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
1006 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
1007 
1008 enum pci_obff_signal_type {
1009         PCI_EXP_OBFF_SIGNAL_L0 = 0,
1010         PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
1011 };
1012 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
1013 void pci_disable_obff(struct pci_dev *dev);
1014 
1015 int pci_enable_ltr(struct pci_dev *dev);
1016 void pci_disable_ltr(struct pci_dev *dev);
1017 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
1018 
1019 /* For use by arch with custom probe code */
1020 void set_pcie_port_type(struct pci_dev *pdev);
1021 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1022 
1023 /* Functions for PCI Hotplug drivers to use */
1024 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1025 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1026 unsigned int pci_rescan_bus(struct pci_bus *bus);
1027 
1028 /* Vital product data routines */
1029 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1030 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1031 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
1032 
1033 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1034 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1035 void pci_bus_assign_resources(const struct pci_bus *bus);
1036 void pci_bus_size_bridges(struct pci_bus *bus);
1037 int pci_claim_resource(struct pci_dev *, int);
1038 void pci_assign_unassigned_resources(void);
1039 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1040 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1041 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1042 void pdev_enable_device(struct pci_dev *);
1043 int pci_enable_resources(struct pci_dev *, int mask);
1044 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1045                     int (*)(const struct pci_dev *, u8, u8));
1046 #define HAVE_PCI_REQ_REGIONS    2
1047 int __must_check pci_request_regions(struct pci_dev *, const char *);
1048 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1049 void pci_release_regions(struct pci_dev *);
1050 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1051 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1052 void pci_release_region(struct pci_dev *, int);
1053 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1054 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1055 void pci_release_selected_regions(struct pci_dev *, int);
1056 
1057 /* drivers/pci/bus.c */
1058 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1059 void pci_bus_put(struct pci_bus *bus);
1060 void pci_add_resource(struct list_head *resources, struct resource *res);
1061 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1062                              resource_size_t offset);
1063 void pci_free_resource_list(struct list_head *resources);
1064 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1065 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1066 void pci_bus_remove_resources(struct pci_bus *bus);
1067 
1068 #define pci_bus_for_each_resource(bus, res, i)                          \
1069         for (i = 0;                                                     \
1070             (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1071              i++)
1072 
1073 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1074                         struct resource *res, resource_size_t size,
1075                         resource_size_t align, resource_size_t min,
1076                         unsigned int type_mask,
1077                         resource_size_t (*alignf)(void *,
1078                                                   const struct resource *,
1079                                                   resource_size_t,
1080                                                   resource_size_t),
1081                         void *alignf_data);
1082 
1083 /* Proper probing supporting hot-pluggable devices */
1084 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1085                                        const char *mod_name);
1086 
1087 /*
1088  * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1089  */
1090 #define pci_register_driver(driver)             \
1091         __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1092 
1093 void pci_unregister_driver(struct pci_driver *dev);
1094 
1095 /**
1096  * module_pci_driver() - Helper macro for registering a PCI driver
1097  * @__pci_driver: pci_driver struct
1098  *
1099  * Helper macro for PCI drivers which do not do anything special in module
1100  * init/exit. This eliminates a lot of boilerplate. Each module may only
1101  * use this macro once, and calling it replaces module_init() and module_exit()
1102  */
1103 #define module_pci_driver(__pci_driver) \
1104         module_driver(__pci_driver, pci_register_driver, \
1105                        pci_unregister_driver)
1106 
1107 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1108 int pci_add_dynid(struct pci_driver *drv,
1109                   unsigned int vendor, unsigned int device,
1110                   unsigned int subvendor, unsigned int subdevice,
1111                   unsigned int class, unsigned int class_mask,
1112                   unsigned long driver_data);
1113 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1114                                          struct pci_dev *dev);
1115 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1116                     int pass);
1117 
1118 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1119                   void *userdata);
1120 int pci_cfg_space_size_ext(struct pci_dev *dev);
1121 int pci_cfg_space_size(struct pci_dev *dev);
1122 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1123 void pci_setup_bridge(struct pci_bus *bus);
1124 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1125                                          unsigned long type);
1126 
1127 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1128 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1129 
1130 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1131                       unsigned int command_bits, u32 flags);
1132 /* kmem_cache style wrapper around pci_alloc_consistent() */
1133 
1134 #include <linux/pci-dma.h>
1135 #include <linux/dmapool.h>
1136 
1137 #define pci_pool dma_pool
1138 #define pci_pool_create(name, pdev, size, align, allocation) \
1139                 dma_pool_create(name, &pdev->dev, size, align, allocation)
1140 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1141 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1142 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1143 
1144 enum pci_dma_burst_strategy {
1145         PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1146                                    strategy_parameter is N/A */
1147         PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1148                                    byte boundaries */
1149         PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1150                                    strategy_parameter byte boundaries */
1151 };
1152 
1153 struct msix_entry {
1154         u32     vector; /* kernel uses to write allocated vector */
1155         u16     entry;  /* driver uses to specify entry, OS writes */
1156 };
1157 
1158 
1159 #ifndef CONFIG_PCI_MSI
1160 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1161 {
1162         return -1;
1163 }
1164 
1165 static inline int
1166 pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
1167 {
1168         return -1;
1169 }
1170 
1171 static inline void pci_msi_shutdown(struct pci_dev *dev)
1172 { }
1173 static inline void pci_disable_msi(struct pci_dev *dev)
1174 { }
1175 
1176 static inline int pci_msix_table_size(struct pci_dev *dev)
1177 {
1178         return 0;
1179 }
1180 static inline int pci_enable_msix(struct pci_dev *dev,
1181                                   struct msix_entry *entries, int nvec)
1182 {
1183         return -1;
1184 }
1185 
1186 static inline void pci_msix_shutdown(struct pci_dev *dev)
1187 { }
1188 static inline void pci_disable_msix(struct pci_dev *dev)
1189 { }
1190 
1191 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1192 { }
1193 
1194 static inline void pci_restore_msi_state(struct pci_dev *dev)
1195 { }
1196 static inline int pci_msi_enabled(void)
1197 {
1198         return 0;
1199 }
1200 #else
1201 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1202 int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
1203 void pci_msi_shutdown(struct pci_dev *dev);
1204 void pci_disable_msi(struct pci_dev *dev);
1205 int pci_msix_table_size(struct pci_dev *dev);
1206 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1207 void pci_msix_shutdown(struct pci_dev *dev);
1208 void pci_disable_msix(struct pci_dev *dev);
1209 void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1210 void pci_restore_msi_state(struct pci_dev *dev);
1211 int pci_msi_enabled(void);
1212 #endif
1213 
1214 #ifdef CONFIG_PCIEPORTBUS
1215 extern bool pcie_ports_disabled;
1216 extern bool pcie_ports_auto;
1217 #else
1218 #define pcie_ports_disabled     true
1219 #define pcie_ports_auto         false
1220 #endif
1221 
1222 #ifndef CONFIG_PCIEASPM
1223 static inline int pcie_aspm_enabled(void) { return 0; }
1224 static inline bool pcie_aspm_support_enabled(void) { return false; }
1225 #else
1226 int pcie_aspm_enabled(void);
1227 bool pcie_aspm_support_enabled(void);
1228 #endif
1229 
1230 #ifdef CONFIG_PCIEAER
1231 void pci_no_aer(void);
1232 bool pci_aer_available(void);
1233 #else
1234 static inline void pci_no_aer(void) { }
1235 static inline bool pci_aer_available(void) { return false; }
1236 #endif
1237 
1238 #ifndef CONFIG_PCIE_ECRC
1239 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1240 {
1241         return;
1242 }
1243 static inline void pcie_ecrc_get_policy(char *str) {};
1244 #else
1245 void pcie_set_ecrc_checking(struct pci_dev *dev);
1246 void pcie_ecrc_get_policy(char *str);
1247 #endif
1248 
1249 #define pci_enable_msi(pdev)    pci_enable_msi_block(pdev, 1)
1250 
1251 #ifdef CONFIG_HT_IRQ
1252 /* The functions a driver should call */
1253 int  ht_create_irq(struct pci_dev *dev, int idx);
1254 void ht_destroy_irq(unsigned int irq);
1255 #endif /* CONFIG_HT_IRQ */
1256 
1257 void pci_cfg_access_lock(struct pci_dev *dev);
1258 bool pci_cfg_access_trylock(struct pci_dev *dev);
1259 void pci_cfg_access_unlock(struct pci_dev *dev);
1260 
1261 /*
1262  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1263  * a PCI domain is defined to be a set of PCI busses which share
1264  * configuration space.
1265  */
1266 #ifdef CONFIG_PCI_DOMAINS
1267 extern int pci_domains_supported;
1268 #else
1269 enum { pci_domains_supported = 0 };
1270 static inline int pci_domain_nr(struct pci_bus *bus)
1271 {
1272         return 0;
1273 }
1274 
1275 static inline int pci_proc_domain(struct pci_bus *bus)
1276 {
1277         return 0;
1278 }
1279 #endif /* CONFIG_PCI_DOMAINS */
1280 
1281 /* some architectures require additional setup to direct VGA traffic */
1282 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1283                       unsigned int command_bits, u32 flags);
1284 void pci_register_set_vga_state(arch_set_vga_state_t func);
1285 
1286 #else /* CONFIG_PCI is not enabled */
1287 
1288 /*
1289  *  If the system does not have PCI, clearly these return errors.  Define
1290  *  these as simple inline functions to avoid hair in drivers.
1291  */
1292 
1293 #define _PCI_NOP(o, s, t) \
1294         static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1295                                                 int where, t val) \
1296                 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1297 
1298 #define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1299                                 _PCI_NOP(o, word, u16 x) \
1300                                 _PCI_NOP(o, dword, u32 x)
1301 _PCI_NOP_ALL(read, *)
1302 _PCI_NOP_ALL(write,)
1303 
1304 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1305                                              unsigned int device,
1306                                              struct pci_dev *from)
1307 {
1308         return NULL;
1309 }
1310 
1311 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1312                                              unsigned int device,
1313                                              unsigned int ss_vendor,
1314                                              unsigned int ss_device,
1315                                              struct pci_dev *from)
1316 {
1317         return NULL;
1318 }
1319 
1320 static inline struct pci_dev *pci_get_class(unsigned int class,
1321                                             struct pci_dev *from)
1322 {
1323         return NULL;
1324 }
1325 
1326 #define pci_dev_present(ids)    (0)
1327 #define no_pci_devices()        (1)
1328 #define pci_dev_put(dev)        do { } while (0)
1329 
1330 static inline void pci_set_master(struct pci_dev *dev)
1331 { }
1332 
1333 static inline int pci_enable_device(struct pci_dev *dev)
1334 {
1335         return -EIO;
1336 }
1337 
1338 static inline void pci_disable_device(struct pci_dev *dev)
1339 { }
1340 
1341 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1342 {
1343         return -EIO;
1344 }
1345 
1346 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1347 {
1348         return -EIO;
1349 }
1350 
1351 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1352                                         unsigned int size)
1353 {
1354         return -EIO;
1355 }
1356 
1357 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1358                                         unsigned long mask)
1359 {
1360         return -EIO;
1361 }
1362 
1363 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1364 {
1365         return -EBUSY;
1366 }
1367 
1368 static inline int __pci_register_driver(struct pci_driver *drv,
1369                                         struct module *owner)
1370 {
1371         return 0;
1372 }
1373 
1374 static inline int pci_register_driver(struct pci_driver *drv)
1375 {
1376         return 0;
1377 }
1378 
1379 static inline void pci_unregister_driver(struct pci_driver *drv)
1380 { }
1381 
1382 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1383 {
1384         return 0;
1385 }
1386 
1387 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1388                                            int cap)
1389 {
1390         return 0;
1391 }
1392 
1393 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1394 {
1395         return 0;
1396 }
1397 
1398 /* Power management related routines */
1399 static inline int pci_save_state(struct pci_dev *dev)
1400 {
1401         return 0;
1402 }
1403 
1404 static inline void pci_restore_state(struct pci_dev *dev)
1405 { }
1406 
1407 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1408 {
1409         return 0;
1410 }
1411 
1412 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1413 {
1414         return 0;
1415 }
1416 
1417 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1418                                            pm_message_t state)
1419 {
1420         return PCI_D0;
1421 }
1422 
1423 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1424                                   int enable)
1425 {
1426         return 0;
1427 }
1428 
1429 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1430 {
1431 }
1432 
1433 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1434 {
1435 }
1436 
1437 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1438 {
1439         return 0;
1440 }
1441 
1442 static inline void pci_disable_obff(struct pci_dev *dev)
1443 {
1444 }
1445 
1446 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1447 {
1448         return -EIO;
1449 }
1450 
1451 static inline void pci_release_regions(struct pci_dev *dev)
1452 { }
1453 
1454 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1455 
1456 static inline void pci_block_cfg_access(struct pci_dev *dev)
1457 { }
1458 
1459 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1460 { return 0; }
1461 
1462 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1463 { }
1464 
1465 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1466 { return NULL; }
1467 
1468 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1469                                                 unsigned int devfn)
1470 { return NULL; }
1471 
1472 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1473                                                 unsigned int devfn)
1474 { return NULL; }
1475 
1476 static inline int pci_domain_nr(struct pci_bus *bus)
1477 { return 0; }
1478 
1479 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1480 { return NULL; }
1481 
1482 #define dev_is_pci(d) (false)
1483 #define dev_is_pf(d) (false)
1484 #define dev_num_vf(d) (0)
1485 #endif /* CONFIG_PCI */
1486 
1487 /* Include architecture-dependent settings and functions */
1488 
1489 #include <asm/pci.h>
1490 
1491 #ifndef PCIBIOS_MAX_MEM_32
1492 #define PCIBIOS_MAX_MEM_32 (-1)
1493 #endif
1494 
1495 /* these helpers provide future and backwards compatibility
1496  * for accessing popular PCI BAR info */
1497 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1498 #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1499 #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1500 #define pci_resource_len(dev,bar) \
1501         ((pci_resource_start((dev), (bar)) == 0 &&      \
1502           pci_resource_end((dev), (bar)) ==             \
1503           pci_resource_start((dev), (bar))) ? 0 :       \
1504                                                         \
1505          (pci_resource_end((dev), (bar)) -              \
1506           pci_resource_start((dev), (bar)) + 1))
1507 
1508 /* Similar to the helpers above, these manipulate per-pci_dev
1509  * driver-specific data.  They are really just a wrapper around
1510  * the generic device structure functions of these calls.
1511  */
1512 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1513 {
1514         return dev_get_drvdata(&pdev->dev);
1515 }
1516 
1517 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1518 {
1519         dev_set_drvdata(&pdev->dev, data);
1520 }
1521 
1522 /* If you want to know what to call your pci_dev, ask this function.
1523  * Again, it's a wrapper around the generic device.
1524  */
1525 static inline const char *pci_name(const struct pci_dev *pdev)
1526 {
1527         return dev_name(&pdev->dev);
1528 }
1529 
1530 
1531 /* Some archs don't want to expose struct resource to userland as-is
1532  * in sysfs and /proc
1533  */
1534 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1535 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1536                 const struct resource *rsrc, resource_size_t *start,
1537                 resource_size_t *end)
1538 {
1539         *start = rsrc->start;
1540         *end = rsrc->end;
1541 }
1542 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1543 
1544 
1545 /*
1546  *  The world is not perfect and supplies us with broken PCI devices.
1547  *  For at least a part of these bugs we need a work-around, so both
1548  *  generic (drivers/pci/quirks.c) and per-architecture code can define
1549  *  fixup hooks to be called for particular buggy devices.
1550  */
1551 
1552 struct pci_fixup {
1553         u16 vendor;             /* You can use PCI_ANY_ID here of course */
1554         u16 device;             /* You can use PCI_ANY_ID here of course */
1555         u32 class;              /* You can use PCI_ANY_ID here too */
1556         unsigned int class_shift;       /* should be 0, 8, 16 */
1557         void (*hook)(struct pci_dev *dev);
1558 };
1559 
1560 enum pci_fixup_pass {
1561         pci_fixup_early,        /* Before probing BARs */
1562         pci_fixup_header,       /* After reading configuration header */
1563         pci_fixup_final,        /* Final phase of device fixups */
1564         pci_fixup_enable,       /* pci_enable_device() time */
1565         pci_fixup_resume,       /* pci_device_resume() */
1566         pci_fixup_suspend,      /* pci_device_suspend */
1567         pci_fixup_resume_early, /* pci_device_resume_early() */
1568 };
1569 
1570 /* Anonymous variables would be nice... */
1571 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1572                                   class_shift, hook)                    \
1573         static const struct pci_fixup __pci_fixup_##name __used         \
1574         __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1575                 = { vendor, device, class, class_shift, hook };
1576 
1577 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1578                                          class_shift, hook)             \
1579         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1580                 vendor##device##hook, vendor, device, class, class_shift, hook)
1581 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1582                                          class_shift, hook)             \
1583         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1584                 vendor##device##hook, vendor, device, class, class_shift, hook)
1585 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1586                                          class_shift, hook)             \
1587         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1588                 vendor##device##hook, vendor, device, class, class_shift, hook)
1589 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1590                                          class_shift, hook)             \
1591         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1592                 vendor##device##hook, vendor, device, class, class_shift, hook)
1593 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1594                                          class_shift, hook)             \
1595         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1596                 resume##vendor##device##hook, vendor, device, class,    \
1597                 class_shift, hook)
1598 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1599                                          class_shift, hook)             \
1600         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1601                 resume_early##vendor##device##hook, vendor, device,     \
1602                 class, class_shift, hook)
1603 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1604                                          class_shift, hook)             \
1605         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1606                 suspend##vendor##device##hook, vendor, device, class,   \
1607                 class_shift, hook)
1608 
1609 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1610         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1611                 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1612 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1613         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1614                 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1615 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1616         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1617                 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1618 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1619         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1620                 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1621 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1622         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1623                 resume##vendor##device##hook, vendor, device,           \
1624                 PCI_ANY_ID, 0, hook)
1625 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1626         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1627                 resume_early##vendor##device##hook, vendor, device,     \
1628                 PCI_ANY_ID, 0, hook)
1629 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1630         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1631                 suspend##vendor##device##hook, vendor, device,          \
1632                 PCI_ANY_ID, 0, hook)
1633 
1634 #ifdef CONFIG_PCI_QUIRKS
1635 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1636 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1637 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1638 #else
1639 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1640                                     struct pci_dev *dev) {}
1641 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1642 {
1643         return pci_dev_get(dev);
1644 }
1645 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1646                                                u16 acs_flags)
1647 {
1648         return -ENOTTY;
1649 }
1650 #endif
1651 
1652 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1653 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1654 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1655 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1656 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1657                                    const char *name);
1658 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1659 
1660 extern int pci_pci_problems;
1661 #define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1662 #define PCIPCI_TRITON           2
1663 #define PCIPCI_NATOMA           4
1664 #define PCIPCI_VIAETBF          8
1665 #define PCIPCI_VSFX             16
1666 #define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1667 #define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1668 
1669 extern unsigned long pci_cardbus_io_size;
1670 extern unsigned long pci_cardbus_mem_size;
1671 extern u8 pci_dfl_cache_line_size;
1672 extern u8 pci_cache_line_size;
1673 
1674 extern unsigned long pci_hotplug_io_size;
1675 extern unsigned long pci_hotplug_mem_size;
1676 
1677 /* Architecture specific versions may override these (weak) */
1678 int pcibios_add_platform_entries(struct pci_dev *dev);
1679 void pcibios_disable_device(struct pci_dev *dev);
1680 void pcibios_set_master(struct pci_dev *dev);
1681 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1682                                  enum pcie_reset_state state);
1683 int pcibios_add_device(struct pci_dev *dev);
1684 void pcibios_release_device(struct pci_dev *dev);
1685 
1686 #ifdef CONFIG_HIBERNATE_CALLBACKS
1687 extern struct dev_pm_ops pcibios_pm_ops;
1688 #endif
1689 
1690 #ifdef CONFIG_PCI_MMCONFIG
1691 void __init pci_mmcfg_early_init(void);
1692 void __init pci_mmcfg_late_init(void);
1693 #else
1694 static inline void pci_mmcfg_early_init(void) { }
1695 static inline void pci_mmcfg_late_init(void) { }
1696 #endif
1697 
1698 int pci_ext_cfg_avail(void);
1699 
1700 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1701 
1702 #ifdef CONFIG_PCI_IOV
1703 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1704 void pci_disable_sriov(struct pci_dev *dev);
1705 irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1706 int pci_num_vf(struct pci_dev *dev);
1707 int pci_vfs_assigned(struct pci_dev *dev);
1708 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1709 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1710 #else
1711 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1712 {
1713         return -ENODEV;
1714 }
1715 static inline void pci_disable_sriov(struct pci_dev *dev)
1716 {
1717 }
1718 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1719 {
1720         return IRQ_NONE;
1721 }
1722 static inline int pci_num_vf(struct pci_dev *dev)
1723 {
1724         return 0;
1725 }
1726 static inline int pci_vfs_assigned(struct pci_dev *dev)
1727 {
1728         return 0;
1729 }
1730 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1731 {
1732         return 0;
1733 }
1734 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1735 {
1736         return 0;
1737 }
1738 #endif
1739 
1740 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1741 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1742 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1743 #endif
1744 
1745 /**
1746  * pci_pcie_cap - get the saved PCIe capability offset
1747  * @dev: PCI device
1748  *
1749  * PCIe capability offset is calculated at PCI device initialization
1750  * time and saved in the data structure. This function returns saved
1751  * PCIe capability offset. Using this instead of pci_find_capability()
1752  * reduces unnecessary search in the PCI configuration space. If you
1753  * need to calculate PCIe capability offset from raw device for some
1754  * reasons, please use pci_find_capability() instead.
1755  */
1756 static inline int pci_pcie_cap(struct pci_dev *dev)
1757 {
1758         return dev->pcie_cap;
1759 }
1760 
1761 /**
1762  * pci_is_pcie - check if the PCI device is PCI Express capable
1763  * @dev: PCI device
1764  *
1765  * Retrun true if the PCI device is PCI Express capable, false otherwise.
1766  */
1767 static inline bool pci_is_pcie(struct pci_dev *dev)
1768 {
1769         return !!pci_pcie_cap(dev);
1770 }
1771 
1772 /**
1773  * pcie_caps_reg - get the PCIe Capabilities Register
1774  * @dev: PCI device
1775  */
1776 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1777 {
1778         return dev->pcie_flags_reg;
1779 }
1780 
1781 /**
1782  * pci_pcie_type - get the PCIe device/port type
1783  * @dev: PCI device
1784  */
1785 static inline int pci_pcie_type(const struct pci_dev *dev)
1786 {
1787         return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1788 }
1789 
1790 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
1791 {
1792         while (1) {
1793                 if (!pci_is_pcie(dev))
1794                         break;
1795                 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1796                         return dev;
1797                 if (!dev->bus->self)
1798                         break;
1799                 dev = dev->bus->self;
1800         }
1801         return NULL;
1802 }
1803 
1804 void pci_request_acs(void);
1805 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1806 bool pci_acs_path_enabled(struct pci_dev *start,
1807                           struct pci_dev *end, u16 acs_flags);
1808 
1809 #define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
1810 #define PCI_VPD_LRDT_ID(x)              (x | PCI_VPD_LRDT)
1811 
1812 /* Large Resource Data Type Tag Item Names */
1813 #define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
1814 #define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
1815 #define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
1816 
1817 #define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1818 #define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1819 #define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1820 
1821 /* Small Resource Data Type Tag Item Names */
1822 #define PCI_VPD_STIN_END                0x78    /* End */
1823 
1824 #define PCI_VPD_SRDT_END                PCI_VPD_STIN_END
1825 
1826 #define PCI_VPD_SRDT_TIN_MASK           0x78
1827 #define PCI_VPD_SRDT_LEN_MASK           0x07
1828 
1829 #define PCI_VPD_LRDT_TAG_SIZE           3
1830 #define PCI_VPD_SRDT_TAG_SIZE           1
1831 
1832 #define PCI_VPD_INFO_FLD_HDR_SIZE       3
1833 
1834 #define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
1835 #define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
1836 #define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
1837 #define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
1838 
1839 /**
1840  * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1841  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1842  *
1843  * Returns the extracted Large Resource Data Type length.
1844  */
1845 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1846 {
1847         return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1848 }
1849 
1850 /**
1851  * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1852  * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1853  *
1854  * Returns the extracted Small Resource Data Type length.
1855  */
1856 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1857 {
1858         return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1859 }
1860 
1861 /**
1862  * pci_vpd_info_field_size - Extracts the information field length
1863  * @lrdt: Pointer to the beginning of an information field header
1864  *
1865  * Returns the extracted information field length.
1866  */
1867 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1868 {
1869         return info_field[2];
1870 }
1871 
1872 /**
1873  * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1874  * @buf: Pointer to buffered vpd data
1875  * @off: The offset into the buffer at which to begin the search
1876  * @len: The length of the vpd buffer
1877  * @rdt: The Resource Data Type to search for
1878  *
1879  * Returns the index where the Resource Data Type was found or
1880  * -ENOENT otherwise.
1881  */
1882 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1883 
1884 /**
1885  * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1886  * @buf: Pointer to buffered vpd data
1887  * @off: The offset into the buffer at which to begin the search
1888  * @len: The length of the buffer area, relative to off, in which to search
1889  * @kw: The keyword to search for
1890  *
1891  * Returns the index where the information field keyword was found or
1892  * -ENOENT otherwise.
1893  */
1894 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1895                               unsigned int len, const char *kw);
1896 
1897 /* PCI <-> OF binding helpers */
1898 #ifdef CONFIG_OF
1899 struct device_node;
1900 void pci_set_of_node(struct pci_dev *dev);
1901 void pci_release_of_node(struct pci_dev *dev);
1902 void pci_set_bus_of_node(struct pci_bus *bus);
1903 void pci_release_bus_of_node(struct pci_bus *bus);
1904 
1905 /* Arch may override this (weak) */
1906 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1907 
1908 static inline struct device_node *
1909 pci_device_to_OF_node(const struct pci_dev *pdev)
1910 {
1911         return pdev ? pdev->dev.of_node : NULL;
1912 }
1913 
1914 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1915 {
1916         return bus ? bus->dev.of_node : NULL;
1917 }
1918 
1919 #else /* CONFIG_OF */
1920 static inline void pci_set_of_node(struct pci_dev *dev) { }
1921 static inline void pci_release_of_node(struct pci_dev *dev) { }
1922 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1923 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1924 #endif  /* CONFIG_OF */
1925 
1926 #ifdef CONFIG_EEH
1927 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1928 {
1929         return pdev->dev.archdata.edev;
1930 }
1931 #endif
1932 
1933 /**
1934  * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1935  * @pdev: the PCI device
1936  *
1937  * if the device is PCIE, return NULL
1938  * if the device isn't connected to a PCIe bridge (that is its parent is a
1939  * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1940  * parent
1941  */
1942 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1943 
1944 #endif /* LINUX_PCI_H */
1945 

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