~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/sound/pci/hda/hda_intel.c

Version: ~ [ linux-5.13-rc5 ] ~ [ linux-5.12.9 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.42 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.124 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.193 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.235 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.271 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.271 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.18.140 ] ~ [ linux-3.16.85 ] ~ [ linux-3.14.79 ] ~ [ linux-3.12.74 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *
  3  *  hda_intel.c - Implementation of primary alsa driver code base
  4  *                for Intel HD Audio.
  5  *
  6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
  7  *
  8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  9  *                     PeiSen Hou <pshou@realtek.com.tw>
 10  *
 11  *  This program is free software; you can redistribute it and/or modify it
 12  *  under the terms of the GNU General Public License as published by the Free
 13  *  Software Foundation; either version 2 of the License, or (at your option)
 14  *  any later version.
 15  *
 16  *  This program is distributed in the hope that it will be useful, but WITHOUT
 17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 19  *  more details.
 20  *
 21  *  You should have received a copy of the GNU General Public License along with
 22  *  this program; if not, write to the Free Software Foundation, Inc., 59
 23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 24  *
 25  *  CONTACTS:
 26  *
 27  *  Matt Jared          matt.jared@intel.com
 28  *  Andy Kopp           andy.kopp@intel.com
 29  *  Dan Kogan           dan.d.kogan@intel.com
 30  *
 31  *  CHANGES:
 32  *
 33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
 34  * 
 35  */
 36 
 37 #include <linux/delay.h>
 38 #include <linux/interrupt.h>
 39 #include <linux/kernel.h>
 40 #include <linux/module.h>
 41 #include <linux/dma-mapping.h>
 42 #include <linux/moduleparam.h>
 43 #include <linux/init.h>
 44 #include <linux/slab.h>
 45 #include <linux/pci.h>
 46 #include <linux/mutex.h>
 47 #include <linux/reboot.h>
 48 #include <linux/io.h>
 49 #include <linux/pm_runtime.h>
 50 #include <linux/clocksource.h>
 51 #include <linux/time.h>
 52 #include <linux/completion.h>
 53 
 54 #ifdef CONFIG_X86
 55 /* for snoop control */
 56 #include <asm/pgtable.h>
 57 #include <asm/cacheflush.h>
 58 #endif
 59 #include <sound/core.h>
 60 #include <sound/initval.h>
 61 #include <linux/vgaarb.h>
 62 #include <linux/vga_switcheroo.h>
 63 #include <linux/firmware.h>
 64 #include "hda_codec.h"
 65 
 66 
 67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 70 static char *model[SNDRV_CARDS];
 71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 74 static int probe_only[SNDRV_CARDS];
 75 static int jackpoll_ms[SNDRV_CARDS];
 76 static bool single_cmd;
 77 static int enable_msi = -1;
 78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 79 static char *patch[SNDRV_CARDS];
 80 #endif
 81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 84 #endif
 85 
 86 module_param_array(index, int, NULL, 0444);
 87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 88 module_param_array(id, charp, NULL, 0444);
 89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 90 module_param_array(enable, bool, NULL, 0444);
 91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 92 module_param_array(model, charp, NULL, 0444);
 93 MODULE_PARM_DESC(model, "Use the given board model.");
 94 module_param_array(position_fix, int, NULL, 0444);
 95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 97 module_param_array(bdl_pos_adj, int, NULL, 0644);
 98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 99 module_param_array(probe_mask, int, NULL, 0444);
100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
101 module_param_array(probe_only, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
103 module_param_array(jackpoll_ms, int, NULL, 0444);
104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
105 module_param(single_cmd, bool, 0444);
106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107                  "(for debugging only).");
108 module_param(enable_msi, bint, 0444);
109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
111 module_param_array(patch, charp, NULL, 0444);
112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113 #endif
114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
115 module_param_array(beep_mode, bool, NULL, 0444);
116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
117                             "(0=off, 1=on) (default=1).");
118 #endif
119 
120 #ifdef CONFIG_PM
121 static int param_set_xint(const char *val, const struct kernel_param *kp);
122 static struct kernel_param_ops param_ops_xint = {
123         .set = param_set_xint,
124         .get = param_get_int,
125 };
126 #define param_check_xint param_check_int
127 
128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
129 module_param(power_save, xint, 0644);
130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131                  "(in second, 0 = disable).");
132 
133 /* reset the HD-audio controller in power save mode.
134  * this may give more power-saving, but will take longer time to
135  * wake up.
136  */
137 static bool power_save_controller = 1;
138 module_param(power_save_controller, bool, 0644);
139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
140 #endif /* CONFIG_PM */
141 
142 static int align_buffer_size = -1;
143 module_param(align_buffer_size, bint, 0644);
144 MODULE_PARM_DESC(align_buffer_size,
145                 "Force buffer and period sizes to be multiple of 128 bytes.");
146 
147 #ifdef CONFIG_X86
148 static bool hda_snoop = true;
149 module_param_named(snoop, hda_snoop, bool, 0444);
150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151 #define azx_snoop(chip)         (chip)->snoop
152 #else
153 #define hda_snoop               true
154 #define azx_snoop(chip)         true
155 #endif
156 
157 
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160                          "{Intel, ICH6M},"
161                          "{Intel, ICH7},"
162                          "{Intel, ESB2},"
163                          "{Intel, ICH8},"
164                          "{Intel, ICH9},"
165                          "{Intel, ICH10},"
166                          "{Intel, PCH},"
167                          "{Intel, CPT},"
168                          "{Intel, PPT},"
169                          "{Intel, LPT},"
170                          "{Intel, LPT_LP},"
171                          "{Intel, HPT},"
172                          "{Intel, PBG},"
173                          "{Intel, SCH},"
174                          "{ATI, SB450},"
175                          "{ATI, SB600},"
176                          "{ATI, RS600},"
177                          "{ATI, RS690},"
178                          "{ATI, RS780},"
179                          "{ATI, R600},"
180                          "{ATI, RV630},"
181                          "{ATI, RV610},"
182                          "{ATI, RV670},"
183                          "{ATI, RV635},"
184                          "{ATI, RV620},"
185                          "{ATI, RV770},"
186                          "{VIA, VT8251},"
187                          "{VIA, VT8237A},"
188                          "{SiS, SIS966},"
189                          "{ULI, M5461}}");
190 MODULE_DESCRIPTION("Intel HDA driver");
191 
192 #ifdef CONFIG_SND_VERBOSE_PRINTK
193 #define SFX     /* nop */
194 #else
195 #define SFX     "hda-intel "
196 #endif
197 
198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
200 #define SUPPORT_VGA_SWITCHEROO
201 #endif
202 #endif
203 
204 
205 /*
206  * registers
207  */
208 #define ICH6_REG_GCAP                   0x00
209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
214 #define ICH6_REG_VMIN                   0x02
215 #define ICH6_REG_VMAJ                   0x03
216 #define ICH6_REG_OUTPAY                 0x04
217 #define ICH6_REG_INPAY                  0x06
218 #define ICH6_REG_GCTL                   0x08
219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
222 #define ICH6_REG_WAKEEN                 0x0c
223 #define ICH6_REG_STATESTS               0x0e
224 #define ICH6_REG_GSTS                   0x10
225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
226 #define ICH6_REG_INTCTL                 0x20
227 #define ICH6_REG_INTSTS                 0x24
228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
230 #define ICH6_REG_SSYNC                  0x38
231 #define ICH6_REG_CORBLBASE              0x40
232 #define ICH6_REG_CORBUBASE              0x44
233 #define ICH6_REG_CORBWP                 0x48
234 #define ICH6_REG_CORBRP                 0x4a
235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
236 #define ICH6_REG_CORBCTL                0x4c
237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
239 #define ICH6_REG_CORBSTS                0x4d
240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
241 #define ICH6_REG_CORBSIZE               0x4e
242 
243 #define ICH6_REG_RIRBLBASE              0x50
244 #define ICH6_REG_RIRBUBASE              0x54
245 #define ICH6_REG_RIRBWP                 0x58
246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
247 #define ICH6_REG_RINTCNT                0x5a
248 #define ICH6_REG_RIRBCTL                0x5c
249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
252 #define ICH6_REG_RIRBSTS                0x5d
253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
255 #define ICH6_REG_RIRBSIZE               0x5e
256 
257 #define ICH6_REG_IC                     0x60
258 #define ICH6_REG_IR                     0x64
259 #define ICH6_REG_IRS                    0x68
260 #define   ICH6_IRS_VALID        (1<<1)
261 #define   ICH6_IRS_BUSY         (1<<0)
262 
263 #define ICH6_REG_DPLBASE                0x70
264 #define ICH6_REG_DPUBASE                0x74
265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
266 
267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269 
270 /* stream register offsets from stream base */
271 #define ICH6_REG_SD_CTL                 0x00
272 #define ICH6_REG_SD_STS                 0x03
273 #define ICH6_REG_SD_LPIB                0x04
274 #define ICH6_REG_SD_CBL                 0x08
275 #define ICH6_REG_SD_LVI                 0x0c
276 #define ICH6_REG_SD_FIFOW               0x0e
277 #define ICH6_REG_SD_FIFOSIZE            0x10
278 #define ICH6_REG_SD_FORMAT              0x12
279 #define ICH6_REG_SD_BDLPL               0x18
280 #define ICH6_REG_SD_BDLPU               0x1c
281 
282 /* PCI space */
283 #define ICH6_PCIREG_TCSEL       0x44
284 
285 /*
286  * other constants
287  */
288 
289 /* max number of SDs */
290 /* ICH, ATI and VIA have 4 playback and 4 capture */
291 #define ICH6_NUM_CAPTURE        4
292 #define ICH6_NUM_PLAYBACK       4
293 
294 /* ULI has 6 playback and 5 capture */
295 #define ULI_NUM_CAPTURE         5
296 #define ULI_NUM_PLAYBACK        6
297 
298 /* ATI HDMI has 1 playback and 0 capture */
299 #define ATIHDMI_NUM_CAPTURE     0
300 #define ATIHDMI_NUM_PLAYBACK    1
301 
302 /* TERA has 4 playback and 3 capture */
303 #define TERA_NUM_CAPTURE        3
304 #define TERA_NUM_PLAYBACK       4
305 
306 /* this number is statically defined for simplicity */
307 #define MAX_AZX_DEV             16
308 
309 /* max number of fragments - we may use more if allocating more pages for BDL */
310 #define BDL_SIZE                4096
311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
312 #define AZX_MAX_FRAG            32
313 /* max buffer size - no h/w limit, you can increase as you like */
314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
315 
316 /* RIRB int mask: overrun[2], response[0] */
317 #define RIRB_INT_RESPONSE       0x01
318 #define RIRB_INT_OVERRUN        0x04
319 #define RIRB_INT_MASK           0x05
320 
321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
322 #define AZX_MAX_CODECS          8
323 #define AZX_DEFAULT_CODECS      4
324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
325 
326 /* SD_CTL bits */
327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
333 #define SD_CTL_STREAM_TAG_SHIFT 20
334 
335 /* SD_CTL and SD_STS */
336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340                                  SD_INT_COMPLETE)
341 
342 /* SD_STS */
343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
344 
345 /* INTCTL and INTSTS */
346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
349 
350 /* below are so far hardcoded - should read registers in future */
351 #define ICH6_MAX_CORB_ENTRIES   256
352 #define ICH6_MAX_RIRB_ENTRIES   256
353 
354 /* position fix mode */
355 enum {
356         POS_FIX_AUTO,
357         POS_FIX_LPIB,
358         POS_FIX_POSBUF,
359         POS_FIX_VIACOMBO,
360         POS_FIX_COMBO,
361 };
362 
363 /* Defines for ATI HD Audio support in SB450 south bridge */
364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
366 
367 /* Defines for Nvidia HDA support */
368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
370 #define NVIDIA_HDA_ISTRM_COH          0x4d
371 #define NVIDIA_HDA_OSTRM_COH          0x4c
372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
373 
374 /* Defines for Intel SCH HDA snoop control */
375 #define INTEL_SCH_HDA_DEVC      0x78
376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
377 
378 /* Define IN stream 0 FIFO size offset in VIA controller */
379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380 /* Define VIA HD Audio Device ID*/
381 #define VIA_HDAC_DEVICE_ID              0x3288
382 
383 /* HD Audio class code */
384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
385 
386 /*
387  */
388 
389 struct azx_dev {
390         struct snd_dma_buffer bdl; /* BDL buffer */
391         u32 *posbuf;            /* position buffer pointer */
392 
393         unsigned int bufsize;   /* size of the play buffer in bytes */
394         unsigned int period_bytes; /* size of the period in bytes */
395         unsigned int frags;     /* number for period in the play buffer */
396         unsigned int fifo_size; /* FIFO size */
397         unsigned long start_wallclk;    /* start + minimum wallclk */
398         unsigned long period_wallclk;   /* wallclk for period */
399 
400         void __iomem *sd_addr;  /* stream descriptor pointer */
401 
402         u32 sd_int_sta_mask;    /* stream int status mask */
403 
404         /* pcm support */
405         struct snd_pcm_substream *substream;    /* assigned substream,
406                                                  * set in PCM open
407                                                  */
408         unsigned int format_val;        /* format value to be set in the
409                                          * controller and the codec
410                                          */
411         unsigned char stream_tag;       /* assigned stream */
412         unsigned char index;            /* stream index */
413         int assigned_key;               /* last device# key assigned to */
414 
415         unsigned int opened :1;
416         unsigned int running :1;
417         unsigned int irq_pending :1;
418         unsigned int prepared:1;
419         unsigned int locked:1;
420         /*
421          * For VIA:
422          *  A flag to ensure DMA position is 0
423          *  when link position is not greater than FIFO size
424          */
425         unsigned int insufficient :1;
426         unsigned int wc_marked:1;
427         unsigned int no_period_wakeup:1;
428 
429         struct timecounter  azx_tc;
430         struct cyclecounter azx_cc;
431 
432 #ifdef CONFIG_SND_HDA_DSP_LOADER
433         struct mutex dsp_mutex;
434 #endif
435 };
436 
437 /* DSP lock helpers */
438 #ifdef CONFIG_SND_HDA_DSP_LOADER
439 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
440 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
441 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
442 #define dsp_is_locked(dev)      ((dev)->locked)
443 #else
444 #define dsp_lock_init(dev)      do {} while (0)
445 #define dsp_lock(dev)           do {} while (0)
446 #define dsp_unlock(dev)         do {} while (0)
447 #define dsp_is_locked(dev)      0
448 #endif
449 
450 /* CORB/RIRB */
451 struct azx_rb {
452         u32 *buf;               /* CORB/RIRB buffer
453                                  * Each CORB entry is 4byte, RIRB is 8byte
454                                  */
455         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
456         /* for RIRB */
457         unsigned short rp, wp;  /* read/write pointers */
458         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
459         u32 res[AZX_MAX_CODECS];        /* last read value */
460 };
461 
462 struct azx_pcm {
463         struct azx *chip;
464         struct snd_pcm *pcm;
465         struct hda_codec *codec;
466         struct hda_pcm_stream *hinfo[2];
467         struct list_head list;
468 };
469 
470 struct azx {
471         struct snd_card *card;
472         struct pci_dev *pci;
473         int dev_index;
474 
475         /* chip type specific */
476         int driver_type;
477         unsigned int driver_caps;
478         int playback_streams;
479         int playback_index_offset;
480         int capture_streams;
481         int capture_index_offset;
482         int num_streams;
483 
484         /* pci resources */
485         unsigned long addr;
486         void __iomem *remap_addr;
487         int irq;
488 
489         /* locks */
490         spinlock_t reg_lock;
491         struct mutex open_mutex;
492         struct completion probe_wait;
493 
494         /* streams (x num_streams) */
495         struct azx_dev *azx_dev;
496 
497         /* PCM */
498         struct list_head pcm_list; /* azx_pcm list */
499 
500         /* HD codec */
501         unsigned short codec_mask;
502         int  codec_probe_mask; /* copied from probe_mask option */
503         struct hda_bus *bus;
504         unsigned int beep_mode;
505 
506         /* CORB/RIRB */
507         struct azx_rb corb;
508         struct azx_rb rirb;
509 
510         /* CORB/RIRB and position buffers */
511         struct snd_dma_buffer rb;
512         struct snd_dma_buffer posbuf;
513 
514 #ifdef CONFIG_SND_HDA_PATCH_LOADER
515         const struct firmware *fw;
516 #endif
517 
518         /* flags */
519         int position_fix[2]; /* for both playback/capture streams */
520         int poll_count;
521         unsigned int running :1;
522         unsigned int initialized :1;
523         unsigned int single_cmd :1;
524         unsigned int polling_mode :1;
525         unsigned int msi :1;
526         unsigned int irq_pending_warned :1;
527         unsigned int probing :1; /* codec probing phase */
528         unsigned int snoop:1;
529         unsigned int align_buffer_size:1;
530         unsigned int region_requested:1;
531 
532         /* VGA-switcheroo setup */
533         unsigned int use_vga_switcheroo:1;
534         unsigned int vga_switcheroo_registered:1;
535         unsigned int init_failed:1; /* delayed init failed */
536         unsigned int disabled:1; /* disabled by VGA-switcher */
537 
538         /* for debugging */
539         unsigned int last_cmd[AZX_MAX_CODECS];
540 
541         /* for pending irqs */
542         struct work_struct irq_pending_work;
543 
544         /* reboot notifier (for mysterious hangup problem at power-down) */
545         struct notifier_block reboot_notifier;
546 
547         /* card list (for power_save trigger) */
548         struct list_head list;
549 
550 #ifdef CONFIG_SND_HDA_DSP_LOADER
551         struct azx_dev saved_azx_dev;
552 #endif
553 };
554 
555 #define CREATE_TRACE_POINTS
556 #include "hda_intel_trace.h"
557 
558 /* driver types */
559 enum {
560         AZX_DRIVER_ICH,
561         AZX_DRIVER_PCH,
562         AZX_DRIVER_SCH,
563         AZX_DRIVER_ATI,
564         AZX_DRIVER_ATIHDMI,
565         AZX_DRIVER_ATIHDMI_NS,
566         AZX_DRIVER_VIA,
567         AZX_DRIVER_SIS,
568         AZX_DRIVER_ULI,
569         AZX_DRIVER_NVIDIA,
570         AZX_DRIVER_TERA,
571         AZX_DRIVER_CTX,
572         AZX_DRIVER_CTHDA,
573         AZX_DRIVER_GENERIC,
574         AZX_NUM_DRIVERS, /* keep this as last entry */
575 };
576 
577 /* driver quirks (capabilities) */
578 /* bits 0-7 are used for indicating driver type */
579 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
580 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
581 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
582 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
583 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
584 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
585 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
586 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
587 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
588 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
589 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
590 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
591 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
592 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
593 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
594 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
595 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
596 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
597 
598 /* quirks for Intel PCH */
599 #define AZX_DCAPS_INTEL_PCH_NOPM \
600         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
601          AZX_DCAPS_COUNT_LPIB_DELAY)
602 
603 #define AZX_DCAPS_INTEL_PCH \
604         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
605 
606 /* quirks for ATI SB / AMD Hudson */
607 #define AZX_DCAPS_PRESET_ATI_SB \
608         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
609          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
610 
611 /* quirks for ATI/AMD HDMI */
612 #define AZX_DCAPS_PRESET_ATI_HDMI \
613         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
614 
615 /* quirks for Nvidia */
616 #define AZX_DCAPS_PRESET_NVIDIA \
617         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
618          AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
619 
620 #define AZX_DCAPS_PRESET_CTHDA \
621         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
622 
623 /*
624  * VGA-switcher support
625  */
626 #ifdef SUPPORT_VGA_SWITCHEROO
627 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
628 #else
629 #define use_vga_switcheroo(chip)        0
630 #endif
631 
632 static char *driver_short_names[] = {
633         [AZX_DRIVER_ICH] = "HDA Intel",
634         [AZX_DRIVER_PCH] = "HDA Intel PCH",
635         [AZX_DRIVER_SCH] = "HDA Intel MID",
636         [AZX_DRIVER_ATI] = "HDA ATI SB",
637         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
638         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
639         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
640         [AZX_DRIVER_SIS] = "HDA SIS966",
641         [AZX_DRIVER_ULI] = "HDA ULI M5461",
642         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
643         [AZX_DRIVER_TERA] = "HDA Teradici", 
644         [AZX_DRIVER_CTX] = "HDA Creative", 
645         [AZX_DRIVER_CTHDA] = "HDA Creative",
646         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
647 };
648 
649 /*
650  * macros for easy use
651  */
652 #define azx_writel(chip,reg,value) \
653         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
654 #define azx_readl(chip,reg) \
655         readl((chip)->remap_addr + ICH6_REG_##reg)
656 #define azx_writew(chip,reg,value) \
657         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
658 #define azx_readw(chip,reg) \
659         readw((chip)->remap_addr + ICH6_REG_##reg)
660 #define azx_writeb(chip,reg,value) \
661         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
662 #define azx_readb(chip,reg) \
663         readb((chip)->remap_addr + ICH6_REG_##reg)
664 
665 #define azx_sd_writel(dev,reg,value) \
666         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
667 #define azx_sd_readl(dev,reg) \
668         readl((dev)->sd_addr + ICH6_REG_##reg)
669 #define azx_sd_writew(dev,reg,value) \
670         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
671 #define azx_sd_readw(dev,reg) \
672         readw((dev)->sd_addr + ICH6_REG_##reg)
673 #define azx_sd_writeb(dev,reg,value) \
674         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
675 #define azx_sd_readb(dev,reg) \
676         readb((dev)->sd_addr + ICH6_REG_##reg)
677 
678 /* for pcm support */
679 #define get_azx_dev(substream) (substream->runtime->private_data)
680 
681 #ifdef CONFIG_X86
682 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
683 {
684         int pages;
685 
686         if (azx_snoop(chip))
687                 return;
688         if (!dmab || !dmab->area || !dmab->bytes)
689                 return;
690 
691 #ifdef CONFIG_SND_DMA_SGBUF
692         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
693                 struct snd_sg_buf *sgbuf = dmab->private_data;
694                 if (on)
695                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
696                 else
697                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
698                 return;
699         }
700 #endif
701 
702         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
703         if (on)
704                 set_memory_wc((unsigned long)dmab->area, pages);
705         else
706                 set_memory_wb((unsigned long)dmab->area, pages);
707 }
708 
709 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
710                                  bool on)
711 {
712         __mark_pages_wc(chip, buf, on);
713 }
714 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
715                                    struct snd_pcm_substream *substream, bool on)
716 {
717         if (azx_dev->wc_marked != on) {
718                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
719                 azx_dev->wc_marked = on;
720         }
721 }
722 #else
723 /* NOP for other archs */
724 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
725                                  bool on)
726 {
727 }
728 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
729                                    struct snd_pcm_substream *substream, bool on)
730 {
731 }
732 #endif
733 
734 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
735 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
736 /*
737  * Interface for HD codec
738  */
739 
740 /*
741  * CORB / RIRB interface
742  */
743 static int azx_alloc_cmd_io(struct azx *chip)
744 {
745         int err;
746 
747         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
748         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
749                                   snd_dma_pci_data(chip->pci),
750                                   PAGE_SIZE, &chip->rb);
751         if (err < 0) {
752                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
753                 return err;
754         }
755         mark_pages_wc(chip, &chip->rb, true);
756         return 0;
757 }
758 
759 static void azx_init_cmd_io(struct azx *chip)
760 {
761         spin_lock_irq(&chip->reg_lock);
762         /* CORB set up */
763         chip->corb.addr = chip->rb.addr;
764         chip->corb.buf = (u32 *)chip->rb.area;
765         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
767 
768         /* set the corb size to 256 entries (ULI requires explicitly) */
769         azx_writeb(chip, CORBSIZE, 0x02);
770         /* set the corb write pointer to 0 */
771         azx_writew(chip, CORBWP, 0);
772         /* reset the corb hw read pointer */
773         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
774         /* enable corb dma */
775         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
776 
777         /* RIRB set up */
778         chip->rirb.addr = chip->rb.addr + 2048;
779         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
780         chip->rirb.wp = chip->rirb.rp = 0;
781         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
782         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
783         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
784 
785         /* set the rirb size to 256 entries (ULI requires explicitly) */
786         azx_writeb(chip, RIRBSIZE, 0x02);
787         /* reset the rirb hw write pointer */
788         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
789         /* set N=1, get RIRB response interrupt for new entry */
790         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
791                 azx_writew(chip, RINTCNT, 0xc0);
792         else
793                 azx_writew(chip, RINTCNT, 1);
794         /* enable rirb dma and response irq */
795         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
796         spin_unlock_irq(&chip->reg_lock);
797 }
798 
799 static void azx_free_cmd_io(struct azx *chip)
800 {
801         spin_lock_irq(&chip->reg_lock);
802         /* disable ringbuffer DMAs */
803         azx_writeb(chip, RIRBCTL, 0);
804         azx_writeb(chip, CORBCTL, 0);
805         spin_unlock_irq(&chip->reg_lock);
806 }
807 
808 static unsigned int azx_command_addr(u32 cmd)
809 {
810         unsigned int addr = cmd >> 28;
811 
812         if (addr >= AZX_MAX_CODECS) {
813                 snd_BUG();
814                 addr = 0;
815         }
816 
817         return addr;
818 }
819 
820 static unsigned int azx_response_addr(u32 res)
821 {
822         unsigned int addr = res & 0xf;
823 
824         if (addr >= AZX_MAX_CODECS) {
825                 snd_BUG();
826                 addr = 0;
827         }
828 
829         return addr;
830 }
831 
832 /* send a command */
833 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
834 {
835         struct azx *chip = bus->private_data;
836         unsigned int addr = azx_command_addr(val);
837         unsigned int wp, rp;
838 
839         spin_lock_irq(&chip->reg_lock);
840 
841         /* add command to corb */
842         wp = azx_readw(chip, CORBWP);
843         if (wp == 0xffff) {
844                 /* something wrong, controller likely turned to D3 */
845                 spin_unlock_irq(&chip->reg_lock);
846                 return -EIO;
847         }
848         wp++;
849         wp %= ICH6_MAX_CORB_ENTRIES;
850 
851         rp = azx_readw(chip, CORBRP);
852         if (wp == rp) {
853                 /* oops, it's full */
854                 spin_unlock_irq(&chip->reg_lock);
855                 return -EAGAIN;
856         }
857 
858         chip->rirb.cmds[addr]++;
859         chip->corb.buf[wp] = cpu_to_le32(val);
860         azx_writel(chip, CORBWP, wp);
861 
862         spin_unlock_irq(&chip->reg_lock);
863 
864         return 0;
865 }
866 
867 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
868 
869 /* retrieve RIRB entry - called from interrupt handler */
870 static void azx_update_rirb(struct azx *chip)
871 {
872         unsigned int rp, wp;
873         unsigned int addr;
874         u32 res, res_ex;
875 
876         wp = azx_readw(chip, RIRBWP);
877         if (wp == 0xffff) {
878                 /* something wrong, controller likely turned to D3 */
879                 return;
880         }
881 
882         if (wp == chip->rirb.wp)
883                 return;
884         chip->rirb.wp = wp;
885 
886         while (chip->rirb.rp != wp) {
887                 chip->rirb.rp++;
888                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
889 
890                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
891                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
892                 res = le32_to_cpu(chip->rirb.buf[rp]);
893                 addr = azx_response_addr(res_ex);
894                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
895                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
896                 else if (chip->rirb.cmds[addr]) {
897                         chip->rirb.res[addr] = res;
898                         smp_wmb();
899                         chip->rirb.cmds[addr]--;
900                 } else
901                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
902                                    "last cmd=%#08x\n",
903                                    pci_name(chip->pci),
904                                    res, res_ex,
905                                    chip->last_cmd[addr]);
906         }
907 }
908 
909 /* receive a response */
910 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
911                                           unsigned int addr)
912 {
913         struct azx *chip = bus->private_data;
914         unsigned long timeout;
915         unsigned long loopcounter;
916         int do_poll = 0;
917 
918  again:
919         timeout = jiffies + msecs_to_jiffies(1000);
920 
921         for (loopcounter = 0;; loopcounter++) {
922                 if (chip->polling_mode || do_poll) {
923                         spin_lock_irq(&chip->reg_lock);
924                         azx_update_rirb(chip);
925                         spin_unlock_irq(&chip->reg_lock);
926                 }
927                 if (!chip->rirb.cmds[addr]) {
928                         smp_rmb();
929                         bus->rirb_error = 0;
930 
931                         if (!do_poll)
932                                 chip->poll_count = 0;
933                         return chip->rirb.res[addr]; /* the last value */
934                 }
935                 if (time_after(jiffies, timeout))
936                         break;
937                 if (bus->needs_damn_long_delay || loopcounter > 3000)
938                         msleep(2); /* temporary workaround */
939                 else {
940                         udelay(10);
941                         cond_resched();
942                 }
943         }
944 
945         if (!chip->polling_mode && chip->poll_count < 2) {
946                 snd_printdd(SFX "%s: azx_get_response timeout, "
947                            "polling the codec once: last cmd=0x%08x\n",
948                            pci_name(chip->pci), chip->last_cmd[addr]);
949                 do_poll = 1;
950                 chip->poll_count++;
951                 goto again;
952         }
953 
954 
955         if (!chip->polling_mode) {
956                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
957                            "switching to polling mode: last cmd=0x%08x\n",
958                            pci_name(chip->pci), chip->last_cmd[addr]);
959                 chip->polling_mode = 1;
960                 goto again;
961         }
962 
963         if (chip->msi) {
964                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
965                            "disabling MSI: last cmd=0x%08x\n",
966                            pci_name(chip->pci), chip->last_cmd[addr]);
967                 free_irq(chip->irq, chip);
968                 chip->irq = -1;
969                 pci_disable_msi(chip->pci);
970                 chip->msi = 0;
971                 if (azx_acquire_irq(chip, 1) < 0) {
972                         bus->rirb_error = 1;
973                         return -1;
974                 }
975                 goto again;
976         }
977 
978         if (chip->probing) {
979                 /* If this critical timeout happens during the codec probing
980                  * phase, this is likely an access to a non-existing codec
981                  * slot.  Better to return an error and reset the system.
982                  */
983                 return -1;
984         }
985 
986         /* a fatal communication error; need either to reset or to fallback
987          * to the single_cmd mode
988          */
989         bus->rirb_error = 1;
990         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
991                 bus->response_reset = 1;
992                 return -1; /* give a chance to retry */
993         }
994 
995         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
996                    "switching to single_cmd mode: last cmd=0x%08x\n",
997                    chip->last_cmd[addr]);
998         chip->single_cmd = 1;
999         bus->response_reset = 0;
1000         /* release CORB/RIRB */
1001         azx_free_cmd_io(chip);
1002         /* disable unsolicited responses */
1003         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1004         return -1;
1005 }
1006 
1007 /*
1008  * Use the single immediate command instead of CORB/RIRB for simplicity
1009  *
1010  * Note: according to Intel, this is not preferred use.  The command was
1011  *       intended for the BIOS only, and may get confused with unsolicited
1012  *       responses.  So, we shouldn't use it for normal operation from the
1013  *       driver.
1014  *       I left the codes, however, for debugging/testing purposes.
1015  */
1016 
1017 /* receive a response */
1018 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1019 {
1020         int timeout = 50;
1021 
1022         while (timeout--) {
1023                 /* check IRV busy bit */
1024                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1025                         /* reuse rirb.res as the response return value */
1026                         chip->rirb.res[addr] = azx_readl(chip, IR);
1027                         return 0;
1028                 }
1029                 udelay(1);
1030         }
1031         if (printk_ratelimit())
1032                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1033                            pci_name(chip->pci), azx_readw(chip, IRS));
1034         chip->rirb.res[addr] = -1;
1035         return -EIO;
1036 }
1037 
1038 /* send a command */
1039 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1040 {
1041         struct azx *chip = bus->private_data;
1042         unsigned int addr = azx_command_addr(val);
1043         int timeout = 50;
1044 
1045         bus->rirb_error = 0;
1046         while (timeout--) {
1047                 /* check ICB busy bit */
1048                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1049                         /* Clear IRV valid bit */
1050                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1051                                    ICH6_IRS_VALID);
1052                         azx_writel(chip, IC, val);
1053                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1054                                    ICH6_IRS_BUSY);
1055                         return azx_single_wait_for_response(chip, addr);
1056                 }
1057                 udelay(1);
1058         }
1059         if (printk_ratelimit())
1060                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1061                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1062         return -EIO;
1063 }
1064 
1065 /* receive a response */
1066 static unsigned int azx_single_get_response(struct hda_bus *bus,
1067                                             unsigned int addr)
1068 {
1069         struct azx *chip = bus->private_data;
1070         return chip->rirb.res[addr];
1071 }
1072 
1073 /*
1074  * The below are the main callbacks from hda_codec.
1075  *
1076  * They are just the skeleton to call sub-callbacks according to the
1077  * current setting of chip->single_cmd.
1078  */
1079 
1080 /* send a command */
1081 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1082 {
1083         struct azx *chip = bus->private_data;
1084 
1085         if (chip->disabled)
1086                 return 0;
1087         chip->last_cmd[azx_command_addr(val)] = val;
1088         if (chip->single_cmd)
1089                 return azx_single_send_cmd(bus, val);
1090         else
1091                 return azx_corb_send_cmd(bus, val);
1092 }
1093 
1094 /* get a response */
1095 static unsigned int azx_get_response(struct hda_bus *bus,
1096                                      unsigned int addr)
1097 {
1098         struct azx *chip = bus->private_data;
1099         if (chip->disabled)
1100                 return 0;
1101         if (chip->single_cmd)
1102                 return azx_single_get_response(bus, addr);
1103         else
1104                 return azx_rirb_get_response(bus, addr);
1105 }
1106 
1107 #ifdef CONFIG_PM_SLEEP
1108 /* put codec down to D3 at hibernation for Intel SKL+;
1109  * otherwise BIOS may still access the codec and screw up the driver
1110  */
1111 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
1112 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
1113 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
1114 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci))
1115 
1116 static int azx_freeze_noirq(struct device *dev)
1117 {
1118         struct pci_dev *pci = to_pci_dev(dev);
1119 
1120         if (IS_SKL_PLUS(pci))
1121                 pci_set_power_state(pci, PCI_D3hot);
1122 
1123         return 0;
1124 }
1125 
1126 static int azx_thaw_noirq(struct device *dev)
1127 {
1128         struct pci_dev *pci = to_pci_dev(dev);
1129 
1130         if (IS_SKL_PLUS(pci))
1131                 pci_set_power_state(pci, PCI_D0);
1132 
1133         return 0;
1134 }
1135 #endif /* CONFIG_PM_SLEEP */
1136 
1137 #ifdef CONFIG_PM
1138 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1139 #endif
1140 
1141 #ifdef CONFIG_SND_HDA_DSP_LOADER
1142 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1143                                 unsigned int byte_size,
1144                                 struct snd_dma_buffer *bufp);
1145 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1146 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1147                                  struct snd_dma_buffer *dmab);
1148 #endif
1149 
1150 /* reset codec link */
1151 static int azx_reset(struct azx *chip, int full_reset)
1152 {
1153         unsigned long timeout;
1154 
1155         if (!full_reset)
1156                 goto __skip;
1157 
1158         /* clear STATESTS */
1159         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1160 
1161         /* reset controller */
1162         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1163 
1164         timeout = jiffies + msecs_to_jiffies(100);
1165         while (azx_readb(chip, GCTL) &&
1166                         time_before(jiffies, timeout))
1167                 usleep_range(500, 1000);
1168 
1169         /* delay for >= 100us for codec PLL to settle per spec
1170          * Rev 0.9 section 5.5.1
1171          */
1172         usleep_range(500, 1000);
1173 
1174         /* Bring controller out of reset */
1175         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1176 
1177         timeout = jiffies + msecs_to_jiffies(100);
1178         while (!azx_readb(chip, GCTL) &&
1179                         time_before(jiffies, timeout))
1180                 usleep_range(500, 1000);
1181 
1182         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1183         usleep_range(1000, 1200);
1184 
1185       __skip:
1186         /* check to see if controller is ready */
1187         if (!azx_readb(chip, GCTL)) {
1188                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1189                 return -EBUSY;
1190         }
1191 
1192         /* Accept unsolicited responses */
1193         if (!chip->single_cmd)
1194                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1195                            ICH6_GCTL_UNSOL);
1196 
1197         /* detect codecs */
1198         if (!chip->codec_mask) {
1199                 chip->codec_mask = azx_readw(chip, STATESTS);
1200                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1201         }
1202 
1203         return 0;
1204 }
1205 
1206 
1207 /*
1208  * Lowlevel interface
1209  */  
1210 
1211 /* enable interrupts */
1212 static void azx_int_enable(struct azx *chip)
1213 {
1214         /* enable controller CIE and GIE */
1215         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1216                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1217 }
1218 
1219 /* disable interrupts */
1220 static void azx_int_disable(struct azx *chip)
1221 {
1222         int i;
1223 
1224         /* disable interrupts in stream descriptor */
1225         for (i = 0; i < chip->num_streams; i++) {
1226                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1227                 azx_sd_writeb(azx_dev, SD_CTL,
1228                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1229         }
1230 
1231         /* disable SIE for all streams */
1232         azx_writeb(chip, INTCTL, 0);
1233 
1234         /* disable controller CIE and GIE */
1235         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1236                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1237 }
1238 
1239 /* clear interrupts */
1240 static void azx_int_clear(struct azx *chip)
1241 {
1242         int i;
1243 
1244         /* clear stream status */
1245         for (i = 0; i < chip->num_streams; i++) {
1246                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1247                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1248         }
1249 
1250         /* clear STATESTS */
1251         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1252 
1253         /* clear rirb status */
1254         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1255 
1256         /* clear int status */
1257         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1258 }
1259 
1260 /* start a stream */
1261 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1262 {
1263         /*
1264          * Before stream start, initialize parameter
1265          */
1266         azx_dev->insufficient = 1;
1267 
1268         /* enable SIE */
1269         azx_writel(chip, INTCTL,
1270                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1271         /* set DMA start and interrupt mask */
1272         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1273                       SD_CTL_DMA_START | SD_INT_MASK);
1274 }
1275 
1276 /* stop DMA */
1277 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1278 {
1279         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1280                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1281         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1282 }
1283 
1284 /* stop a stream */
1285 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1286 {
1287         azx_stream_clear(chip, azx_dev);
1288         /* disable SIE */
1289         azx_writel(chip, INTCTL,
1290                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1291 }
1292 
1293 
1294 /*
1295  * reset and start the controller registers
1296  */
1297 static void azx_init_chip(struct azx *chip, int full_reset)
1298 {
1299         if (chip->initialized)
1300                 return;
1301 
1302         /* reset controller */
1303         azx_reset(chip, full_reset);
1304 
1305         /* initialize interrupts */
1306         azx_int_clear(chip);
1307         azx_int_enable(chip);
1308 
1309         /* initialize the codec command I/O */
1310         if (!chip->single_cmd)
1311                 azx_init_cmd_io(chip);
1312 
1313         /* program the position buffer */
1314         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1315         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1316 
1317         chip->initialized = 1;
1318 }
1319 
1320 /*
1321  * initialize the PCI registers
1322  */
1323 /* update bits in a PCI register byte */
1324 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1325                             unsigned char mask, unsigned char val)
1326 {
1327         unsigned char data;
1328 
1329         pci_read_config_byte(pci, reg, &data);
1330         data &= ~mask;
1331         data |= (val & mask);
1332         pci_write_config_byte(pci, reg, data);
1333 }
1334 
1335 static void azx_init_pci(struct azx *chip)
1336 {
1337         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1338          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1339          * Ensuring these bits are 0 clears playback static on some HD Audio
1340          * codecs.
1341          * The PCI register TCSEL is defined in the Intel manuals.
1342          */
1343         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1344                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1345                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1346         }
1347 
1348         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1349          * we need to enable snoop.
1350          */
1351         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1352                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1353                 update_pci_byte(chip->pci,
1354                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1355                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1356         }
1357 
1358         /* For NVIDIA HDA, enable snoop */
1359         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1360                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1361                 update_pci_byte(chip->pci,
1362                                 NVIDIA_HDA_TRANSREG_ADDR,
1363                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1364                 update_pci_byte(chip->pci,
1365                                 NVIDIA_HDA_ISTRM_COH,
1366                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1367                 update_pci_byte(chip->pci,
1368                                 NVIDIA_HDA_OSTRM_COH,
1369                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1370         }
1371 
1372         /* Enable SCH/PCH snoop if needed */
1373         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1374                 unsigned short snoop;
1375                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1376                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1377                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1378                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1379                         if (!azx_snoop(chip))
1380                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1381                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1382                         pci_read_config_word(chip->pci,
1383                                 INTEL_SCH_HDA_DEVC, &snoop);
1384                 }
1385                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1386                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1387                                 ? "Disabled" : "Enabled");
1388         }
1389 }
1390 
1391 
1392 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1393 
1394 /*
1395  * interrupt handler
1396  */
1397 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1398 {
1399         struct azx *chip = dev_id;
1400         struct azx_dev *azx_dev;
1401         u32 status;
1402         u8 sd_status;
1403         int i, ok;
1404 
1405 #ifdef CONFIG_PM_RUNTIME
1406         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1407                 return IRQ_NONE;
1408 #endif
1409 
1410         spin_lock(&chip->reg_lock);
1411 
1412         if (chip->disabled) {
1413                 spin_unlock(&chip->reg_lock);
1414                 return IRQ_NONE;
1415         }
1416 
1417         status = azx_readl(chip, INTSTS);
1418         if (status == 0) {
1419                 spin_unlock(&chip->reg_lock);
1420                 return IRQ_NONE;
1421         }
1422         
1423         for (i = 0; i < chip->num_streams; i++) {
1424                 azx_dev = &chip->azx_dev[i];
1425                 if (status & azx_dev->sd_int_sta_mask) {
1426                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1427                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1428                         if (!azx_dev->substream || !azx_dev->running ||
1429                             !(sd_status & SD_INT_COMPLETE))
1430                                 continue;
1431                         /* check whether this IRQ is really acceptable */
1432                         ok = azx_position_ok(chip, azx_dev);
1433                         if (ok == 1) {
1434                                 azx_dev->irq_pending = 0;
1435                                 spin_unlock(&chip->reg_lock);
1436                                 snd_pcm_period_elapsed(azx_dev->substream);
1437                                 spin_lock(&chip->reg_lock);
1438                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1439                                 /* bogus IRQ, process it later */
1440                                 azx_dev->irq_pending = 1;
1441                                 queue_work(chip->bus->workq,
1442                                            &chip->irq_pending_work);
1443                         }
1444                 }
1445         }
1446 
1447         /* clear rirb int */
1448         status = azx_readb(chip, RIRBSTS);
1449         if (status & RIRB_INT_MASK) {
1450                 if (status & RIRB_INT_RESPONSE) {
1451                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1452                                 udelay(80);
1453                         azx_update_rirb(chip);
1454                 }
1455                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1456         }
1457 
1458 #if 0
1459         /* clear state status int */
1460         if (azx_readb(chip, STATESTS) & 0x04)
1461                 azx_writeb(chip, STATESTS, 0x04);
1462 #endif
1463         spin_unlock(&chip->reg_lock);
1464         
1465         return IRQ_HANDLED;
1466 }
1467 
1468 
1469 /*
1470  * set up a BDL entry
1471  */
1472 static int setup_bdle(struct azx *chip,
1473                       struct snd_dma_buffer *dmab,
1474                       struct azx_dev *azx_dev, u32 **bdlp,
1475                       int ofs, int size, int with_ioc)
1476 {
1477         u32 *bdl = *bdlp;
1478 
1479         while (size > 0) {
1480                 dma_addr_t addr;
1481                 int chunk;
1482 
1483                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1484                         return -EINVAL;
1485 
1486                 addr = snd_sgbuf_get_addr(dmab, ofs);
1487                 /* program the address field of the BDL entry */
1488                 bdl[0] = cpu_to_le32((u32)addr);
1489                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1490                 /* program the size field of the BDL entry */
1491                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1492                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1493                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1494                         u32 remain = 0x1000 - (ofs & 0xfff);
1495                         if (chunk > remain)
1496                                 chunk = remain;
1497                 }
1498                 bdl[2] = cpu_to_le32(chunk);
1499                 /* program the IOC to enable interrupt
1500                  * only when the whole fragment is processed
1501                  */
1502                 size -= chunk;
1503                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1504                 bdl += 4;
1505                 azx_dev->frags++;
1506                 ofs += chunk;
1507         }
1508         *bdlp = bdl;
1509         return ofs;
1510 }
1511 
1512 /*
1513  * set up BDL entries
1514  */
1515 static int azx_setup_periods(struct azx *chip,
1516                              struct snd_pcm_substream *substream,
1517                              struct azx_dev *azx_dev)
1518 {
1519         u32 *bdl;
1520         int i, ofs, periods, period_bytes;
1521         int pos_adj;
1522 
1523         /* reset BDL address */
1524         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1525         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1526 
1527         period_bytes = azx_dev->period_bytes;
1528         periods = azx_dev->bufsize / period_bytes;
1529 
1530         /* program the initial BDL entries */
1531         bdl = (u32 *)azx_dev->bdl.area;
1532         ofs = 0;
1533         azx_dev->frags = 0;
1534         pos_adj = bdl_pos_adj[chip->dev_index];
1535         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1536                 struct snd_pcm_runtime *runtime = substream->runtime;
1537                 int pos_align = pos_adj;
1538                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1539                 if (!pos_adj)
1540                         pos_adj = pos_align;
1541                 else
1542                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1543                                 pos_align;
1544                 pos_adj = frames_to_bytes(runtime, pos_adj);
1545                 if (pos_adj >= period_bytes) {
1546                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1547                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1548                         pos_adj = 0;
1549                 } else {
1550                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1551                                          azx_dev,
1552                                          &bdl, ofs, pos_adj, true);
1553                         if (ofs < 0)
1554                                 goto error;
1555                 }
1556         } else
1557                 pos_adj = 0;
1558         for (i = 0; i < periods; i++) {
1559                 if (i == periods - 1 && pos_adj)
1560                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1561                                          azx_dev, &bdl, ofs,
1562                                          period_bytes - pos_adj, 0);
1563                 else
1564                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1565                                          azx_dev, &bdl, ofs,
1566                                          period_bytes,
1567                                          !azx_dev->no_period_wakeup);
1568                 if (ofs < 0)
1569                         goto error;
1570         }
1571         return 0;
1572 
1573  error:
1574         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1575                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1576         return -EINVAL;
1577 }
1578 
1579 /* reset stream */
1580 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1581 {
1582         unsigned char val;
1583         int timeout;
1584 
1585         azx_stream_clear(chip, azx_dev);
1586 
1587         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1588                       SD_CTL_STREAM_RESET);
1589         udelay(3);
1590         timeout = 300;
1591         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1592                --timeout)
1593                 ;
1594         val &= ~SD_CTL_STREAM_RESET;
1595         azx_sd_writeb(azx_dev, SD_CTL, val);
1596         udelay(3);
1597 
1598         timeout = 300;
1599         /* waiting for hardware to report that the stream is out of reset */
1600         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1601                --timeout)
1602                 ;
1603 
1604         /* reset first position - may not be synced with hw at this time */
1605         *azx_dev->posbuf = 0;
1606 }
1607 
1608 /*
1609  * set up the SD for streaming
1610  */
1611 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1612 {
1613         unsigned int val;
1614         /* make sure the run bit is zero for SD */
1615         azx_stream_clear(chip, azx_dev);
1616         /* program the stream_tag */
1617         val = azx_sd_readl(azx_dev, SD_CTL);
1618         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1619                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1620         if (!azx_snoop(chip))
1621                 val |= SD_CTL_TRAFFIC_PRIO;
1622         azx_sd_writel(azx_dev, SD_CTL, val);
1623 
1624         /* program the length of samples in cyclic buffer */
1625         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1626 
1627         /* program the stream format */
1628         /* this value needs to be the same as the one programmed */
1629         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1630 
1631         /* program the stream LVI (last valid index) of the BDL */
1632         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1633 
1634         /* program the BDL address */
1635         /* lower BDL address */
1636         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1637         /* upper BDL address */
1638         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1639 
1640         /* enable the position buffer */
1641         if (chip->position_fix[0] != POS_FIX_LPIB ||
1642             chip->position_fix[1] != POS_FIX_LPIB) {
1643                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1644                         azx_writel(chip, DPLBASE,
1645                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1646         }
1647 
1648         /* set the interrupt enable bits in the descriptor control register */
1649         azx_sd_writel(azx_dev, SD_CTL,
1650                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1651 
1652         return 0;
1653 }
1654 
1655 /*
1656  * Probe the given codec address
1657  */
1658 static int probe_codec(struct azx *chip, int addr)
1659 {
1660         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1661                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1662         unsigned int res;
1663 
1664         mutex_lock(&chip->bus->cmd_mutex);
1665         chip->probing = 1;
1666         azx_send_cmd(chip->bus, cmd);
1667         res = azx_get_response(chip->bus, addr);
1668         chip->probing = 0;
1669         mutex_unlock(&chip->bus->cmd_mutex);
1670         if (res == -1)
1671                 return -EIO;
1672         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1673         return 0;
1674 }
1675 
1676 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1677                                  struct hda_pcm *cpcm);
1678 static void azx_stop_chip(struct azx *chip);
1679 
1680 static void azx_bus_reset(struct hda_bus *bus)
1681 {
1682         struct azx *chip = bus->private_data;
1683 
1684         bus->in_reset = 1;
1685         azx_stop_chip(chip);
1686         azx_init_chip(chip, 1);
1687 #ifdef CONFIG_PM
1688         if (chip->initialized) {
1689                 struct azx_pcm *p;
1690                 list_for_each_entry(p, &chip->pcm_list, list)
1691                         snd_pcm_suspend_all(p->pcm);
1692                 snd_hda_suspend(chip->bus);
1693                 snd_hda_resume(chip->bus);
1694         }
1695 #endif
1696         bus->in_reset = 0;
1697 }
1698 
1699 static int get_jackpoll_interval(struct azx *chip)
1700 {
1701         int i = jackpoll_ms[chip->dev_index];
1702         unsigned int j;
1703         if (i == 0)
1704                 return 0;
1705         if (i < 50 || i > 60000)
1706                 j = 0;
1707         else
1708                 j = msecs_to_jiffies(i);
1709         if (j == 0)
1710                 snd_printk(KERN_WARNING SFX
1711                            "jackpoll_ms value out of range: %d\n", i);
1712         return j;
1713 }
1714 
1715 /*
1716  * Codec initialization
1717  */
1718 
1719 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1720 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1721         [AZX_DRIVER_NVIDIA] = 8,
1722         [AZX_DRIVER_TERA] = 1,
1723 };
1724 
1725 static int azx_codec_create(struct azx *chip, const char *model)
1726 {
1727         struct hda_bus_template bus_temp;
1728         int c, codecs, err;
1729         int max_slots;
1730 
1731         memset(&bus_temp, 0, sizeof(bus_temp));
1732         bus_temp.private_data = chip;
1733         bus_temp.modelname = model;
1734         bus_temp.pci = chip->pci;
1735         bus_temp.ops.command = azx_send_cmd;
1736         bus_temp.ops.get_response = azx_get_response;
1737         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1738         bus_temp.ops.bus_reset = azx_bus_reset;
1739 #ifdef CONFIG_PM
1740         bus_temp.power_save = &power_save;
1741         bus_temp.ops.pm_notify = azx_power_notify;
1742 #endif
1743 #ifdef CONFIG_SND_HDA_DSP_LOADER
1744         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1745         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1746         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1747 #endif
1748 
1749         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1750         if (err < 0)
1751                 return err;
1752 
1753         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1754                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1755                 chip->bus->needs_damn_long_delay = 1;
1756         }
1757 
1758         codecs = 0;
1759         max_slots = azx_max_codecs[chip->driver_type];
1760         if (!max_slots)
1761                 max_slots = AZX_DEFAULT_CODECS;
1762 
1763         /* First try to probe all given codec slots */
1764         for (c = 0; c < max_slots; c++) {
1765                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1766                         if (probe_codec(chip, c) < 0) {
1767                                 /* Some BIOSen give you wrong codec addresses
1768                                  * that don't exist
1769                                  */
1770                                 snd_printk(KERN_WARNING SFX
1771                                            "%s: Codec #%d probe error; "
1772                                            "disabling it...\n", pci_name(chip->pci), c);
1773                                 chip->codec_mask &= ~(1 << c);
1774                                 /* More badly, accessing to a non-existing
1775                                  * codec often screws up the controller chip,
1776                                  * and disturbs the further communications.
1777                                  * Thus if an error occurs during probing,
1778                                  * better to reset the controller chip to
1779                                  * get back to the sanity state.
1780                                  */
1781                                 azx_stop_chip(chip);
1782                                 azx_init_chip(chip, 1);
1783                         }
1784                 }
1785         }
1786 
1787         /* AMD chipsets often cause the communication stalls upon certain
1788          * sequence like the pin-detection.  It seems that forcing the synced
1789          * access works around the stall.  Grrr...
1790          */
1791         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1792                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1793                         pci_name(chip->pci));
1794                 chip->bus->sync_write = 1;
1795                 chip->bus->allow_bus_reset = 1;
1796         }
1797 
1798         /* Then create codec instances */
1799         for (c = 0; c < max_slots; c++) {
1800                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1801                         struct hda_codec *codec;
1802                         err = snd_hda_codec_new(chip->bus, c, &codec);
1803                         if (err < 0)
1804                                 continue;
1805                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1806                         codec->beep_mode = chip->beep_mode;
1807                         codecs++;
1808                 }
1809         }
1810         if (!codecs) {
1811                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1812                 return -ENXIO;
1813         }
1814         return 0;
1815 }
1816 
1817 /* configure each codec instance */
1818 static int azx_codec_configure(struct azx *chip)
1819 {
1820         struct hda_codec *codec;
1821         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1822                 snd_hda_codec_configure(codec);
1823         }
1824         return 0;
1825 }
1826 
1827 
1828 /*
1829  * PCM support
1830  */
1831 
1832 /* assign a stream for the PCM */
1833 static inline struct azx_dev *
1834 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1835 {
1836         int dev, i, nums;
1837         struct azx_dev *res = NULL;
1838         /* make a non-zero unique key for the substream */
1839         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1840                 (substream->stream + 1);
1841 
1842         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1843                 dev = chip->playback_index_offset;
1844                 nums = chip->playback_streams;
1845         } else {
1846                 dev = chip->capture_index_offset;
1847                 nums = chip->capture_streams;
1848         }
1849         for (i = 0; i < nums; i++, dev++) {
1850                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1851                 dsp_lock(azx_dev);
1852                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1853                         res = azx_dev;
1854                         if (res->assigned_key == key) {
1855                                 res->opened = 1;
1856                                 res->assigned_key = key;
1857                                 dsp_unlock(azx_dev);
1858                                 return azx_dev;
1859                         }
1860                 }
1861                 dsp_unlock(azx_dev);
1862         }
1863         if (res) {
1864                 dsp_lock(res);
1865                 res->opened = 1;
1866                 res->assigned_key = key;
1867                 dsp_unlock(res);
1868         }
1869         return res;
1870 }
1871 
1872 /* release the assigned stream */
1873 static inline void azx_release_device(struct azx_dev *azx_dev)
1874 {
1875         azx_dev->opened = 0;
1876 }
1877 
1878 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1879 {
1880         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1881         struct snd_pcm_substream *substream = azx_dev->substream;
1882         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1883         struct azx *chip = apcm->chip;
1884 
1885         return azx_readl(chip, WALLCLK);
1886 }
1887 
1888 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1889                                 bool force, cycle_t last)
1890 {
1891         struct azx_dev *azx_dev = get_azx_dev(substream);
1892         struct timecounter *tc = &azx_dev->azx_tc;
1893         struct cyclecounter *cc = &azx_dev->azx_cc;
1894         u64 nsec;
1895 
1896         cc->read = azx_cc_read;
1897         cc->mask = CLOCKSOURCE_MASK(32);
1898 
1899         /*
1900          * Converting from 24 MHz to ns means applying a 125/3 factor.
1901          * To avoid any saturation issues in intermediate operations,
1902          * the 125 factor is applied first. The division is applied
1903          * last after reading the timecounter value.
1904          * Applying the 1/3 factor as part of the multiplication
1905          * requires at least 20 bits for a decent precision, however
1906          * overflows occur after about 4 hours or less, not a option.
1907          */
1908 
1909         cc->mult = 125; /* saturation after 195 years */
1910         cc->shift = 0;
1911 
1912         nsec = 0; /* audio time is elapsed time since trigger */
1913         timecounter_init(tc, cc, nsec);
1914         if (force)
1915                 /*
1916                  * force timecounter to use predefined value,
1917                  * used for synchronized starts
1918                  */
1919                 tc->cycle_last = last;
1920 }
1921 
1922 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1923                                 u64 nsec)
1924 {
1925         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1926         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1927         u64 codec_frames, codec_nsecs;
1928 
1929         if (!hinfo->ops.get_delay)
1930                 return nsec;
1931 
1932         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1933         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1934                               substream->runtime->rate);
1935 
1936         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1937                 return nsec + codec_nsecs;
1938 
1939         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1940 }
1941 
1942 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1943                                 struct timespec *ts)
1944 {
1945         struct azx_dev *azx_dev = get_azx_dev(substream);
1946         u64 nsec;
1947 
1948         nsec = timecounter_read(&azx_dev->azx_tc);
1949         nsec = div_u64(nsec, 3); /* can be optimized */
1950         nsec = azx_adjust_codec_delay(substream, nsec);
1951 
1952         *ts = ns_to_timespec(nsec);
1953 
1954         return 0;
1955 }
1956 
1957 static struct snd_pcm_hardware azx_pcm_hw = {
1958         .info =                 (SNDRV_PCM_INFO_MMAP |
1959                                  SNDRV_PCM_INFO_INTERLEAVED |
1960                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1961                                  SNDRV_PCM_INFO_MMAP_VALID |
1962                                  /* No full-resume yet implemented */
1963                                  /* SNDRV_PCM_INFO_RESUME |*/
1964                                  SNDRV_PCM_INFO_PAUSE |
1965                                  SNDRV_PCM_INFO_SYNC_START |
1966                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1967                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1968         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1969         .rates =                SNDRV_PCM_RATE_48000,
1970         .rate_min =             48000,
1971         .rate_max =             48000,
1972         .channels_min =         2,
1973         .channels_max =         2,
1974         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1975         .period_bytes_min =     128,
1976         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1977         .periods_min =          2,
1978         .periods_max =          AZX_MAX_FRAG,
1979         .fifo_size =            0,
1980 };
1981 
1982 static int azx_pcm_open(struct snd_pcm_substream *substream)
1983 {
1984         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1985         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1986         struct azx *chip = apcm->chip;
1987         struct azx_dev *azx_dev;
1988         struct snd_pcm_runtime *runtime = substream->runtime;
1989         unsigned long flags;
1990         int err;
1991         int buff_step;
1992 
1993         mutex_lock(&chip->open_mutex);
1994         azx_dev = azx_assign_device(chip, substream);
1995         if (azx_dev == NULL) {
1996                 mutex_unlock(&chip->open_mutex);
1997                 return -EBUSY;
1998         }
1999         runtime->hw = azx_pcm_hw;
2000         runtime->hw.channels_min = hinfo->channels_min;
2001         runtime->hw.channels_max = hinfo->channels_max;
2002         runtime->hw.formats = hinfo->formats;
2003         runtime->hw.rates = hinfo->rates;
2004         snd_pcm_limit_hw_rates(runtime);
2005         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
2006 
2007         /* avoid wrap-around with wall-clock */
2008         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2009                                 20,
2010                                 178000000);
2011 
2012         if (chip->align_buffer_size)
2013                 /* constrain buffer sizes to be multiple of 128
2014                    bytes. This is more efficient in terms of memory
2015                    access but isn't required by the HDA spec and
2016                    prevents users from specifying exact period/buffer
2017                    sizes. For example for 44.1kHz, a period size set
2018                    to 20ms will be rounded to 19.59ms. */
2019                 buff_step = 128;
2020         else
2021                 /* Don't enforce steps on buffer sizes, still need to
2022                    be multiple of 4 bytes (HDA spec). Tested on Intel
2023                    HDA controllers, may not work on all devices where
2024                    option needs to be disabled */
2025                 buff_step = 4;
2026 
2027         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2028                                    buff_step);
2029         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2030                                    buff_step);
2031         snd_hda_power_up_d3wait(apcm->codec);
2032         err = hinfo->ops.open(hinfo, apcm->codec, substream);
2033         if (err < 0) {
2034                 azx_release_device(azx_dev);
2035                 snd_hda_power_down(apcm->codec);
2036                 mutex_unlock(&chip->open_mutex);
2037                 return err;
2038         }
2039         snd_pcm_limit_hw_rates(runtime);
2040         /* sanity check */
2041         if (snd_BUG_ON(!runtime->hw.channels_min) ||
2042             snd_BUG_ON(!runtime->hw.channels_max) ||
2043             snd_BUG_ON(!runtime->hw.formats) ||
2044             snd_BUG_ON(!runtime->hw.rates)) {
2045                 azx_release_device(azx_dev);
2046                 hinfo->ops.close(hinfo, apcm->codec, substream);
2047                 snd_hda_power_down(apcm->codec);
2048                 mutex_unlock(&chip->open_mutex);
2049                 return -EINVAL;
2050         }
2051 
2052         /* disable WALLCLOCK timestamps for capture streams
2053            until we figure out how to handle digital inputs */
2054         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2055                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2056 
2057         spin_lock_irqsave(&chip->reg_lock, flags);
2058         azx_dev->substream = substream;
2059         azx_dev->running = 0;
2060         spin_unlock_irqrestore(&chip->reg_lock, flags);
2061 
2062         runtime->private_data = azx_dev;
2063         snd_pcm_set_sync(substream);
2064         mutex_unlock(&chip->open_mutex);
2065         return 0;
2066 }
2067 
2068 static int azx_pcm_close(struct snd_pcm_substream *substream)
2069 {
2070         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2071         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2072         struct azx *chip = apcm->chip;
2073         struct azx_dev *azx_dev = get_azx_dev(substream);
2074         unsigned long flags;
2075 
2076         mutex_lock(&chip->open_mutex);
2077         spin_lock_irqsave(&chip->reg_lock, flags);
2078         azx_dev->substream = NULL;
2079         azx_dev->running = 0;
2080         spin_unlock_irqrestore(&chip->reg_lock, flags);
2081         azx_release_device(azx_dev);
2082         hinfo->ops.close(hinfo, apcm->codec, substream);
2083         snd_hda_power_down(apcm->codec);
2084         mutex_unlock(&chip->open_mutex);
2085         return 0;
2086 }
2087 
2088 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2089                              struct snd_pcm_hw_params *hw_params)
2090 {
2091         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2092         struct azx *chip = apcm->chip;
2093         struct azx_dev *azx_dev = get_azx_dev(substream);
2094         int ret;
2095 
2096         dsp_lock(azx_dev);
2097         if (dsp_is_locked(azx_dev)) {
2098                 ret = -EBUSY;
2099                 goto unlock;
2100         }
2101 
2102         mark_runtime_wc(chip, azx_dev, substream, false);
2103         azx_dev->bufsize = 0;
2104         azx_dev->period_bytes = 0;
2105         azx_dev->format_val = 0;
2106         ret = snd_pcm_lib_malloc_pages(substream,
2107                                         params_buffer_bytes(hw_params));
2108         if (ret < 0)
2109                 goto unlock;
2110         mark_runtime_wc(chip, azx_dev, substream, true);
2111  unlock:
2112         dsp_unlock(azx_dev);
2113         return ret;
2114 }
2115 
2116 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2117 {
2118         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2119         struct azx_dev *azx_dev = get_azx_dev(substream);
2120         struct azx *chip = apcm->chip;
2121         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2122 
2123         /* reset BDL address */
2124         dsp_lock(azx_dev);
2125         if (!dsp_is_locked(azx_dev)) {
2126                 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2127                 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2128                 azx_sd_writel(azx_dev, SD_CTL, 0);
2129                 azx_dev->bufsize = 0;
2130                 azx_dev->period_bytes = 0;
2131                 azx_dev->format_val = 0;
2132         }
2133 
2134         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2135 
2136         mark_runtime_wc(chip, azx_dev, substream, false);
2137         azx_dev->prepared = 0;
2138         dsp_unlock(azx_dev);
2139         return snd_pcm_lib_free_pages(substream);
2140 }
2141 
2142 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2143 {
2144         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2145         struct azx *chip = apcm->chip;
2146         struct azx_dev *azx_dev = get_azx_dev(substream);
2147         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2148         struct snd_pcm_runtime *runtime = substream->runtime;
2149         unsigned int bufsize, period_bytes, format_val, stream_tag;
2150         int err;
2151         struct hda_spdif_out *spdif =
2152                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2153         unsigned short ctls = spdif ? spdif->ctls : 0;
2154 
2155         dsp_lock(azx_dev);
2156         if (dsp_is_locked(azx_dev)) {
2157                 err = -EBUSY;
2158                 goto unlock;
2159         }
2160 
2161         azx_stream_reset(chip, azx_dev);
2162         format_val = snd_hda_calc_stream_format(runtime->rate,
2163                                                 runtime->channels,
2164                                                 runtime->format,
2165                                                 hinfo->maxbps,
2166                                                 ctls);
2167         if (!format_val) {
2168                 snd_printk(KERN_ERR SFX
2169                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2170                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2171                 err = -EINVAL;
2172                 goto unlock;
2173         }
2174 
2175         bufsize = snd_pcm_lib_buffer_bytes(substream);
2176         period_bytes = snd_pcm_lib_period_bytes(substream);
2177 
2178         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2179                     pci_name(chip->pci), bufsize, format_val);
2180 
2181         if (bufsize != azx_dev->bufsize ||
2182             period_bytes != azx_dev->period_bytes ||
2183             format_val != azx_dev->format_val ||
2184             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2185                 azx_dev->bufsize = bufsize;
2186                 azx_dev->period_bytes = period_bytes;
2187                 azx_dev->format_val = format_val;
2188                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2189                 err = azx_setup_periods(chip, substream, azx_dev);
2190                 if (err < 0)
2191                         goto unlock;
2192         }
2193 
2194         /* wallclk has 24Mhz clock source */
2195         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2196                                                 runtime->rate) * 1000);
2197         azx_setup_controller(chip, azx_dev);
2198         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2199                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2200         else
2201                 azx_dev->fifo_size = 0;
2202 
2203         stream_tag = azx_dev->stream_tag;
2204         /* CA-IBG chips need the playback stream starting from 1 */
2205         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2206             stream_tag > chip->capture_streams)
2207                 stream_tag -= chip->capture_streams;
2208         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2209                                      azx_dev->format_val, substream);
2210 
2211  unlock:
2212         if (!err)
2213                 azx_dev->prepared = 1;
2214         dsp_unlock(azx_dev);
2215         return err;
2216 }
2217 
2218 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2219 {
2220         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2221         struct azx *chip = apcm->chip;
2222         struct azx_dev *azx_dev;
2223         struct snd_pcm_substream *s;
2224         int rstart = 0, start, nsync = 0, sbits = 0;
2225         int nwait, timeout;
2226 
2227         azx_dev = get_azx_dev(substream);
2228         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2229 
2230         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2231                 return -EPIPE;
2232 
2233         switch (cmd) {
2234         case SNDRV_PCM_TRIGGER_START:
2235                 rstart = 1;
2236         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2237         case SNDRV_PCM_TRIGGER_RESUME:
2238                 start = 1;
2239                 break;
2240         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2241         case SNDRV_PCM_TRIGGER_SUSPEND:
2242         case SNDRV_PCM_TRIGGER_STOP:
2243                 start = 0;
2244                 break;
2245         default:
2246                 return -EINVAL;
2247         }
2248 
2249         snd_pcm_group_for_each_entry(s, substream) {
2250                 if (s->pcm->card != substream->pcm->card)
2251                         continue;
2252                 azx_dev = get_azx_dev(s);
2253                 sbits |= 1 << azx_dev->index;
2254                 nsync++;
2255                 snd_pcm_trigger_done(s, substream);
2256         }
2257 
2258         spin_lock(&chip->reg_lock);
2259 
2260         /* first, set SYNC bits of corresponding streams */
2261         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2262                 azx_writel(chip, OLD_SSYNC,
2263                         azx_readl(chip, OLD_SSYNC) | sbits);
2264         else
2265                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2266 
2267         snd_pcm_group_for_each_entry(s, substream) {
2268                 if (s->pcm->card != substream->pcm->card)
2269                         continue;
2270                 azx_dev = get_azx_dev(s);
2271                 if (start) {
2272                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2273                         if (!rstart)
2274                                 azx_dev->start_wallclk -=
2275                                                 azx_dev->period_wallclk;
2276                         azx_stream_start(chip, azx_dev);
2277                 } else {
2278                         azx_stream_stop(chip, azx_dev);
2279                 }
2280                 azx_dev->running = start;
2281         }
2282         spin_unlock(&chip->reg_lock);
2283         if (start) {
2284                 /* wait until all FIFOs get ready */
2285                 for (timeout = 5000; timeout; timeout--) {
2286                         nwait = 0;
2287                         snd_pcm_group_for_each_entry(s, substream) {
2288                                 if (s->pcm->card != substream->pcm->card)
2289                                         continue;
2290                                 azx_dev = get_azx_dev(s);
2291                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2292                                       SD_STS_FIFO_READY))
2293                                         nwait++;
2294                         }
2295                         if (!nwait)
2296                                 break;
2297                         cpu_relax();
2298                 }
2299         } else {
2300                 /* wait until all RUN bits are cleared */
2301                 for (timeout = 5000; timeout; timeout--) {
2302                         nwait = 0;
2303                         snd_pcm_group_for_each_entry(s, substream) {
2304                                 if (s->pcm->card != substream->pcm->card)
2305                                         continue;
2306                                 azx_dev = get_azx_dev(s);
2307                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2308                                     SD_CTL_DMA_START)
2309                                         nwait++;
2310                         }
2311                         if (!nwait)
2312                                 break;
2313                         cpu_relax();
2314                 }
2315         }
2316         spin_lock(&chip->reg_lock);
2317         /* reset SYNC bits */
2318         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2319                 azx_writel(chip, OLD_SSYNC,
2320                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2321         else
2322                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2323         if (start) {
2324                 azx_timecounter_init(substream, 0, 0);
2325                 if (nsync > 1) {
2326                         cycle_t cycle_last;
2327 
2328                         /* same start cycle for master and group */
2329                         azx_dev = get_azx_dev(substream);
2330                         cycle_last = azx_dev->azx_tc.cycle_last;
2331 
2332                         snd_pcm_group_for_each_entry(s, substream) {
2333                                 if (s->pcm->card != substream->pcm->card)
2334                                         continue;
2335                                 azx_timecounter_init(s, 1, cycle_last);
2336                         }
2337                 }
2338         }
2339         spin_unlock(&chip->reg_lock);
2340         return 0;
2341 }
2342 
2343 /* get the current DMA position with correction on VIA chips */
2344 static unsigned int azx_via_get_position(struct azx *chip,
2345                                          struct azx_dev *azx_dev)
2346 {
2347         unsigned int link_pos, mini_pos, bound_pos;
2348         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2349         unsigned int fifo_size;
2350 
2351         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2352         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2353                 /* Playback, no problem using link position */
2354                 return link_pos;
2355         }
2356 
2357         /* Capture */
2358         /* For new chipset,
2359          * use mod to get the DMA position just like old chipset
2360          */
2361         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2362         mod_dma_pos %= azx_dev->period_bytes;
2363 
2364         /* azx_dev->fifo_size can't get FIFO size of in stream.
2365          * Get from base address + offset.
2366          */
2367         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2368 
2369         if (azx_dev->insufficient) {
2370                 /* Link position never gather than FIFO size */
2371                 if (link_pos <= fifo_size)
2372                         return 0;
2373 
2374                 azx_dev->insufficient = 0;
2375         }
2376 
2377         if (link_pos <= fifo_size)
2378                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2379         else
2380                 mini_pos = link_pos - fifo_size;
2381 
2382         /* Find nearest previous boudary */
2383         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2384         mod_link_pos = link_pos % azx_dev->period_bytes;
2385         if (mod_link_pos >= fifo_size)
2386                 bound_pos = link_pos - mod_link_pos;
2387         else if (mod_dma_pos >= mod_mini_pos)
2388                 bound_pos = mini_pos - mod_mini_pos;
2389         else {
2390                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2391                 if (bound_pos >= azx_dev->bufsize)
2392                         bound_pos = 0;
2393         }
2394 
2395         /* Calculate real DMA position we want */
2396         return bound_pos + mod_dma_pos;
2397 }
2398 
2399 static unsigned int azx_get_position(struct azx *chip,
2400                                      struct azx_dev *azx_dev,
2401                                      bool with_check)
2402 {
2403         struct snd_pcm_substream *substream = azx_dev->substream;
2404         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2405         unsigned int pos;
2406         int stream = substream->stream;
2407         struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2408         int delay = 0;
2409 
2410         switch (chip->position_fix[stream]) {
2411         case POS_FIX_LPIB:
2412                 /* read LPIB */
2413                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2414                 break;
2415         case POS_FIX_VIACOMBO:
2416                 pos = azx_via_get_position(chip, azx_dev);
2417                 break;
2418         default:
2419                 /* use the position buffer */
2420                 pos = le32_to_cpu(*azx_dev->posbuf);
2421                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2422                         if (!pos || pos == (u32)-1) {
2423                                 printk(KERN_WARNING
2424                                        "hda-intel: Invalid position buffer, "
2425                                        "using LPIB read method instead.\n");
2426                                 chip->position_fix[stream] = POS_FIX_LPIB;
2427                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2428                         } else
2429                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2430                 }
2431                 break;
2432         }
2433 
2434         if (pos >= azx_dev->bufsize)
2435                 pos = 0;
2436 
2437         /* calculate runtime delay from LPIB */
2438         if (substream->runtime &&
2439             chip->position_fix[stream] == POS_FIX_POSBUF &&
2440             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2441                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2442                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2443                         delay = pos - lpib_pos;
2444                 else
2445                         delay = lpib_pos - pos;
2446                 if (delay < 0)
2447                         delay += azx_dev->bufsize;
2448                 if (delay >= azx_dev->period_bytes) {
2449                         snd_printk(KERN_WARNING SFX
2450                                    "%s: Unstable LPIB (%d >= %d); "
2451                                    "disabling LPIB delay counting\n",
2452                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2453                         delay = 0;
2454                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2455                 }
2456                 delay = bytes_to_frames(substream->runtime, delay);
2457         }
2458 
2459         if (substream->runtime) {
2460                 if (hinfo->ops.get_delay)
2461                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2462                                                       substream);
2463                 substream->runtime->delay = delay;
2464         }
2465 
2466         trace_azx_get_position(chip, azx_dev, pos, delay);
2467         return pos;
2468 }
2469 
2470 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2471 {
2472         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2473         struct azx *chip = apcm->chip;
2474         struct azx_dev *azx_dev = get_azx_dev(substream);
2475         return bytes_to_frames(substream->runtime,
2476                                azx_get_position(chip, azx_dev, false));
2477 }
2478 
2479 /*
2480  * Check whether the current DMA position is acceptable for updating
2481  * periods.  Returns non-zero if it's OK.
2482  *
2483  * Many HD-audio controllers appear pretty inaccurate about
2484  * the update-IRQ timing.  The IRQ is issued before actually the
2485  * data is processed.  So, we need to process it afterwords in a
2486  * workqueue.
2487  */
2488 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2489 {
2490         u32 wallclk;
2491         unsigned int pos;
2492 
2493         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2494         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2495                 return -1;      /* bogus (too early) interrupt */
2496 
2497         pos = azx_get_position(chip, azx_dev, true);
2498 
2499         if (WARN_ONCE(!azx_dev->period_bytes,
2500                       "hda-intel: zero azx_dev->period_bytes"))
2501                 return -1; /* this shouldn't happen! */
2502         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2503             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2504                 /* NG - it's below the first next period boundary */
2505                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2506         azx_dev->start_wallclk += wallclk;
2507         return 1; /* OK, it's fine */
2508 }
2509 
2510 /*
2511  * The work for pending PCM period updates.
2512  */
2513 static void azx_irq_pending_work(struct work_struct *work)
2514 {
2515         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2516         int i, pending, ok;
2517 
2518         if (!chip->irq_pending_warned) {
2519                 printk(KERN_WARNING
2520                        "hda-intel: IRQ timing workaround is activated "
2521                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2522                        chip->card->number);
2523                 chip->irq_pending_warned = 1;
2524         }
2525 
2526         for (;;) {
2527                 pending = 0;
2528                 spin_lock_irq(&chip->reg_lock);
2529                 for (i = 0; i < chip->num_streams; i++) {
2530                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2531                         if (!azx_dev->irq_pending ||
2532                             !azx_dev->substream ||
2533                             !azx_dev->running)
2534                                 continue;
2535                         ok = azx_position_ok(chip, azx_dev);
2536                         if (ok > 0) {
2537                                 azx_dev->irq_pending = 0;
2538                                 spin_unlock(&chip->reg_lock);
2539                                 snd_pcm_period_elapsed(azx_dev->substream);
2540                                 spin_lock(&chip->reg_lock);
2541                         } else if (ok < 0) {
2542                                 pending = 0;    /* too early */
2543                         } else
2544                                 pending++;
2545                 }
2546                 spin_unlock_irq(&chip->reg_lock);
2547                 if (!pending)
2548                         return;
2549                 msleep(1);
2550         }
2551 }
2552 
2553 /* clear irq_pending flags and assure no on-going workq */
2554 static void azx_clear_irq_pending(struct azx *chip)
2555 {
2556         int i;
2557 
2558         spin_lock_irq(&chip->reg_lock);
2559         for (i = 0; i < chip->num_streams; i++)
2560                 chip->azx_dev[i].irq_pending = 0;
2561         spin_unlock_irq(&chip->reg_lock);
2562 }
2563 
2564 #ifdef CONFIG_X86
2565 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2566                         struct vm_area_struct *area)
2567 {
2568         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2569         struct azx *chip = apcm->chip;
2570         if (!azx_snoop(chip))
2571                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2572         return snd_pcm_lib_default_mmap(substream, area);
2573 }
2574 #else
2575 #define azx_pcm_mmap    NULL
2576 #endif
2577 
2578 static struct snd_pcm_ops azx_pcm_ops = {
2579         .open = azx_pcm_open,
2580         .close = azx_pcm_close,
2581         .ioctl = snd_pcm_lib_ioctl,
2582         .hw_params = azx_pcm_hw_params,
2583         .hw_free = azx_pcm_hw_free,
2584         .prepare = azx_pcm_prepare,
2585         .trigger = azx_pcm_trigger,
2586         .pointer = azx_pcm_pointer,
2587         .wall_clock =  azx_get_wallclock_tstamp,
2588         .mmap = azx_pcm_mmap,
2589         .page = snd_pcm_sgbuf_ops_page,
2590 };
2591 
2592 static void azx_pcm_free(struct snd_pcm *pcm)
2593 {
2594         struct azx_pcm *apcm = pcm->private_data;
2595         if (apcm) {
2596                 list_del(&apcm->list);
2597                 kfree(apcm);
2598         }
2599 }
2600 
2601 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2602 
2603 static int
2604 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2605                       struct hda_pcm *cpcm)
2606 {
2607         struct azx *chip = bus->private_data;
2608         struct snd_pcm *pcm;
2609         struct azx_pcm *apcm;
2610         int pcm_dev = cpcm->device;
2611         unsigned int size;
2612         int s, err;
2613 
2614         list_for_each_entry(apcm, &chip->pcm_list, list) {
2615                 if (apcm->pcm->device == pcm_dev) {
2616                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2617                                    pci_name(chip->pci), pcm_dev);
2618                         return -EBUSY;
2619                 }
2620         }
2621         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2622                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2623                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2624                           &pcm);
2625         if (err < 0)
2626                 return err;
2627         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2628         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2629         if (apcm == NULL)
2630                 return -ENOMEM;
2631         apcm->chip = chip;
2632         apcm->pcm = pcm;
2633         apcm->codec = codec;
2634         pcm->private_data = apcm;
2635         pcm->private_free = azx_pcm_free;
2636         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2637                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2638         list_add_tail(&apcm->list, &chip->pcm_list);
2639         cpcm->pcm = pcm;
2640         for (s = 0; s < 2; s++) {
2641                 apcm->hinfo[s] = &cpcm->stream[s];
2642                 if (cpcm->stream[s].substreams)
2643                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2644         }
2645         /* buffer pre-allocation */
2646         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2647         if (size > MAX_PREALLOC_SIZE)
2648                 size = MAX_PREALLOC_SIZE;
2649         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2650                                               snd_dma_pci_data(chip->pci),
2651                                               size, MAX_PREALLOC_SIZE);
2652         return 0;
2653 }
2654 
2655 /*
2656  * mixer creation - all stuff is implemented in hda module
2657  */
2658 static int azx_mixer_create(struct azx *chip)
2659 {
2660         return snd_hda_build_controls(chip->bus);
2661 }
2662 
2663 
2664 /*
2665  * initialize SD streams
2666  */
2667 static int azx_init_stream(struct azx *chip)
2668 {
2669         int i;
2670 
2671         /* initialize each stream (aka device)
2672          * assign the starting bdl address to each stream (device)
2673          * and initialize
2674          */
2675         for (i = 0; i < chip->num_streams; i++) {
2676                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2677                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2678                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2679                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2680                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2681                 azx_dev->sd_int_sta_mask = 1 << i;
2682                 /* stream tag: must be non-zero and unique */
2683                 azx_dev->index = i;
2684                 azx_dev->stream_tag = i + 1;
2685         }
2686 
2687         return 0;
2688 }
2689 
2690 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2691 {
2692         if (request_irq(chip->pci->irq, azx_interrupt,
2693                         chip->msi ? 0 : IRQF_SHARED,
2694                         KBUILD_MODNAME, chip)) {
2695                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2696                        "disabling device\n", chip->pci->irq);
2697                 if (do_disconnect)
2698                         snd_card_disconnect(chip->card);
2699                 return -1;
2700         }
2701         chip->irq = chip->pci->irq;
2702         pci_intx(chip->pci, !chip->msi);
2703         return 0;
2704 }
2705 
2706 
2707 static void azx_stop_chip(struct azx *chip)
2708 {
2709         if (!chip->initialized)
2710                 return;
2711 
2712         /* disable interrupts */
2713         azx_int_disable(chip);
2714         azx_int_clear(chip);
2715 
2716         /* disable CORB/RIRB */
2717         azx_free_cmd_io(chip);
2718 
2719         /* disable position buffer */
2720         azx_writel(chip, DPLBASE, 0);
2721         azx_writel(chip, DPUBASE, 0);
2722 
2723         chip->initialized = 0;
2724 }
2725 
2726 #ifdef CONFIG_SND_HDA_DSP_LOADER
2727 /*
2728  * DSP loading code (e.g. for CA0132)
2729  */
2730 
2731 /* use the first stream for loading DSP */
2732 static struct azx_dev *
2733 azx_get_dsp_loader_dev(struct azx *chip)
2734 {
2735         return &chip->azx_dev[chip->playback_index_offset];
2736 }
2737 
2738 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2739                                 unsigned int byte_size,
2740                                 struct snd_dma_buffer *bufp)
2741 {
2742         u32 *bdl;
2743         struct azx *chip = bus->private_data;
2744         struct azx_dev *azx_dev;
2745         int err;
2746 
2747         azx_dev = azx_get_dsp_loader_dev(chip);
2748 
2749         dsp_lock(azx_dev);
2750         spin_lock_irq(&chip->reg_lock);
2751         if (azx_dev->running || azx_dev->locked) {
2752                 spin_unlock_irq(&chip->reg_lock);
2753                 err = -EBUSY;
2754                 goto unlock;
2755         }
2756         azx_dev->prepared = 0;
2757         chip->saved_azx_dev = *azx_dev;
2758         azx_dev->locked = 1;
2759         spin_unlock_irq(&chip->reg_lock);
2760 
2761         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2762                                   snd_dma_pci_data(chip->pci),
2763                                   byte_size, bufp);
2764         if (err < 0)
2765                 goto err_alloc;
2766 
2767         mark_pages_wc(chip, bufp, true);
2768         azx_dev->bufsize = byte_size;
2769         azx_dev->period_bytes = byte_size;
2770         azx_dev->format_val = format;
2771 
2772         azx_stream_reset(chip, azx_dev);
2773 
2774         /* reset BDL address */
2775         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2776         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2777 
2778         azx_dev->frags = 0;
2779         bdl = (u32 *)azx_dev->bdl.area;
2780         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2781         if (err < 0)
2782                 goto error;
2783 
2784         azx_setup_controller(chip, azx_dev);
2785         dsp_unlock(azx_dev);
2786         return azx_dev->stream_tag;
2787 
2788  error:
2789         mark_pages_wc(chip, bufp, false);
2790         snd_dma_free_pages(bufp);
2791  err_alloc:
2792         spin_lock_irq(&chip->reg_lock);
2793         if (azx_dev->opened)
2794                 *azx_dev = chip->saved_azx_dev;
2795         azx_dev->locked = 0;
2796         spin_unlock_irq(&chip->reg_lock);
2797  unlock:
2798         dsp_unlock(azx_dev);
2799         return err;
2800 }
2801 
2802 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2803 {
2804         struct azx *chip = bus->private_data;
2805         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2806 
2807         if (start)
2808                 azx_stream_start(chip, azx_dev);
2809         else
2810                 azx_stream_stop(chip, azx_dev);
2811         azx_dev->running = start;
2812 }
2813 
2814 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2815                                  struct snd_dma_buffer *dmab)
2816 {
2817         struct azx *chip = bus->private_data;
2818         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2819 
2820         if (!dmab->area || !azx_dev->locked)
2821                 return;
2822 
2823         dsp_lock(azx_dev);
2824         /* reset BDL address */
2825         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2826         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2827         azx_sd_writel(azx_dev, SD_CTL, 0);
2828         azx_dev->bufsize = 0;
2829         azx_dev->period_bytes = 0;
2830         azx_dev->format_val = 0;
2831 
2832         mark_pages_wc(chip, dmab, false);
2833         snd_dma_free_pages(dmab);
2834         dmab->area = NULL;
2835 
2836         spin_lock_irq(&chip->reg_lock);
2837         if (azx_dev->opened)
2838                 *azx_dev = chip->saved_azx_dev;
2839         azx_dev->locked = 0;
2840         spin_unlock_irq(&chip->reg_lock);
2841         dsp_unlock(azx_dev);
2842 }
2843 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2844 
2845 #ifdef CONFIG_PM
2846 /* power-up/down the controller */
2847 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2848 {
2849         struct azx *chip = bus->private_data;
2850 
2851         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2852                 return;
2853 
2854         if (power_up)
2855                 pm_runtime_get_sync(&chip->pci->dev);
2856         else
2857                 pm_runtime_put_sync(&chip->pci->dev);
2858 }
2859 
2860 static DEFINE_MUTEX(card_list_lock);
2861 static LIST_HEAD(card_list);
2862 
2863 static void azx_add_card_list(struct azx *chip)
2864 {
2865         mutex_lock(&card_list_lock);
2866         list_add(&chip->list, &card_list);
2867         mutex_unlock(&card_list_lock);
2868 }
2869 
2870 static void azx_del_card_list(struct azx *chip)
2871 {
2872         mutex_lock(&card_list_lock);
2873         list_del_init(&chip->list);
2874         mutex_unlock(&card_list_lock);
2875 }
2876 
2877 /* trigger power-save check at writing parameter */
2878 static int param_set_xint(const char *val, const struct kernel_param *kp)
2879 {
2880         struct azx *chip;
2881         struct hda_codec *c;
2882         int prev = power_save;
2883         int ret = param_set_int(val, kp);
2884 
2885         if (ret || prev == power_save)
2886                 return ret;
2887 
2888         mutex_lock(&card_list_lock);
2889         list_for_each_entry(chip, &card_list, list) {
2890                 if (!chip->bus || chip->disabled)
2891                         continue;
2892                 list_for_each_entry(c, &chip->bus->codec_list, list)
2893                         snd_hda_power_sync(c);
2894         }
2895         mutex_unlock(&card_list_lock);
2896         return 0;
2897 }
2898 #else
2899 #define azx_add_card_list(chip) /* NOP */
2900 #define azx_del_card_list(chip) /* NOP */
2901 #endif /* CONFIG_PM */
2902 
2903 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2904 /*
2905  * power management
2906  */
2907 static int azx_suspend(struct device *dev)
2908 {
2909         struct pci_dev *pci = to_pci_dev(dev);
2910         struct snd_card *card = dev_get_drvdata(dev);
2911         struct azx *chip = card->private_data;
2912         struct azx_pcm *p;
2913 
2914         if (chip->disabled)
2915                 return 0;
2916 
2917         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2918         azx_clear_irq_pending(chip);
2919         list_for_each_entry(p, &chip->pcm_list, list)
2920                 snd_pcm_suspend_all(p->pcm);
2921         if (chip->initialized)
2922                 snd_hda_suspend(chip->bus);
2923         azx_stop_chip(chip);
2924         if (chip->irq >= 0) {
2925                 free_irq(chip->irq, chip);
2926                 chip->irq = -1;
2927         }
2928         if (chip->msi)
2929                 pci_disable_msi(chip->pci);
2930         pci_disable_device(pci);
2931         pci_save_state(pci);
2932         pci_set_power_state(pci, PCI_D3hot);
2933         return 0;
2934 }
2935 
2936 static int azx_resume(struct device *dev)
2937 {
2938         struct pci_dev *pci = to_pci_dev(dev);
2939         struct snd_card *card = dev_get_drvdata(dev);
2940         struct azx *chip = card->private_data;
2941 
2942         if (chip->disabled)
2943                 return 0;
2944 
2945         pci_set_power_state(pci, PCI_D0);
2946         pci_restore_state(pci);
2947         if (pci_enable_device(pci) < 0) {
2948                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2949                        "disabling device\n");
2950                 snd_card_disconnect(card);
2951                 return -EIO;
2952         }
2953         pci_set_master(pci);
2954         if (chip->msi)
2955                 if (pci_enable_msi(pci) < 0)
2956                         chip->msi = 0;
2957         if (azx_acquire_irq(chip, 1) < 0)
2958                 return -EIO;
2959         azx_init_pci(chip);
2960 
2961         azx_init_chip(chip, 1);
2962 
2963         snd_hda_resume(chip->bus);
2964         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2965         return 0;
2966 }
2967 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2968 
2969 #ifdef CONFIG_PM_RUNTIME
2970 static int azx_runtime_suspend(struct device *dev)
2971 {
2972         struct snd_card *card = dev_get_drvdata(dev);
2973         struct azx *chip = card->private_data;
2974 
2975         azx_stop_chip(chip);
2976         azx_clear_irq_pending(chip);
2977         return 0;
2978 }
2979 
2980 static int azx_runtime_resume(struct device *dev)
2981 {
2982         struct snd_card *card = dev_get_drvdata(dev);
2983         struct azx *chip = card->private_data;
2984 
2985         azx_init_pci(chip);
2986         azx_init_chip(chip, 1);
2987         return 0;
2988 }
2989 
2990 static int azx_runtime_idle(struct device *dev)
2991 {
2992         struct snd_card *card = dev_get_drvdata(dev);
2993         struct azx *chip = card->private_data;
2994 
2995         if (!power_save_controller ||
2996             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2997                 return -EBUSY;
2998 
2999         return 0;
3000 }
3001 
3002 #endif /* CONFIG_PM_RUNTIME */
3003 
3004 #ifdef CONFIG_PM
3005 static const struct dev_pm_ops azx_pm = {
3006         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3007 #ifdef CONFIG_PM_SLEEP
3008         .freeze_noirq = azx_freeze_noirq,
3009         .thaw_noirq = azx_thaw_noirq,
3010 #endif
3011         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
3012 };
3013 
3014 #define AZX_PM_OPS      &azx_pm
3015 #else
3016 #define AZX_PM_OPS      NULL
3017 #endif /* CONFIG_PM */
3018 
3019 
3020 /*
3021  * reboot notifier for hang-up problem at power-down
3022  */
3023 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3024 {
3025         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3026         snd_hda_bus_reboot_notify(chip->bus);
3027         azx_stop_chip(chip);
3028         return NOTIFY_OK;
3029 }
3030 
3031 static void azx_notifier_register(struct azx *chip)
3032 {
3033         chip->reboot_notifier.notifier_call = azx_halt;
3034         register_reboot_notifier(&chip->reboot_notifier);
3035 }
3036 
3037 static void azx_notifier_unregister(struct azx *chip)
3038 {
3039         if (chip->reboot_notifier.notifier_call)
3040                 unregister_reboot_notifier(&chip->reboot_notifier);
3041 }
3042 
3043 static int azx_first_init(struct azx *chip);
3044 static int azx_probe_continue(struct azx *chip);
3045 
3046 #ifdef SUPPORT_VGA_SWITCHEROO
3047 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3048 
3049 static void azx_vs_set_state(struct pci_dev *pci,
3050                              enum vga_switcheroo_state state)
3051 {
3052         struct snd_card *card = pci_get_drvdata(pci);
3053         struct azx *chip = card->private_data;
3054         bool disabled;
3055 
3056         wait_for_completion(&chip->probe_wait);
3057         if (chip->init_failed)
3058                 return;
3059 
3060         disabled = (state == VGA_SWITCHEROO_OFF);
3061         if (chip->disabled == disabled)
3062                 return;
3063 
3064         if (!chip->bus) {
3065                 chip->disabled = disabled;
3066                 if (!disabled) {
3067                         snd_printk(KERN_INFO SFX
3068                                    "%s: Start delayed initialization\n",
3069                                    pci_name(chip->pci));
3070                         if (azx_first_init(chip) < 0 ||
3071                             azx_probe_continue(chip) < 0) {
3072                                 snd_printk(KERN_ERR SFX
3073                                            "%s: initialization error\n",
3074                                            pci_name(chip->pci));
3075                                 chip->init_failed = true;
3076                         }
3077                 }
3078         } else {
3079                 snd_printk(KERN_INFO SFX
3080                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3081                            disabled ? "Disabling" : "Enabling");
3082                 if (disabled) {
3083                         azx_suspend(&pci->dev);
3084                         chip->disabled = true;
3085                         if (snd_hda_lock_devices(chip->bus))
3086                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3087                                            pci_name(chip->pci));
3088                 } else {
3089                         snd_hda_unlock_devices(chip->bus);
3090                         chip->disabled = false;
3091                         azx_resume(&pci->dev);
3092                 }
3093         }
3094 }
3095 
3096 static bool azx_vs_can_switch(struct pci_dev *pci)
3097 {
3098         struct snd_card *card = pci_get_drvdata(pci);
3099         struct azx *chip = card->private_data;
3100 
3101         wait_for_completion(&chip->probe_wait);
3102         if (chip->init_failed)
3103                 return false;
3104         if (chip->disabled || !chip->bus)
3105                 return true;
3106         if (snd_hda_lock_devices(chip->bus))
3107                 return false;
3108         snd_hda_unlock_devices(chip->bus);
3109         return true;
3110 }
3111 
3112 static void init_vga_switcheroo(struct azx *chip)
3113 {
3114         struct pci_dev *p = get_bound_vga(chip->pci);
3115         if (p) {
3116                 snd_printk(KERN_INFO SFX
3117                            "%s: Handle VGA-switcheroo audio client\n",
3118                            pci_name(chip->pci));
3119                 chip->use_vga_switcheroo = 1;
3120                 pci_dev_put(p);
3121         }
3122 }
3123 
3124 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3125         .set_gpu_state = azx_vs_set_state,
3126         .can_switch = azx_vs_can_switch,
3127 };
3128 
3129 static int register_vga_switcheroo(struct azx *chip)
3130 {
3131         int err;
3132 
3133         if (!chip->use_vga_switcheroo)
3134                 return 0;
3135         /* FIXME: currently only handling DIS controller
3136          * is there any machine with two switchable HDMI audio controllers?
3137          */
3138         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3139                                                     VGA_SWITCHEROO_DIS,
3140                                                     chip->bus != NULL);
3141         if (err < 0)
3142                 return err;
3143         chip->vga_switcheroo_registered = 1;
3144         return 0;
3145 }
3146 #else
3147 #define init_vga_switcheroo(chip)               /* NOP */
3148 #define register_vga_switcheroo(chip)           0
3149 #define check_hdmi_disabled(pci)        false
3150 #endif /* SUPPORT_VGA_SWITCHER */
3151 
3152 /*
3153  * destructor
3154  */
3155 static int azx_free(struct azx *chip)
3156 {
3157         int i;
3158 
3159         azx_del_card_list(chip);
3160 
3161         azx_notifier_unregister(chip);
3162 
3163         chip->init_failed = 1; /* to be sure */
3164         complete_all(&chip->probe_wait);
3165 
3166         if (use_vga_switcheroo(chip)) {
3167                 if (chip->disabled && chip->bus)
3168                         snd_hda_unlock_devices(chip->bus);
3169                 if (chip->vga_switcheroo_registered)
3170                         vga_switcheroo_unregister_client(chip->pci);
3171         }
3172 
3173         if (chip->initialized) {
3174                 azx_clear_irq_pending(chip);
3175                 for (i = 0; i < chip->num_streams; i++)
3176                         azx_stream_stop(chip, &chip->azx_dev[i]);
3177                 azx_stop_chip(chip);
3178         }
3179 
3180         if (chip->irq >= 0)
3181                 free_irq(chip->irq, (void*)chip);
3182         if (chip->msi)
3183                 pci_disable_msi(chip->pci);
3184         if (chip->remap_addr)
3185                 iounmap(chip->remap_addr);
3186 
3187         if (chip->azx_dev) {
3188                 for (i = 0; i < chip->num_streams; i++)
3189                         if (chip->azx_dev[i].bdl.area) {
3190                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3191                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3192                         }
3193         }
3194         if (chip->rb.area) {
3195                 mark_pages_wc(chip, &chip->rb, false);
3196                 snd_dma_free_pages(&chip->rb);
3197         }
3198         if (chip->posbuf.area) {
3199                 mark_pages_wc(chip, &chip->posbuf, false);
3200                 snd_dma_free_pages(&chip->posbuf);
3201         }
3202         if (chip->region_requested)
3203                 pci_release_regions(chip->pci);
3204         pci_disable_device(chip->pci);
3205         kfree(chip->azx_dev);
3206 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3207         if (chip->fw)
3208                 release_firmware(chip->fw);
3209 #endif
3210         kfree(chip);
3211 
3212         return 0;
3213 }
3214 
3215 static int azx_dev_free(struct snd_device *device)
3216 {
3217         return azx_free(device->device_data);
3218 }
3219 
3220 #ifdef SUPPORT_VGA_SWITCHEROO
3221 /*
3222  * Check of disabled HDMI controller by vga-switcheroo
3223  */
3224 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3225 {
3226         struct pci_dev *p;
3227 
3228         /* check only discrete GPU */
3229         switch (pci->vendor) {
3230         case PCI_VENDOR_ID_ATI:
3231         case PCI_VENDOR_ID_AMD:
3232         case PCI_VENDOR_ID_NVIDIA:
3233                 if (pci->devfn == 1) {
3234                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3235                                                         pci->bus->number, 0);
3236                         if (p) {
3237                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3238                                         return p;
3239                                 pci_dev_put(p);
3240                         }
3241                 }
3242                 break;
3243         }
3244         return NULL;
3245 }
3246 
3247 static bool check_hdmi_disabled(struct pci_dev *pci)
3248 {
3249         bool vga_inactive = false;
3250         struct pci_dev *p = get_bound_vga(pci);
3251 
3252         if (p) {
3253                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3254                         vga_inactive = true;
3255                 pci_dev_put(p);
3256         }
3257         return vga_inactive;
3258 }
3259 #endif /* SUPPORT_VGA_SWITCHEROO */
3260 
3261 /*
3262  * white/black-listing for position_fix
3263  */
3264 static struct snd_pci_quirk position_fix_list[] = {
3265         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3266         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3267         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3268         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3269         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3270         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3271         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3272         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3273         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3274         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3275         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3276         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3277         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3278         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3279         {}
3280 };
3281 
3282 static int check_position_fix(struct azx *chip, int fix)
3283 {
3284         const struct snd_pci_quirk *q;
3285 
3286         switch (fix) {
3287         case POS_FIX_AUTO:
3288         case POS_FIX_LPIB:
3289         case POS_FIX_POSBUF:
3290         case POS_FIX_VIACOMBO:
3291         case POS_FIX_COMBO:
3292                 return fix;
3293         }
3294 
3295         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3296         if (q) {
3297                 printk(KERN_INFO
3298                        "hda_intel: position_fix set to %d "
3299                        "for device %04x:%04x\n",
3300                        q->value, q->subvendor, q->subdevice);
3301                 return q->value;
3302         }
3303 
3304         /* Check VIA/ATI HD Audio Controller exist */
3305         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3306                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3307                 return POS_FIX_VIACOMBO;
3308         }
3309         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3310                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3311                 return POS_FIX_LPIB;
3312         }
3313         return POS_FIX_AUTO;
3314 }
3315 
3316 /*
3317  * black-lists for probe_mask
3318  */
3319 static struct snd_pci_quirk probe_mask_list[] = {
3320         /* Thinkpad often breaks the controller communication when accessing
3321          * to the non-working (or non-existing) modem codec slot.
3322          */
3323         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3324         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3325         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3326         /* broken BIOS */
3327         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3328         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3329         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3330         /* forced codec slots */
3331         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3332         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3333         /* WinFast VP200 H (Teradici) user reported broken communication */
3334         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3335         {}
3336 };
3337 
3338 #define AZX_FORCE_CODEC_MASK    0x100
3339 
3340 static void check_probe_mask(struct azx *chip, int dev)
3341 {
3342         const struct snd_pci_quirk *q;
3343 
3344         chip->codec_probe_mask = probe_mask[dev];
3345         if (chip->codec_probe_mask == -1) {
3346                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3347                 if (q) {
3348                         printk(KERN_INFO
3349                                "hda_intel: probe_mask set to 0x%x "
3350                                "for device %04x:%04x\n",
3351                                q->value, q->subvendor, q->subdevice);
3352                         chip->codec_probe_mask = q->value;
3353                 }
3354         }
3355 
3356         /* check forced option */
3357         if (chip->codec_probe_mask != -1 &&
3358             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3359                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3360                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3361                        chip->codec_mask);
3362         }
3363 }
3364 
3365 /*
3366  * white/black-list for enable_msi
3367  */
3368 static struct snd_pci_quirk msi_black_list[] = {
3369         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
3370         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
3371         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
3372         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
3373         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3374         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3375         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3376         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
3377         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3378         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3379         {}
3380 };
3381 
3382 static void check_msi(struct azx *chip)
3383 {
3384         const struct snd_pci_quirk *q;
3385 
3386         if (enable_msi >= 0) {
3387                 chip->msi = !!enable_msi;
3388                 return;
3389         }
3390         chip->msi = 1;  /* enable MSI as default */
3391         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3392         if (q) {
3393                 printk(KERN_INFO
3394                        "hda_intel: msi for device %04x:%04x set to %d\n",
3395                        q->subvendor, q->subdevice, q->value);
3396                 chip->msi = q->value;
3397                 return;
3398         }
3399 
3400         /* NVidia chipsets seem to cause troubles with MSI */
3401         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3402                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3403                 chip->msi = 0;
3404         }
3405 }
3406 
3407 /* check the snoop mode availability */
3408 static void azx_check_snoop_available(struct azx *chip)
3409 {
3410         bool snoop = chip->snoop;
3411 
3412         switch (chip->driver_type) {
3413         case AZX_DRIVER_VIA:
3414                 /* force to non-snoop mode for a new VIA controller
3415                  * when BIOS is set
3416                  */
3417                 if (snoop) {
3418                         u8 val;
3419                         pci_read_config_byte(chip->pci, 0x42, &val);
3420                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3421                                 snoop = false;
3422                 }
3423                 break;
3424         case AZX_DRIVER_ATIHDMI_NS:
3425                 /* new ATI HDMI requires non-snoop */
3426                 snoop = false;
3427                 break;
3428         case AZX_DRIVER_CTHDA:
3429                 snoop = false;
3430                 break;
3431         }
3432 
3433         if (snoop != chip->snoop) {
3434                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3435                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3436                 chip->snoop = snoop;
3437         }
3438 }
3439 
3440 /*
3441  * constructor
3442  */
3443 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3444                       int dev, unsigned int driver_caps,
3445                       struct azx **rchip)
3446 {
3447         static struct snd_device_ops ops = {
3448                 .dev_free = azx_dev_free,
3449         };
3450         struct azx *chip;
3451         int err;
3452 
3453         *rchip = NULL;
3454 
3455         err = pci_enable_device(pci);
3456         if (err < 0)
3457                 return err;
3458 
3459         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3460         if (!chip) {
3461                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3462                 pci_disable_device(pci);
3463                 return -ENOMEM;
3464         }
3465 
3466         spin_lock_init(&chip->reg_lock);
3467         mutex_init(&chip->open_mutex);
3468         chip->card = card;
3469         chip->pci = pci;
3470         chip->irq = -1;
3471         chip->driver_caps = driver_caps;
3472         chip->driver_type = driver_caps & 0xff;
3473         check_msi(chip);
3474         chip->dev_index = dev;
3475         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3476         INIT_LIST_HEAD(&chip->pcm_list);
3477         INIT_LIST_HEAD(&chip->list);
3478         init_vga_switcheroo(chip);
3479         init_completion(&chip->probe_wait);
3480 
3481         chip->position_fix[0] = chip->position_fix[1] =
3482                 check_position_fix(chip, position_fix[dev]);
3483         /* combo mode uses LPIB for playback */
3484         if (chip->position_fix[0] == POS_FIX_COMBO) {
3485                 chip->position_fix[0] = POS_FIX_LPIB;
3486                 chip->position_fix[1] = POS_FIX_AUTO;
3487         }
3488 
3489         check_probe_mask(chip, dev);
3490 
3491         chip->single_cmd = single_cmd;
3492         chip->snoop = hda_snoop;
3493         azx_check_snoop_available(chip);
3494 
3495         if (bdl_pos_adj[dev] < 0) {
3496                 switch (chip->driver_type) {
3497                 case AZX_DRIVER_ICH:
3498                 case AZX_DRIVER_PCH:
3499                         bdl_pos_adj[dev] = 1;
3500                         break;
3501                 default:
3502                         bdl_pos_adj[dev] = 32;
3503                         break;
3504                 }
3505         }
3506 
3507         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3508         if (err < 0) {
3509                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3510                    pci_name(chip->pci));
3511                 azx_free(chip);
3512                 return err;
3513         }
3514 
3515         *rchip = chip;
3516         return 0;
3517 }
3518 
3519 static int azx_first_init(struct azx *chip)
3520 {
3521         int dev = chip->dev_index;
3522         struct pci_dev *pci = chip->pci;
3523         struct snd_card *card = chip->card;
3524         int i, err;
3525         unsigned short gcap;
3526 
3527 #if BITS_PER_LONG != 64
3528         /* Fix up base address on ULI M5461 */
3529         if (chip->driver_type == AZX_DRIVER_ULI) {
3530                 u16 tmp3;
3531                 pci_read_config_word(pci, 0x40, &tmp3);
3532                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3533                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3534         }
3535 #endif
3536 
3537         err = pci_request_regions(pci, "ICH HD audio");
3538         if (err < 0)
3539                 return err;
3540         chip->region_requested = 1;
3541 
3542         chip->addr = pci_resource_start(pci, 0);
3543         chip->remap_addr = pci_ioremap_bar(pci, 0);
3544         if (chip->remap_addr == NULL) {
3545                 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3546                 return -ENXIO;
3547         }
3548 
3549         if (chip->msi)
3550                 if (pci_enable_msi(pci) < 0)
3551                         chip->msi = 0;
3552 
3553         if (azx_acquire_irq(chip, 0) < 0)
3554                 return -EBUSY;
3555 
3556         pci_set_master(pci);
3557         synchronize_irq(chip->irq);
3558 
3559         gcap = azx_readw(chip, GCAP);
3560         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3561 
3562         /* disable SB600 64bit support for safety */
3563         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3564                 struct pci_dev *p_smbus;
3565                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3566                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3567                                          NULL);
3568                 if (p_smbus) {
3569                         if (p_smbus->revision < 0x30)
3570                                 gcap &= ~ICH6_GCAP_64OK;
3571                         pci_dev_put(p_smbus);
3572                 }
3573         }
3574 
3575         /* disable 64bit DMA address on some devices */
3576         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3577                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3578                 gcap &= ~ICH6_GCAP_64OK;
3579         }
3580 
3581         /* disable buffer size rounding to 128-byte multiples if supported */
3582         if (align_buffer_size >= 0)
3583                 chip->align_buffer_size = !!align_buffer_size;
3584         else {
3585                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3586                         chip->align_buffer_size = 0;
3587                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3588                         chip->align_buffer_size = 1;
3589                 else
3590                         chip->align_buffer_size = 1;
3591         }
3592 
3593         /* allow 64bit DMA address if supported by H/W */
3594         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3595                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3596         else {
3597                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3598                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3599         }
3600 
3601         /* read number of streams from GCAP register instead of using
3602          * hardcoded value
3603          */
3604         chip->capture_streams = (gcap >> 8) & 0x0f;
3605         chip->playback_streams = (gcap >> 12) & 0x0f;
3606         if (!chip->playback_streams && !chip->capture_streams) {
3607                 /* gcap didn't give any info, switching to old method */
3608 
3609                 switch (chip->driver_type) {
3610                 case AZX_DRIVER_ULI:
3611                         chip->playback_streams = ULI_NUM_PLAYBACK;
3612                         chip->capture_streams = ULI_NUM_CAPTURE;
3613                         break;
3614                 case AZX_DRIVER_ATIHDMI:
3615                 case AZX_DRIVER_ATIHDMI_NS:
3616                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3617                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3618                         break;
3619                 case AZX_DRIVER_GENERIC:
3620                 default:
3621                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3622                         chip->capture_streams = ICH6_NUM_CAPTURE;
3623                         break;
3624                 }
3625         }
3626         chip->capture_index_offset = 0;
3627         chip->playback_index_offset = chip->capture_streams;
3628         chip->num_streams = chip->playback_streams + chip->capture_streams;
3629         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3630                                 GFP_KERNEL);
3631         if (!chip->azx_dev) {
3632                 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3633                 return -ENOMEM;
3634         }
3635 
3636         for (i = 0; i < chip->num_streams; i++) {
3637                 dsp_lock_init(&chip->azx_dev[i]);
3638                 /* allocate memory for the BDL for each stream */
3639                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3640                                           snd_dma_pci_data(chip->pci),
3641                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3642                 if (err < 0) {
3643                         snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3644                         return -ENOMEM;
3645                 }
3646                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3647         }
3648         /* allocate memory for the position buffer */
3649         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3650                                   snd_dma_pci_data(chip->pci),
3651                                   chip->num_streams * 8, &chip->posbuf);
3652         if (err < 0) {
3653                 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3654                 return -ENOMEM;
3655         }
3656         mark_pages_wc(chip, &chip->posbuf, true);
3657         /* allocate CORB/RIRB */
3658         err = azx_alloc_cmd_io(chip);
3659         if (err < 0)
3660                 return err;
3661 
3662         /* initialize streams */
3663         azx_init_stream(chip);
3664 
3665         /* initialize chip */
3666         azx_init_pci(chip);
3667         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3668 
3669         /* codec detection */
3670         if (!chip->codec_mask) {
3671                 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3672                 return -ENODEV;
3673         }
3674 
3675         strcpy(card->driver, "HDA-Intel");
3676         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3677                 sizeof(card->shortname));
3678         snprintf(card->longname, sizeof(card->longname),
3679                  "%s at 0x%lx irq %i",
3680                  card->shortname, chip->addr, chip->irq);
3681 
3682         return 0;
3683 }
3684 
3685 static void power_down_all_codecs(struct azx *chip)
3686 {
3687 #ifdef CONFIG_PM
3688         /* The codecs were powered up in snd_hda_codec_new().
3689          * Now all initialization done, so turn them down if possible
3690          */
3691         struct hda_codec *codec;
3692         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3693                 snd_hda_power_down(codec);
3694         }
3695 #endif
3696 }
3697 
3698 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3699 /* callback from request_firmware_nowait() */
3700 static void azx_firmware_cb(const struct firmware *fw, void *context)
3701 {
3702         struct snd_card *card = context;
3703         struct azx *chip = card->private_data;
3704         struct pci_dev *pci = chip->pci;
3705 
3706         if (!fw) {
3707                 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3708                            pci_name(chip->pci));
3709                 goto error;
3710         }
3711 
3712         chip->fw = fw;
3713         if (!chip->disabled) {
3714                 /* continue probing */
3715                 if (azx_probe_continue(chip))
3716                         goto error;
3717         }
3718         return; /* OK */
3719 
3720  error:
3721         snd_card_free(card);
3722         pci_set_drvdata(pci, NULL);
3723 }
3724 #endif
3725 
3726 static int azx_probe(struct pci_dev *pci,
3727                      const struct pci_device_id *pci_id)
3728 {
3729         static int dev;
3730         struct snd_card *card;
3731         struct azx *chip;
3732         bool probe_now;
3733         int err;
3734 
3735         if (dev >= SNDRV_CARDS)
3736                 return -ENODEV;
3737         if (!enable[dev]) {
3738                 dev++;
3739                 return -ENOENT;
3740         }
3741 
3742         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3743         if (err < 0) {
3744                 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3745                 return err;
3746         }
3747 
3748         snd_card_set_dev(card, &pci->dev);
3749 
3750         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3751         if (err < 0)
3752                 goto out_free;
3753         card->private_data = chip;
3754 
3755         pci_set_drvdata(pci, card);
3756 
3757         err = register_vga_switcheroo(chip);
3758         if (err < 0) {
3759                 snd_printk(KERN_ERR SFX
3760                            "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3761                 goto out_free;
3762         }
3763 
3764         if (check_hdmi_disabled(pci)) {
3765                 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3766                            pci_name(pci));
3767                 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3768                 chip->disabled = true;
3769         }
3770 
3771         probe_now = !chip->disabled;
3772         if (probe_now) {
3773                 err = azx_first_init(chip);
3774                 if (err < 0)
3775                         goto out_free;
3776         }
3777 
3778 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3779         if (patch[dev] && *patch[dev]) {
3780                 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3781                            pci_name(pci), patch[dev]);
3782                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3783                                               &pci->dev, GFP_KERNEL, card,
3784                                               azx_firmware_cb);
3785                 if (err < 0)
3786                         goto out_free;
3787                 probe_now = false; /* continued in azx_firmware_cb() */
3788         }
3789 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3790 
3791         if (probe_now) {
3792                 err = azx_probe_continue(chip);
3793                 if (err < 0)
3794                         goto out_free;
3795         }
3796 
3797         if (pci_dev_run_wake(pci))
3798                 pm_runtime_put_noidle(&pci->dev);
3799 
3800         dev++;
3801         complete_all(&chip->probe_wait);
3802         return 0;
3803 
3804 out_free:
3805         snd_card_free(card);
3806         pci_set_drvdata(pci, NULL);
3807         return err;
3808 }
3809 
3810 static int azx_probe_continue(struct azx *chip)
3811 {
3812         int dev = chip->dev_index;
3813         int err;
3814 
3815 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3816         chip->beep_mode = beep_mode[dev];
3817 #endif
3818 
3819         /* create codec instances */
3820         err = azx_codec_create(chip, model[dev]);
3821         if (err < 0)
3822                 goto out_free;
3823 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3824         if (chip->fw) {
3825                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3826                                          chip->fw->data);
3827                 if (err < 0)
3828                         goto out_free;
3829 #ifndef CONFIG_PM
3830                 release_firmware(chip->fw); /* no longer needed */
3831                 chip->fw = NULL;
3832 #endif
3833         }
3834 #endif
3835         if ((probe_only[dev] & 1) == 0) {
3836                 err = azx_codec_configure(chip);
3837                 if (err < 0)
3838                         goto out_free;
3839         }
3840 
3841         /* create PCM streams */
3842         err = snd_hda_build_pcms(chip->bus);
3843         if (err < 0)
3844                 goto out_free;
3845 
3846         /* create mixer controls */
3847         err = azx_mixer_create(chip);
3848         if (err < 0)
3849                 goto out_free;
3850 
3851         err = snd_card_register(chip->card);
3852         if (err < 0)
3853                 goto out_free;
3854 
3855         chip->running = 1;
3856         power_down_all_codecs(chip);
3857         azx_notifier_register(chip);
3858         azx_add_card_list(chip);
3859 
3860         return 0;
3861 
3862 out_free:
3863         chip->init_failed = 1;
3864         return err;
3865 }
3866 
3867 static void azx_remove(struct pci_dev *pci)
3868 {
3869         struct snd_card *card = pci_get_drvdata(pci);
3870 
3871         if (pci_dev_run_wake(pci))
3872                 pm_runtime_get_noresume(&pci->dev);
3873 
3874         if (card)
3875                 snd_card_free(card);
3876         pci_set_drvdata(pci, NULL);
3877 }
3878 
3879 /* PCI IDs */
3880 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3881         /* CPT */
3882         { PCI_DEVICE(0x8086, 0x1c20),
3883           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3884         /* PBG */
3885         { PCI_DEVICE(0x8086, 0x1d20),
3886           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3887         /* Panther Point */
3888         { PCI_DEVICE(0x8086, 0x1e20),
3889           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3890         /* Lynx Point */
3891         { PCI_DEVICE(0x8086, 0x8c20),
3892           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3893         /* 9 Series */
3894         { PCI_DEVICE(0x8086, 0x8ca0),
3895           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3896         /* Wellsburg */
3897         { PCI_DEVICE(0x8086, 0x8d20),
3898           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3899         { PCI_DEVICE(0x8086, 0x8d21),
3900           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3901         /* Lewisburg */
3902         { PCI_DEVICE(0x8086, 0xa1f0),
3903           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3904         { PCI_DEVICE(0x8086, 0xa270),
3905           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3906         /* Lynx Point-LP */
3907         { PCI_DEVICE(0x8086, 0x9c20),
3908           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3909         /* Lynx Point-LP */
3910         { PCI_DEVICE(0x8086, 0x9c21),
3911           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3912         /* Haswell */
3913         { PCI_DEVICE(0x8086, 0x0a0c),
3914           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3915         { PCI_DEVICE(0x8086, 0x0c0c),
3916           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3917         { PCI_DEVICE(0x8086, 0x0d0c),
3918           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3919         /* 5 Series/3400 */
3920         { PCI_DEVICE(0x8086, 0x3b56),
3921           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3922         /* Poulsbo */
3923         { PCI_DEVICE(0x8086, 0x811b),
3924           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3925         /* Oaktrail */
3926         { PCI_DEVICE(0x8086, 0x080a),
3927           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3928         /* ICH */
3929         { PCI_DEVICE(0x8086, 0x2668),
3930           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3931           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3932         { PCI_DEVICE(0x8086, 0x27d8),
3933           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3934           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3935         { PCI_DEVICE(0x8086, 0x269a),
3936           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3937           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3938         { PCI_DEVICE(0x8086, 0x284b),
3939           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3940           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3941         { PCI_DEVICE(0x8086, 0x293e),
3942           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3943           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3944         { PCI_DEVICE(0x8086, 0x293f),
3945           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3946           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3947         { PCI_DEVICE(0x8086, 0x3a3e),
3948           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3949           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3950         { PCI_DEVICE(0x8086, 0x3a6e),
3951           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3952           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3953         /* Generic Intel */
3954         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3955           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3956           .class_mask = 0xffffff,
3957           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3958         /* ATI SB 450/600/700/800/900 */
3959         { PCI_DEVICE(0x1002, 0x437b),
3960           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3961         { PCI_DEVICE(0x1002, 0x4383),
3962           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3963         /* AMD Hudson */
3964         { PCI_DEVICE(0x1022, 0x780d),
3965           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3966         /* ATI HDMI */
3967         { PCI_DEVICE(0x1002, 0x793b),
3968           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3969         { PCI_DEVICE(0x1002, 0x7919),
3970           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3971         { PCI_DEVICE(0x1002, 0x960f),
3972           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3973         { PCI_DEVICE(0x1002, 0x970f),
3974           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3975         { PCI_DEVICE(0x1002, 0xaa00),
3976           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3977         { PCI_DEVICE(0x1002, 0xaa08),
3978           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3979         { PCI_DEVICE(0x1002, 0xaa10),
3980           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3981         { PCI_DEVICE(0x1002, 0xaa18),
3982           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3983         { PCI_DEVICE(0x1002, 0xaa20),
3984           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3985         { PCI_DEVICE(0x1002, 0xaa28),
3986           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3987         { PCI_DEVICE(0x1002, 0xaa30),
3988           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3989         { PCI_DEVICE(0x1002, 0xaa38),
3990           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3991         { PCI_DEVICE(0x1002, 0xaa40),
3992           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3993         { PCI_DEVICE(0x1002, 0xaa48),
3994           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3995         { PCI_DEVICE(0x1002, 0x9902),
3996           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3997         { PCI_DEVICE(0x1002, 0xaaa0),
3998           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3999         { PCI_DEVICE(0x1002, 0xaaa8),
4000           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4001         { PCI_DEVICE(0x1002, 0xaab0),
4002           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4003         /* VIA VT8251/VT8237A */
4004         { PCI_DEVICE(0x1106, 0x3288),
4005           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
4006         /* VIA GFX VT7122/VX900 */
4007         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4008         /* VIA GFX VT6122/VX11 */
4009         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
4010         /* SIS966 */
4011         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4012         /* ULI M5461 */
4013         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4014         /* NVIDIA MCP */
4015         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4016           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4017           .class_mask = 0xffffff,
4018           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
4019         /* Teradici */
4020         { PCI_DEVICE(0x6549, 0x1200),
4021           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4022         { PCI_DEVICE(0x6549, 0x2200),
4023           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4024         /* Creative X-Fi (CA0110-IBG) */
4025         /* CTHDA chips */
4026         { PCI_DEVICE(0x1102, 0x0010),
4027           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4028         { PCI_DEVICE(0x1102, 0x0012),
4029           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4030 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4031         /* the following entry conflicts with snd-ctxfi driver,
4032          * as ctxfi driver mutates from HD-audio to native mode with
4033          * a special command sequence.
4034          */
4035         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4036           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4037           .class_mask = 0xffffff,
4038           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4039           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4040 #else
4041         /* this entry seems still valid -- i.e. without emu20kx chip */
4042         { PCI_DEVICE(0x1102, 0x0009),
4043           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4044           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4045 #endif
4046         /* Vortex86MX */
4047         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4048         /* VMware HDAudio */
4049         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4050         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4051         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4052           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4053           .class_mask = 0xffffff,
4054           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4055         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4056           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4057           .class_mask = 0xffffff,
4058           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4059         { 0, }
4060 };
4061 MODULE_DEVICE_TABLE(pci, azx_ids);
4062 
4063 /* pci_driver definition */
4064 static struct pci_driver azx_driver = {
4065         .name = KBUILD_MODNAME,
4066         .id_table = azx_ids,
4067         .probe = azx_probe,
4068         .remove = azx_remove,
4069         .driver = {
4070                 .pm = AZX_PM_OPS,
4071         },
4072 };
4073 
4074 module_pci_driver(azx_driver);
4075 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp