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TOMOYO Linux Cross Reference
Linux/sound/pci/rme9652/hdspm.c

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  1 /*
  2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
  3  *
  4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
  5  *      code based on hdsp.c   Paul Davis
  6  *                             Marcus Andersson
  7  *                             Thomas Charbonnel
  8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
  9  *                                               <remy.bruno@trinnov.com>
 10  *
 11  *      Modified 2009-04-13 for proper metering by Florian Faber
 12  *                                               <faber@faberman.de>
 13  *
 14  *      Modified 2009-04-14 for native float support by Florian Faber
 15  *                                               <faber@faberman.de>
 16  *
 17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
 18  *                                               <faber@faberman.de>
 19  *
 20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
 21  *
 22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
 23  *
 24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
 25  *
 26  *   This program is free software; you can redistribute it and/or modify
 27  *   it under the terms of the GNU General Public License as published by
 28  *   the Free Software Foundation; either version 2 of the License, or
 29  *   (at your option) any later version.
 30  *
 31  *   This program is distributed in the hope that it will be useful,
 32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 34  *   GNU General Public License for more details.
 35  *
 36  *   You should have received a copy of the GNU General Public License
 37  *   along with this program; if not, write to the Free Software
 38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 39  *
 40  */
 41 #include <linux/init.h>
 42 #include <linux/delay.h>
 43 #include <linux/interrupt.h>
 44 #include <linux/module.h>
 45 #include <linux/slab.h>
 46 #include <linux/pci.h>
 47 #include <linux/math64.h>
 48 #include <asm/io.h>
 49 
 50 #include <sound/core.h>
 51 #include <sound/control.h>
 52 #include <sound/pcm.h>
 53 #include <sound/pcm_params.h>
 54 #include <sound/info.h>
 55 #include <sound/asoundef.h>
 56 #include <sound/rawmidi.h>
 57 #include <sound/hwdep.h>
 58 #include <sound/initval.h>
 59 
 60 #include <sound/hdspm.h>
 61 
 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
 64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
 65 
 66 module_param_array(index, int, NULL, 0444);
 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
 68 
 69 module_param_array(id, charp, NULL, 0444);
 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
 71 
 72 module_param_array(enable, bool, NULL, 0444);
 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
 74 
 75 
 76 MODULE_AUTHOR
 77 (
 78         "Winfried Ritsch <ritsch_AT_iem.at>, "
 79         "Paul Davis <paul@linuxaudiosystems.com>, "
 80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
 81         "Remy Bruno <remy.bruno@trinnov.com>, "
 82         "Florian Faber <faberman@linuxproaudio.org>, "
 83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
 84 );
 85 MODULE_DESCRIPTION("RME HDSPM");
 86 MODULE_LICENSE("GPL");
 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
 88 
 89 /* --- Write registers. ---
 90   These are defined as byte-offsets from the iobase value.  */
 91 
 92 #define HDSPM_WR_SETTINGS             0
 93 #define HDSPM_outputBufferAddress    32
 94 #define HDSPM_inputBufferAddress     36
 95 #define HDSPM_controlRegister        64
 96 #define HDSPM_interruptConfirmation  96
 97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
 98 #define HDSPM_freqReg                256  /* for AES32 */
 99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
100 #define HDSPM_midiDataOut1           356
101 #define HDSPM_eeprom_wr              384  /* for AES32 */
102 
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
106 
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut       8192
110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
111 
112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
113 
114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
115 
116 /* --- Read registers. ---
117    These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister    0
119 /*#define HDSPM_statusRegister2  96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121  * offset 192, for AES32 *and* MADI
122  * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2  192
124 #define HDSPM_timecodeRegister 128
125 
126 /* AIO, RayDAT */
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
131 
132 #define HDSPM_RD_TCO           256
133 #define HDSPM_RD_PLL_FREQ      512
134 #define HDSPM_WR_TCO           128
135 
136 #define HDSPM_TCO1_TCO_lock                     0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
143 
144 #define HDSPM_TCO1_set_TC                       0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
148 
149 #define HDSPM_TCO2_TC_run                       0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
155 #define HDSPM_TCO2_set_flywheel                 0x00400000
156 
157 #define HDSPM_TCO2_set_01_4                     0x01000000
158 #define HDSPM_TCO2_set_pull_down                0x02000000
159 #define HDSPM_TCO2_set_pull_up                  0x04000000
160 #define HDSPM_TCO2_set_freq                     0x08000000
161 #define HDSPM_TCO2_set_term_75R                 0x10000000
162 #define HDSPM_TCO2_set_input_LSB                0x20000000
163 #define HDSPM_TCO2_set_input_MSB                0x40000000
164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
165 
166 
167 #define HDSPM_midiDataOut0    352
168 #define HDSPM_midiDataOut1    356
169 #define HDSPM_midiDataOut2    368
170 
171 #define HDSPM_midiDataIn0     360
172 #define HDSPM_midiDataIn1     364
173 #define HDSPM_midiDataIn2     372
174 #define HDSPM_midiDataIn3     376
175 
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0  384
178 #define HDSPM_midiStatusOut1  388
179 #define HDSPM_midiStatusOut2  400
180 
181 #define HDSPM_midiStatusIn0   392
182 #define HDSPM_midiStatusIn1   396
183 #define HDSPM_midiStatusIn2   404
184 #define HDSPM_midiStatusIn3   408
185 
186 
187 /* the meters are regular i/o-mapped registers, but offset
188    considerably from the rest. the peak registers are reset
189    when read; the least-significant 4 bits are full-scale counters;
190    the actual peak value is in the most-significant 24 bits.
191 */
192 
193 #define HDSPM_MADI_INPUT_PEAK           4096
194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
195 #define HDSPM_MADI_OUTPUT_PEAK          4608
196 
197 #define HDSPM_MADI_INPUT_RMS_L          6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
200 
201 #define HDSPM_MADI_INPUT_RMS_H          7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
204 
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start                (1<<0) /* start engine */
207 
208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
211 
212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
214                                           register [RayDAT, AIO] */
215 
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217 
218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
222 
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
225                                      56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
227 
228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
229                                      0=off, 1=on  */ /* MADI ONLY */
230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231 
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233                                     * -- MADI ONLY
234                                     */
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236 
237 #define HDSPM_SyncRef2     (1<<13)
238 #define HDSPM_SyncRef3     (1<<25)
239 
240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
242                                       AES additional bits in
243                                       lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246 
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
251 
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT         0x2000000
254 
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
258 
259 #define HDSPM_wclk_sel (1<<30)
260 
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
264                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical   0
267 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269                               HDSPM_SyncRef2|HDSPM_SyncRef3)
270 
271 #define HDSPM_c0_SyncRef0      0x2
272 #define HDSPM_c0_SyncRef1      0x4
273 #define HDSPM_c0_SyncRef2      0x8
274 #define HDSPM_c0_SyncRef3      0x10
275 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277 
278 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO     2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
282 
283 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289                                 HDSPM_Frequency0)
290 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293                                  HDSPM_Frequency0)
294 
295 
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK    1
299 #define HDSPM_SYNC_CHECK_SYNC    2
300 
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD      0
303 #define HDSPM_AUTOSYNC_FROM_MADI      1
304 #define HDSPM_AUTOSYNC_FROM_TCO       2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
306 #define HDSPM_AUTOSYNC_FROM_NONE      4
307 
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0         /* optical   */
310 #define HDSPM_COAXIAL 1         /* BNC */
311 
312 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
314 
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
317 
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS             (1<<0)
320 #define HDSPM_TCK             (1<<1)
321 #define HDSPM_TDI             (1<<2)
322 #define HDSPM_JTAG            (1<<3)
323 #define HDSPM_PWDN            (1<<4)
324 #define HDSPM_PROGRAM         (1<<5)
325 #define HDSPM_CONFIG_MODE_0   (1<<6)
326 #define HDSPM_CONFIG_MODE_1   (1<<7)
327 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE  (1<<9)
329 #define HDSPM_RD_MULTIPLE     (1<<10)
330 
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332      that do not conflict with specific bits for AES32 seem to be valid also
333      for the AES32
334  */
335 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
338                                          * (like inp0)
339                                          */
340 
341 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
343 
344 #define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
346 
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349 
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351                         /* since 64byte accurate, last 6 bits are not used */
352 
353 
354 
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356 
357 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
361 
362 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
363                                          * Interrupt
364                                          */
365 #define HDSPM_tco_detect         0x08000000
366 #define HDSPM_tco_lock           0x20000000
367 
368 #define HDSPM_s2_tco_detect      0x00000040
369 #define HDSPM_s2_AEBO_D          0x00000080
370 #define HDSPM_s2_AEBI_D          0x00000100
371 
372 
373 #define HDSPM_midi0IRQPending    0x40000000
374 #define HDSPM_midi1IRQPending    0x80000000
375 #define HDSPM_midi2IRQPending    0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending    0x00200000
378 
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381                              HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
391 
392 /* Status2 Register bits */ /* MADI ONLY */
393 
394 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
397 
398 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
400 
401 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
402 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit   for               111=128, 1000=176.4, 1001=192 */
405 
406 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
408 
409 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
412 
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414 
415 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
422 
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
428 
429 
430 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
431                                     HDSPM_SelSyncRef2)
432 #define HDSPM_SelSyncRef_WORD      0
433 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
437                                     HDSPM_SelSyncRef2)
438 
439 /*
440    For AES32, bits for status, status2 and timecode are different
441 */
442 /* status */
443 #define HDSPM_AES32_wcLock      0x0200000
444 #define HDSPM_AES32_wcSync      0x0100000
445 #define HDSPM_AES32_wcFreq_bit  22
446 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
447   HDSPM_bit2freq */
448 #define HDSPM_AES32_syncref_bit  16
449 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
450 
451 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
459 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
460 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
461 
462 /*  status2 */
463 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
464 #define HDSPM_LockAES   0x80
465 #define HDSPM_LockAES1  0x80
466 #define HDSPM_LockAES2  0x40
467 #define HDSPM_LockAES3  0x20
468 #define HDSPM_LockAES4  0x10
469 #define HDSPM_LockAES5  0x8
470 #define HDSPM_LockAES6  0x4
471 #define HDSPM_LockAES7  0x2
472 #define HDSPM_LockAES8  0x1
473 /*
474    Timecode
475    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
476    AES i+1
477  bits 3210
478       0001  32kHz
479       0010  44.1kHz
480       0011  48kHz
481       0100  64kHz
482       0101  88.2kHz
483       0110  96kHz
484       0111  128kHz
485       1000  176.4kHz
486       1001  192kHz
487   NB: Timecode register doesn't seem to work on AES32 card revision 230
488 */
489 
490 /* Mixer Values */
491 #define UNITY_GAIN          32768       /* = 65536/2 */
492 #define MINUS_INFINITY_GAIN 0
493 
494 /* Number of channels for different Speed Modes */
495 #define MADI_SS_CHANNELS       64
496 #define MADI_DS_CHANNELS       32
497 #define MADI_QS_CHANNELS       16
498 
499 #define RAYDAT_SS_CHANNELS     36
500 #define RAYDAT_DS_CHANNELS     20
501 #define RAYDAT_QS_CHANNELS     12
502 
503 #define AIO_IN_SS_CHANNELS        14
504 #define AIO_IN_DS_CHANNELS        10
505 #define AIO_IN_QS_CHANNELS        8
506 #define AIO_OUT_SS_CHANNELS        16
507 #define AIO_OUT_DS_CHANNELS        12
508 #define AIO_OUT_QS_CHANNELS        10
509 
510 #define AES32_CHANNELS          16
511 
512 /* the size of a substream (1 mono data stream) */
513 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
514 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
515 
516 /* the size of the area we need to allocate for DMA transfers. the
517    size is the same regardless of the number of channels, and
518    also the latency to use.
519    for one direction !!!
520 */
521 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
522 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
523 
524 #define HDSPM_RAYDAT_REV        211
525 #define HDSPM_AIO_REV           212
526 #define HDSPM_MADIFACE_REV      213
527 
528 /* speed factor modes */
529 #define HDSPM_SPEED_SINGLE 0
530 #define HDSPM_SPEED_DOUBLE 1
531 #define HDSPM_SPEED_QUAD   2
532 
533 /* names for speed modes */
534 static char *hdspm_speed_names[] = { "single", "double", "quad" };
535 
536 static char *texts_autosync_aes_tco[] = { "Word Clock",
537                                           "AES1", "AES2", "AES3", "AES4",
538                                           "AES5", "AES6", "AES7", "AES8",
539                                           "TCO" };
540 static char *texts_autosync_aes[] = { "Word Clock",
541                                       "AES1", "AES2", "AES3", "AES4",
542                                       "AES5", "AES6", "AES7", "AES8" };
543 static char *texts_autosync_madi_tco[] = { "Word Clock",
544                                            "MADI", "TCO", "Sync In" };
545 static char *texts_autosync_madi[] = { "Word Clock",
546                                        "MADI", "Sync In" };
547 
548 static char *texts_autosync_raydat_tco[] = {
549         "Word Clock",
550         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
551         "AES", "SPDIF", "TCO", "Sync In"
552 };
553 static char *texts_autosync_raydat[] = {
554         "Word Clock",
555         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
556         "AES", "SPDIF", "Sync In"
557 };
558 static char *texts_autosync_aio_tco[] = {
559         "Word Clock",
560         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
561 };
562 static char *texts_autosync_aio[] = { "Word Clock",
563                                       "ADAT", "AES", "SPDIF", "Sync In" };
564 
565 static char *texts_freq[] = {
566         "No Lock",
567         "32 kHz",
568         "44.1 kHz",
569         "48 kHz",
570         "64 kHz",
571         "88.2 kHz",
572         "96 kHz",
573         "128 kHz",
574         "176.4 kHz",
575         "192 kHz"
576 };
577 
578 static char *texts_ports_madi[] = {
579         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
580         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
581         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
582         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
583         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
584         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
585         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
586         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
587         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
588         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
589         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
590 };
591 
592 
593 static char *texts_ports_raydat_ss[] = {
594         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
595         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
596         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
597         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
598         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
599         "ADAT4.7", "ADAT4.8",
600         "AES.L", "AES.R",
601         "SPDIF.L", "SPDIF.R"
602 };
603 
604 static char *texts_ports_raydat_ds[] = {
605         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
606         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
607         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
608         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
609         "AES.L", "AES.R",
610         "SPDIF.L", "SPDIF.R"
611 };
612 
613 static char *texts_ports_raydat_qs[] = {
614         "ADAT1.1", "ADAT1.2",
615         "ADAT2.1", "ADAT2.2",
616         "ADAT3.1", "ADAT3.2",
617         "ADAT4.1", "ADAT4.2",
618         "AES.L", "AES.R",
619         "SPDIF.L", "SPDIF.R"
620 };
621 
622 
623 static char *texts_ports_aio_in_ss[] = {
624         "Analogue.L", "Analogue.R",
625         "AES.L", "AES.R",
626         "SPDIF.L", "SPDIF.R",
627         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
628         "ADAT.7", "ADAT.8"
629 };
630 
631 static char *texts_ports_aio_out_ss[] = {
632         "Analogue.L", "Analogue.R",
633         "AES.L", "AES.R",
634         "SPDIF.L", "SPDIF.R",
635         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
636         "ADAT.7", "ADAT.8",
637         "Phone.L", "Phone.R"
638 };
639 
640 static char *texts_ports_aio_in_ds[] = {
641         "Analogue.L", "Analogue.R",
642         "AES.L", "AES.R",
643         "SPDIF.L", "SPDIF.R",
644         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
645 };
646 
647 static char *texts_ports_aio_out_ds[] = {
648         "Analogue.L", "Analogue.R",
649         "AES.L", "AES.R",
650         "SPDIF.L", "SPDIF.R",
651         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
652         "Phone.L", "Phone.R"
653 };
654 
655 static char *texts_ports_aio_in_qs[] = {
656         "Analogue.L", "Analogue.R",
657         "AES.L", "AES.R",
658         "SPDIF.L", "SPDIF.R",
659         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
660 };
661 
662 static char *texts_ports_aio_out_qs[] = {
663         "Analogue.L", "Analogue.R",
664         "AES.L", "AES.R",
665         "SPDIF.L", "SPDIF.R",
666         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
667         "Phone.L", "Phone.R"
668 };
669 
670 static char *texts_ports_aes32[] = {
671         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
672         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
673         "AES.15", "AES.16"
674 };
675 
676 /* These tables map the ALSA channels 1..N to the channels that we
677    need to use in order to find the relevant channel buffer. RME
678    refers to this kind of mapping as between "the ADAT channel and
679    the DMA channel." We index it using the logical audio channel,
680    and the value is the DMA channel (i.e. channel buffer number)
681    where the data for that channel can be read/written from/to.
682 */
683 
684 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
685         0, 1, 2, 3, 4, 5, 6, 7,
686         8, 9, 10, 11, 12, 13, 14, 15,
687         16, 17, 18, 19, 20, 21, 22, 23,
688         24, 25, 26, 27, 28, 29, 30, 31,
689         32, 33, 34, 35, 36, 37, 38, 39,
690         40, 41, 42, 43, 44, 45, 46, 47,
691         48, 49, 50, 51, 52, 53, 54, 55,
692         56, 57, 58, 59, 60, 61, 62, 63
693 };
694 
695 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
696         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
697         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
698         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
699         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
700         0, 1,                   /* AES */
701         2, 3,                   /* SPDIF */
702         -1, -1, -1, -1,
703         -1, -1, -1, -1, -1, -1, -1, -1,
704         -1, -1, -1, -1, -1, -1, -1, -1,
705         -1, -1, -1, -1, -1, -1, -1, -1,
706 };
707 
708 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
709         4, 5, 6, 7,             /* ADAT 1 */
710         8, 9, 10, 11,           /* ADAT 2 */
711         12, 13, 14, 15,         /* ADAT 3 */
712         16, 17, 18, 19,         /* ADAT 4 */
713         0, 1,                   /* AES */
714         2, 3,                   /* SPDIF */
715         -1, -1, -1, -1,
716         -1, -1, -1, -1, -1, -1, -1, -1,
717         -1, -1, -1, -1, -1, -1, -1, -1,
718         -1, -1, -1, -1, -1, -1, -1, -1,
719         -1, -1, -1, -1, -1, -1, -1, -1,
720         -1, -1, -1, -1, -1, -1, -1, -1,
721 };
722 
723 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
724         4, 5,                   /* ADAT 1 */
725         6, 7,                   /* ADAT 2 */
726         8, 9,                   /* ADAT 3 */
727         10, 11,                 /* ADAT 4 */
728         0, 1,                   /* AES */
729         2, 3,                   /* SPDIF */
730         -1, -1, -1, -1,
731         -1, -1, -1, -1, -1, -1, -1, -1,
732         -1, -1, -1, -1, -1, -1, -1, -1,
733         -1, -1, -1, -1, -1, -1, -1, -1,
734         -1, -1, -1, -1, -1, -1, -1, -1,
735         -1, -1, -1, -1, -1, -1, -1, -1,
736         -1, -1, -1, -1, -1, -1, -1, -1,
737 };
738 
739 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
740         0, 1,                   /* line in */
741         8, 9,                   /* aes in, */
742         10, 11,                 /* spdif in */
743         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
744         -1, -1,
745         -1, -1, -1, -1, -1, -1, -1, -1,
746         -1, -1, -1, -1, -1, -1, -1, -1,
747         -1, -1, -1, -1, -1, -1, -1, -1,
748         -1, -1, -1, -1, -1, -1, -1, -1,
749         -1, -1, -1, -1, -1, -1, -1, -1,
750         -1, -1, -1, -1, -1, -1, -1, -1,
751 };
752 
753 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
754         0, 1,                   /* line out */
755         8, 9,                   /* aes out */
756         10, 11,                 /* spdif out */
757         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
758         6, 7,                   /* phone out */
759         -1, -1, -1, -1, -1, -1, -1, -1,
760         -1, -1, -1, -1, -1, -1, -1, -1,
761         -1, -1, -1, -1, -1, -1, -1, -1,
762         -1, -1, -1, -1, -1, -1, -1, -1,
763         -1, -1, -1, -1, -1, -1, -1, -1,
764         -1, -1, -1, -1, -1, -1, -1, -1,
765 };
766 
767 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
768         0, 1,                   /* line in */
769         8, 9,                   /* aes in */
770         10, 11,                 /* spdif in */
771         12, 14, 16, 18,         /* adat in */
772         -1, -1, -1, -1, -1, -1,
773         -1, -1, -1, -1, -1, -1, -1, -1,
774         -1, -1, -1, -1, -1, -1, -1, -1,
775         -1, -1, -1, -1, -1, -1, -1, -1,
776         -1, -1, -1, -1, -1, -1, -1, -1,
777         -1, -1, -1, -1, -1, -1, -1, -1,
778         -1, -1, -1, -1, -1, -1, -1, -1
779 };
780 
781 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
782         0, 1,                   /* line out */
783         8, 9,                   /* aes out */
784         10, 11,                 /* spdif out */
785         12, 14, 16, 18,         /* adat out */
786         6, 7,                   /* phone out */
787         -1, -1, -1, -1,
788         -1, -1, -1, -1, -1, -1, -1, -1,
789         -1, -1, -1, -1, -1, -1, -1, -1,
790         -1, -1, -1, -1, -1, -1, -1, -1,
791         -1, -1, -1, -1, -1, -1, -1, -1,
792         -1, -1, -1, -1, -1, -1, -1, -1,
793         -1, -1, -1, -1, -1, -1, -1, -1
794 };
795 
796 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
797         0, 1,                   /* line in */
798         8, 9,                   /* aes in */
799         10, 11,                 /* spdif in */
800         12, 16,                 /* adat in */
801         -1, -1, -1, -1, -1, -1, -1, -1,
802         -1, -1, -1, -1, -1, -1, -1, -1,
803         -1, -1, -1, -1, -1, -1, -1, -1,
804         -1, -1, -1, -1, -1, -1, -1, -1,
805         -1, -1, -1, -1, -1, -1, -1, -1,
806         -1, -1, -1, -1, -1, -1, -1, -1,
807         -1, -1, -1, -1, -1, -1, -1, -1
808 };
809 
810 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
811         0, 1,                   /* line out */
812         8, 9,                   /* aes out */
813         10, 11,                 /* spdif out */
814         12, 16,                 /* adat out */
815         6, 7,                   /* phone out */
816         -1, -1, -1, -1, -1, -1,
817         -1, -1, -1, -1, -1, -1, -1, -1,
818         -1, -1, -1, -1, -1, -1, -1, -1,
819         -1, -1, -1, -1, -1, -1, -1, -1,
820         -1, -1, -1, -1, -1, -1, -1, -1,
821         -1, -1, -1, -1, -1, -1, -1, -1,
822         -1, -1, -1, -1, -1, -1, -1, -1
823 };
824 
825 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
826         0, 1, 2, 3, 4, 5, 6, 7,
827         8, 9, 10, 11, 12, 13, 14, 15,
828         -1, -1, -1, -1, -1, -1, -1, -1,
829         -1, -1, -1, -1, -1, -1, -1, -1,
830         -1, -1, -1, -1, -1, -1, -1, -1,
831         -1, -1, -1, -1, -1, -1, -1, -1,
832         -1, -1, -1, -1, -1, -1, -1, -1,
833         -1, -1, -1, -1, -1, -1, -1, -1
834 };
835 
836 struct hdspm_midi {
837         struct hdspm *hdspm;
838         int id;
839         struct snd_rawmidi *rmidi;
840         struct snd_rawmidi_substream *input;
841         struct snd_rawmidi_substream *output;
842         char istimer;           /* timer in use */
843         struct timer_list timer;
844         spinlock_t lock;
845         int pending;
846         int dataIn;
847         int statusIn;
848         int dataOut;
849         int statusOut;
850         int ie;
851         int irq;
852 };
853 
854 struct hdspm_tco {
855         int input;
856         int framerate;
857         int wordclock;
858         int samplerate;
859         int pull;
860         int term; /* 0 = off, 1 = on */
861 };
862 
863 struct hdspm {
864         spinlock_t lock;
865         /* only one playback and/or capture stream */
866         struct snd_pcm_substream *capture_substream;
867         struct snd_pcm_substream *playback_substream;
868 
869         char *card_name;             /* for procinfo */
870         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
871 
872         uint8_t io_type;
873 
874         int monitor_outs;       /* set up monitoring outs init flag */
875 
876         u32 control_register;   /* cached value */
877         u32 control2_register;  /* cached value */
878         u32 settings_register;
879 
880         struct hdspm_midi midi[4];
881         struct tasklet_struct midi_tasklet;
882 
883         size_t period_bytes;
884         unsigned char ss_in_channels;
885         unsigned char ds_in_channels;
886         unsigned char qs_in_channels;
887         unsigned char ss_out_channels;
888         unsigned char ds_out_channels;
889         unsigned char qs_out_channels;
890 
891         unsigned char max_channels_in;
892         unsigned char max_channels_out;
893 
894         signed char *channel_map_in;
895         signed char *channel_map_out;
896 
897         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
898         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
899 
900         char **port_names_in;
901         char **port_names_out;
902 
903         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
904         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
905 
906         unsigned char *playback_buffer; /* suitably aligned address */
907         unsigned char *capture_buffer;  /* suitably aligned address */
908 
909         pid_t capture_pid;      /* process id which uses capture */
910         pid_t playback_pid;     /* process id which uses capture */
911         int running;            /* running status */
912 
913         int last_external_sample_rate;  /* samplerate mystic ... */
914         int last_internal_sample_rate;
915         int system_sample_rate;
916 
917         int dev;                /* Hardware vars... */
918         int irq;
919         unsigned long port;
920         void __iomem *iobase;
921 
922         int irq_count;          /* for debug */
923         int midiPorts;
924 
925         struct snd_card *card;  /* one card */
926         struct snd_pcm *pcm;            /* has one pcm */
927         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
928         struct pci_dev *pci;    /* and an pci info */
929 
930         /* Mixer vars */
931         /* fast alsa mixer */
932         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
933         /* but input to much, so not used */
934         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
935         /* full mixer accessible over mixer ioctl or hwdep-device */
936         struct hdspm_mixer *mixer;
937 
938         struct hdspm_tco *tco;  /* NULL if no TCO detected */
939 
940         char **texts_autosync;
941         int texts_autosync_items;
942 
943         cycles_t last_interrupt;
944 
945         unsigned int serial;
946 
947         struct hdspm_peak_rms peak_rms;
948 };
949 
950 
951 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
952         {
953          .vendor = PCI_VENDOR_ID_XILINX,
954          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
955          .subvendor = PCI_ANY_ID,
956          .subdevice = PCI_ANY_ID,
957          .class = 0,
958          .class_mask = 0,
959          .driver_data = 0},
960         {0,}
961 };
962 
963 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
964 
965 /* prototypes */
966 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
967                                          struct hdspm *hdspm);
968 static int snd_hdspm_create_pcm(struct snd_card *card,
969                                 struct hdspm *hdspm);
970 
971 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
972 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
973 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
974 static int hdspm_autosync_ref(struct hdspm *hdspm);
975 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
976 static int hdspm_system_clock_mode(struct hdspm *hdspm);
977 static void hdspm_set_sgbuf(struct hdspm *hdspm,
978                             struct snd_pcm_substream *substream,
979                              unsigned int reg, int channels);
980 
981 static inline int HDSPM_bit2freq(int n)
982 {
983         static const int bit2freq_tab[] = {
984                 0, 32000, 44100, 48000, 64000, 88200,
985                 96000, 128000, 176400, 192000 };
986         if (n < 1 || n > 9)
987                 return 0;
988         return bit2freq_tab[n];
989 }
990 
991 /* Write/read to/from HDSPM with Adresses in Bytes
992    not words but only 32Bit writes are allowed */
993 
994 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
995                                unsigned int val)
996 {
997         writel(val, hdspm->iobase + reg);
998 }
999 
1000 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1001 {
1002         return readl(hdspm->iobase + reg);
1003 }
1004 
1005 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1006    mixer is write only on hardware so we have to cache him for read
1007    each fader is a u32, but uses only the first 16 bit */
1008 
1009 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1010                                      unsigned int in)
1011 {
1012         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1013                 return 0;
1014 
1015         return hdspm->mixer->ch[chan].in[in];
1016 }
1017 
1018 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1019                                      unsigned int pb)
1020 {
1021         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1022                 return 0;
1023         return hdspm->mixer->ch[chan].pb[pb];
1024 }
1025 
1026 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1027                                       unsigned int in, unsigned short data)
1028 {
1029         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1030                 return -1;
1031 
1032         hdspm_write(hdspm,
1033                     HDSPM_MADI_mixerBase +
1034                     ((in + 128 * chan) * sizeof(u32)),
1035                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1036         return 0;
1037 }
1038 
1039 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1040                                       unsigned int pb, unsigned short data)
1041 {
1042         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1043                 return -1;
1044 
1045         hdspm_write(hdspm,
1046                     HDSPM_MADI_mixerBase +
1047                     ((64 + pb + 128 * chan) * sizeof(u32)),
1048                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1049         return 0;
1050 }
1051 
1052 
1053 /* enable DMA for specific channels, now available for DSP-MADI */
1054 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1055 {
1056         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1057 }
1058 
1059 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1060 {
1061         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1062 }
1063 
1064 /* check if same process is writing and reading */
1065 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1066 {
1067         unsigned long flags;
1068         int ret = 1;
1069 
1070         spin_lock_irqsave(&hdspm->lock, flags);
1071         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1072             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1073                 ret = 0;
1074         }
1075         spin_unlock_irqrestore(&hdspm->lock, flags);
1076         return ret;
1077 }
1078 
1079 /* round arbitary sample rates to commonly known rates */
1080 static int hdspm_round_frequency(int rate)
1081 {
1082         if (rate < 38050)
1083                 return 32000;
1084         if (rate < 46008)
1085                 return 44100;
1086         else
1087                 return 48000;
1088 }
1089 
1090 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1091 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1092 
1093 /* check for external sample rate */
1094 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1095 {
1096         unsigned int status, status2, timecode;
1097         int syncref, rate = 0, rate_bits;
1098 
1099         switch (hdspm->io_type) {
1100         case AES32:
1101                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1102                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1103                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1104 
1105                 syncref = hdspm_autosync_ref(hdspm);
1106 
1107                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1108                                 status & HDSPM_AES32_wcLock)
1109                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1110 
1111                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1112                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1113                                 status2 & (HDSPM_LockAES >>
1114                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1115                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1116                 return 0;
1117                 break;
1118 
1119         case MADIface:
1120                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1121 
1122                 if (!(status & HDSPM_madiLock)) {
1123                         rate = 0;  /* no lock */
1124                 } else {
1125                         switch (status & (HDSPM_status1_freqMask)) {
1126                         case HDSPM_status1_F_0*1:
1127                                 rate = 32000; break;
1128                         case HDSPM_status1_F_0*2:
1129                                 rate = 44100; break;
1130                         case HDSPM_status1_F_0*3:
1131                                 rate = 48000; break;
1132                         case HDSPM_status1_F_0*4:
1133                                 rate = 64000; break;
1134                         case HDSPM_status1_F_0*5:
1135                                 rate = 88200; break;
1136                         case HDSPM_status1_F_0*6:
1137                                 rate = 96000; break;
1138                         case HDSPM_status1_F_0*7:
1139                                 rate = 128000; break;
1140                         case HDSPM_status1_F_0*8:
1141                                 rate = 176400; break;
1142                         case HDSPM_status1_F_0*9:
1143                                 rate = 192000; break;
1144                         default:
1145                                 rate = 0; break;
1146                         }
1147                 }
1148 
1149                 break;
1150 
1151         case MADI:
1152         case AIO:
1153         case RayDAT:
1154                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1155                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1156                 rate = 0;
1157 
1158                 /* if wordclock has synced freq and wordclock is valid */
1159                 if ((status2 & HDSPM_wcLock) != 0 &&
1160                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1161 
1162                         rate_bits = status2 & HDSPM_wcFreqMask;
1163 
1164 
1165                         switch (rate_bits) {
1166                         case HDSPM_wcFreq32:
1167                                 rate = 32000;
1168                                 break;
1169                         case HDSPM_wcFreq44_1:
1170                                 rate = 44100;
1171                                 break;
1172                         case HDSPM_wcFreq48:
1173                                 rate = 48000;
1174                                 break;
1175                         case HDSPM_wcFreq64:
1176                                 rate = 64000;
1177                                 break;
1178                         case HDSPM_wcFreq88_2:
1179                                 rate = 88200;
1180                                 break;
1181                         case HDSPM_wcFreq96:
1182                                 rate = 96000;
1183                                 break;
1184                         default:
1185                                 rate = 0;
1186                                 break;
1187                         }
1188                 }
1189 
1190                 /* if rate detected and Syncref is Word than have it,
1191                  * word has priority to MADI
1192                  */
1193                 if (rate != 0 &&
1194                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1195                         return rate;
1196 
1197                 /* maybe a madi input (which is taken if sel sync is madi) */
1198                 if (status & HDSPM_madiLock) {
1199                         rate_bits = status & HDSPM_madiFreqMask;
1200 
1201                         switch (rate_bits) {
1202                         case HDSPM_madiFreq32:
1203                                 rate = 32000;
1204                                 break;
1205                         case HDSPM_madiFreq44_1:
1206                                 rate = 44100;
1207                                 break;
1208                         case HDSPM_madiFreq48:
1209                                 rate = 48000;
1210                                 break;
1211                         case HDSPM_madiFreq64:
1212                                 rate = 64000;
1213                                 break;
1214                         case HDSPM_madiFreq88_2:
1215                                 rate = 88200;
1216                                 break;
1217                         case HDSPM_madiFreq96:
1218                                 rate = 96000;
1219                                 break;
1220                         case HDSPM_madiFreq128:
1221                                 rate = 128000;
1222                                 break;
1223                         case HDSPM_madiFreq176_4:
1224                                 rate = 176400;
1225                                 break;
1226                         case HDSPM_madiFreq192:
1227                                 rate = 192000;
1228                                 break;
1229                         default:
1230                                 rate = 0;
1231                                 break;
1232                         }
1233 
1234                 } /* endif HDSPM_madiLock */
1235 
1236                 /* check sample rate from TCO or SYNC_IN */
1237                 {
1238                         bool is_valid_input = 0;
1239                         bool has_sync = 0;
1240 
1241                         syncref = hdspm_autosync_ref(hdspm);
1242                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1243                                 is_valid_input = 1;
1244                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1245                                         hdspm_tco_sync_check(hdspm));
1246                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1247                                 is_valid_input = 1;
1248                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1249                                         hdspm_sync_in_sync_check(hdspm));
1250                         }
1251 
1252                         if (is_valid_input && has_sync) {
1253                                 rate = hdspm_round_frequency(
1254                                         hdspm_get_pll_freq(hdspm));
1255                         }
1256                 }
1257 
1258                 /* QS and DS rates normally can not be detected
1259                  * automatically by the card. Only exception is MADI
1260                  * in 96k frame mode.
1261                  *
1262                  * So if we read SS values (32 .. 48k), check for
1263                  * user-provided DS/QS bits in the control register
1264                  * and multiply the base frequency accordingly.
1265                  */
1266                 if (rate <= 48000) {
1267                         if (hdspm->control_register & HDSPM_QuadSpeed)
1268                                 rate *= 4;
1269                         else if (hdspm->control_register &
1270                                         HDSPM_DoubleSpeed)
1271                                 rate *= 2;
1272                 }
1273                 break;
1274         }
1275 
1276         return rate;
1277 }
1278 
1279 /* return latency in samples per period */
1280 static int hdspm_get_latency(struct hdspm *hdspm)
1281 {
1282         int n;
1283 
1284         n = hdspm_decode_latency(hdspm->control_register);
1285 
1286         /* Special case for new RME cards with 32 samples period size.
1287          * The three latency bits in the control register
1288          * (HDSP_LatencyMask) encode latency values of 64 samples as
1289          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1290          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1291          * it corresponds to 32 samples.
1292          */
1293         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1294                 n = -1;
1295 
1296         return 1 << (n + 6);
1297 }
1298 
1299 /* Latency function */
1300 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1301 {
1302         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1303 }
1304 
1305 
1306 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1307 {
1308         int position;
1309 
1310         position = hdspm_read(hdspm, HDSPM_statusRegister);
1311 
1312         switch (hdspm->io_type) {
1313         case RayDAT:
1314         case AIO:
1315                 position &= HDSPM_BufferPositionMask;
1316                 position /= 4; /* Bytes per sample */
1317                 break;
1318         default:
1319                 position = (position & HDSPM_BufferID) ?
1320                         (hdspm->period_bytes / 4) : 0;
1321         }
1322 
1323         return position;
1324 }
1325 
1326 
1327 static inline void hdspm_start_audio(struct hdspm * s)
1328 {
1329         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1330         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1331 }
1332 
1333 static inline void hdspm_stop_audio(struct hdspm * s)
1334 {
1335         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1336         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1337 }
1338 
1339 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1340 static void hdspm_silence_playback(struct hdspm *hdspm)
1341 {
1342         int i;
1343         int n = hdspm->period_bytes;
1344         void *buf = hdspm->playback_buffer;
1345 
1346         if (buf == NULL)
1347                 return;
1348 
1349         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1350                 memset(buf, 0, n);
1351                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1352         }
1353 }
1354 
1355 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1356 {
1357         int n;
1358 
1359         spin_lock_irq(&s->lock);
1360 
1361         if (32 == frames) {
1362                 /* Special case for new RME cards like RayDAT/AIO which
1363                  * support period sizes of 32 samples. Since latency is
1364                  * encoded in the three bits of HDSP_LatencyMask, we can only
1365                  * have values from 0 .. 7. While 0 still means 64 samples and
1366                  * 6 represents 4096 samples on all cards, 7 represents 8192
1367                  * on older cards and 32 samples on new cards.
1368                  *
1369                  * In other words, period size in samples is calculated by
1370                  * 2^(n+6) with n ranging from 0 .. 7.
1371                  */
1372                 n = 7;
1373         } else {
1374                 frames >>= 7;
1375                 n = 0;
1376                 while (frames) {
1377                         n++;
1378                         frames >>= 1;
1379                 }
1380         }
1381 
1382         s->control_register &= ~HDSPM_LatencyMask;
1383         s->control_register |= hdspm_encode_latency(n);
1384 
1385         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1386 
1387         hdspm_compute_period_size(s);
1388 
1389         spin_unlock_irq(&s->lock);
1390 
1391         return 0;
1392 }
1393 
1394 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1395 {
1396         u64 freq_const;
1397 
1398         if (period == 0)
1399                 return 0;
1400 
1401         switch (hdspm->io_type) {
1402         case MADI:
1403         case AES32:
1404                 freq_const = 110069313433624ULL;
1405                 break;
1406         case RayDAT:
1407         case AIO:
1408                 freq_const = 104857600000000ULL;
1409                 break;
1410         case MADIface:
1411                 freq_const = 131072000000000ULL;
1412                 break;
1413         default:
1414                 snd_BUG();
1415                 return 0;
1416         }
1417 
1418         return div_u64(freq_const, period);
1419 }
1420 
1421 
1422 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1423 {
1424         u64 n;
1425 
1426         if (snd_BUG_ON(rate <= 0))
1427                 return;
1428 
1429         if (rate >= 112000)
1430                 rate /= 4;
1431         else if (rate >= 56000)
1432                 rate /= 2;
1433 
1434         switch (hdspm->io_type) {
1435         case MADIface:
1436                 n = 131072000000000ULL;  /* 125 MHz */
1437                 break;
1438         case MADI:
1439         case AES32:
1440                 n = 110069313433624ULL;  /* 105 MHz */
1441                 break;
1442         case RayDAT:
1443         case AIO:
1444                 n = 104857600000000ULL;  /* 100 MHz */
1445                 break;
1446         default:
1447                 snd_BUG();
1448                 return;
1449         }
1450 
1451         n = div_u64(n, rate);
1452         /* n should be less than 2^32 for being written to FREQ register */
1453         snd_BUG_ON(n >> 32);
1454         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1455 }
1456 
1457 /* dummy set rate lets see what happens */
1458 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1459 {
1460         int current_rate;
1461         int rate_bits;
1462         int not_set = 0;
1463         int current_speed, target_speed;
1464 
1465         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1466            it (e.g. during module initialization).
1467          */
1468 
1469         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1470 
1471                 /* SLAVE --- */
1472                 if (called_internally) {
1473 
1474                         /* request from ctl or card initialization
1475                            just make a warning an remember setting
1476                            for future master mode switching */
1477 
1478                         snd_printk(KERN_WARNING "HDSPM: "
1479                                    "Warning: device is not running "
1480                                    "as a clock master.\n");
1481                         not_set = 1;
1482                 } else {
1483 
1484                         /* hw_param request while in AutoSync mode */
1485                         int external_freq =
1486                             hdspm_external_sample_rate(hdspm);
1487 
1488                         if (hdspm_autosync_ref(hdspm) ==
1489                             HDSPM_AUTOSYNC_FROM_NONE) {
1490 
1491                                 snd_printk(KERN_WARNING "HDSPM: "
1492                                            "Detected no Externel Sync \n");
1493                                 not_set = 1;
1494 
1495                         } else if (rate != external_freq) {
1496 
1497                                 snd_printk(KERN_WARNING "HDSPM: "
1498                                            "Warning: No AutoSync source for "
1499                                            "requested rate\n");
1500                                 not_set = 1;
1501                         }
1502                 }
1503         }
1504 
1505         current_rate = hdspm->system_sample_rate;
1506 
1507         /* Changing between Singe, Double and Quad speed is not
1508            allowed if any substreams are open. This is because such a change
1509            causes a shift in the location of the DMA buffers and a reduction
1510            in the number of available buffers.
1511 
1512            Note that a similar but essentially insoluble problem exists for
1513            externally-driven rate changes. All we can do is to flag rate
1514            changes in the read/write routines.
1515          */
1516 
1517         if (current_rate <= 48000)
1518                 current_speed = HDSPM_SPEED_SINGLE;
1519         else if (current_rate <= 96000)
1520                 current_speed = HDSPM_SPEED_DOUBLE;
1521         else
1522                 current_speed = HDSPM_SPEED_QUAD;
1523 
1524         if (rate <= 48000)
1525                 target_speed = HDSPM_SPEED_SINGLE;
1526         else if (rate <= 96000)
1527                 target_speed = HDSPM_SPEED_DOUBLE;
1528         else
1529                 target_speed = HDSPM_SPEED_QUAD;
1530 
1531         switch (rate) {
1532         case 32000:
1533                 rate_bits = HDSPM_Frequency32KHz;
1534                 break;
1535         case 44100:
1536                 rate_bits = HDSPM_Frequency44_1KHz;
1537                 break;
1538         case 48000:
1539                 rate_bits = HDSPM_Frequency48KHz;
1540                 break;
1541         case 64000:
1542                 rate_bits = HDSPM_Frequency64KHz;
1543                 break;
1544         case 88200:
1545                 rate_bits = HDSPM_Frequency88_2KHz;
1546                 break;
1547         case 96000:
1548                 rate_bits = HDSPM_Frequency96KHz;
1549                 break;
1550         case 128000:
1551                 rate_bits = HDSPM_Frequency128KHz;
1552                 break;
1553         case 176400:
1554                 rate_bits = HDSPM_Frequency176_4KHz;
1555                 break;
1556         case 192000:
1557                 rate_bits = HDSPM_Frequency192KHz;
1558                 break;
1559         default:
1560                 return -EINVAL;
1561         }
1562 
1563         if (current_speed != target_speed
1564             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1565                 snd_printk
1566                     (KERN_ERR "HDSPM: "
1567                      "cannot change from %s speed to %s speed mode "
1568                      "(capture PID = %d, playback PID = %d)\n",
1569                      hdspm_speed_names[current_speed],
1570                      hdspm_speed_names[target_speed],
1571                      hdspm->capture_pid, hdspm->playback_pid);
1572                 return -EBUSY;
1573         }
1574 
1575         hdspm->control_register &= ~HDSPM_FrequencyMask;
1576         hdspm->control_register |= rate_bits;
1577         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1578 
1579         /* For AES32, need to set DDS value in FREQ register
1580            For MADI, also apparently */
1581         hdspm_set_dds_value(hdspm, rate);
1582 
1583         if (AES32 == hdspm->io_type && rate != current_rate)
1584                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1585 
1586         hdspm->system_sample_rate = rate;
1587 
1588         if (rate <= 48000) {
1589                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1590                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1591                 hdspm->max_channels_in = hdspm->ss_in_channels;
1592                 hdspm->max_channels_out = hdspm->ss_out_channels;
1593                 hdspm->port_names_in = hdspm->port_names_in_ss;
1594                 hdspm->port_names_out = hdspm->port_names_out_ss;
1595         } else if (rate <= 96000) {
1596                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1597                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1598                 hdspm->max_channels_in = hdspm->ds_in_channels;
1599                 hdspm->max_channels_out = hdspm->ds_out_channels;
1600                 hdspm->port_names_in = hdspm->port_names_in_ds;
1601                 hdspm->port_names_out = hdspm->port_names_out_ds;
1602         } else {
1603                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1604                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1605                 hdspm->max_channels_in = hdspm->qs_in_channels;
1606                 hdspm->max_channels_out = hdspm->qs_out_channels;
1607                 hdspm->port_names_in = hdspm->port_names_in_qs;
1608                 hdspm->port_names_out = hdspm->port_names_out_qs;
1609         }
1610 
1611         if (not_set != 0)
1612                 return -1;
1613 
1614         return 0;
1615 }
1616 
1617 /* mainly for init to 0 on load */
1618 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1619 {
1620         int i, j;
1621         unsigned int gain;
1622 
1623         if (sgain > UNITY_GAIN)
1624                 gain = UNITY_GAIN;
1625         else if (sgain < 0)
1626                 gain = 0;
1627         else
1628                 gain = sgain;
1629 
1630         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1631                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1632                         hdspm_write_in_gain(hdspm, i, j, gain);
1633                         hdspm_write_pb_gain(hdspm, i, j, gain);
1634                 }
1635 }
1636 
1637 /*----------------------------------------------------------------------------
1638    MIDI
1639   ----------------------------------------------------------------------------*/
1640 
1641 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1642                                                       int id)
1643 {
1644         /* the hardware already does the relevant bit-mask with 0xff */
1645         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1646 }
1647 
1648 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1649                                               int val)
1650 {
1651         /* the hardware already does the relevant bit-mask with 0xff */
1652         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1653 }
1654 
1655 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1656 {
1657         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1658 }
1659 
1660 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1661 {
1662         int fifo_bytes_used;
1663 
1664         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1665 
1666         if (fifo_bytes_used < 128)
1667                 return  128 - fifo_bytes_used;
1668         else
1669                 return 0;
1670 }
1671 
1672 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1673 {
1674         while (snd_hdspm_midi_input_available (hdspm, id))
1675                 snd_hdspm_midi_read_byte (hdspm, id);
1676 }
1677 
1678 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1679 {
1680         unsigned long flags;
1681         int n_pending;
1682         int to_write;
1683         int i;
1684         unsigned char buf[128];
1685 
1686         /* Output is not interrupt driven */
1687 
1688         spin_lock_irqsave (&hmidi->lock, flags);
1689         if (hmidi->output &&
1690             !snd_rawmidi_transmit_empty (hmidi->output)) {
1691                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1692                                                             hmidi->id);
1693                 if (n_pending > 0) {
1694                         if (n_pending > (int)sizeof (buf))
1695                                 n_pending = sizeof (buf);
1696 
1697                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1698                                                          n_pending);
1699                         if (to_write > 0) {
1700                                 for (i = 0; i < to_write; ++i)
1701                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1702                                                                    hmidi->id,
1703                                                                    buf[i]);
1704                         }
1705                 }
1706         }
1707         spin_unlock_irqrestore (&hmidi->lock, flags);
1708         return 0;
1709 }
1710 
1711 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1712 {
1713         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1714                                  * input FIFO size
1715                                  */
1716         unsigned long flags;
1717         int n_pending;
1718         int i;
1719 
1720         spin_lock_irqsave (&hmidi->lock, flags);
1721         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1722         if (n_pending > 0) {
1723                 if (hmidi->input) {
1724                         if (n_pending > (int)sizeof (buf))
1725                                 n_pending = sizeof (buf);
1726                         for (i = 0; i < n_pending; ++i)
1727                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1728                                                                    hmidi->id);
1729                         if (n_pending)
1730                                 snd_rawmidi_receive (hmidi->input, buf,
1731                                                      n_pending);
1732                 } else {
1733                         /* flush the MIDI input FIFO */
1734                         while (n_pending--)
1735                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1736                                                           hmidi->id);
1737                 }
1738         }
1739         hmidi->pending = 0;
1740         spin_unlock_irqrestore(&hmidi->lock, flags);
1741 
1742         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1743         hmidi->hdspm->control_register |= hmidi->ie;
1744         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1745                     hmidi->hdspm->control_register);
1746         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1747 
1748         return snd_hdspm_midi_output_write (hmidi);
1749 }
1750 
1751 static void
1752 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1753 {
1754         struct hdspm *hdspm;
1755         struct hdspm_midi *hmidi;
1756         unsigned long flags;
1757 
1758         hmidi = substream->rmidi->private_data;
1759         hdspm = hmidi->hdspm;
1760 
1761         spin_lock_irqsave (&hdspm->lock, flags);
1762         if (up) {
1763                 if (!(hdspm->control_register & hmidi->ie)) {
1764                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1765                         hdspm->control_register |= hmidi->ie;
1766                 }
1767         } else {
1768                 hdspm->control_register &= ~hmidi->ie;
1769         }
1770 
1771         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1772         spin_unlock_irqrestore (&hdspm->lock, flags);
1773 }
1774 
1775 static void snd_hdspm_midi_output_timer(unsigned long data)
1776 {
1777         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1778         unsigned long flags;
1779 
1780         snd_hdspm_midi_output_write(hmidi);
1781         spin_lock_irqsave (&hmidi->lock, flags);
1782 
1783         /* this does not bump hmidi->istimer, because the
1784            kernel automatically removed the timer when it
1785            expired, and we are now adding it back, thus
1786            leaving istimer wherever it was set before.
1787         */
1788 
1789         if (hmidi->istimer) {
1790                 hmidi->timer.expires = 1 + jiffies;
1791                 add_timer(&hmidi->timer);
1792         }
1793 
1794         spin_unlock_irqrestore (&hmidi->lock, flags);
1795 }
1796 
1797 static void
1798 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1799 {
1800         struct hdspm_midi *hmidi;
1801         unsigned long flags;
1802 
1803         hmidi = substream->rmidi->private_data;
1804         spin_lock_irqsave (&hmidi->lock, flags);
1805         if (up) {
1806                 if (!hmidi->istimer) {
1807                         init_timer(&hmidi->timer);
1808                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1809                         hmidi->timer.data = (unsigned long) hmidi;
1810                         hmidi->timer.expires = 1 + jiffies;
1811                         add_timer(&hmidi->timer);
1812                         hmidi->istimer++;
1813                 }
1814         } else {
1815                 if (hmidi->istimer && --hmidi->istimer <= 0)
1816                         del_timer (&hmidi->timer);
1817         }
1818         spin_unlock_irqrestore (&hmidi->lock, flags);
1819         if (up)
1820                 snd_hdspm_midi_output_write(hmidi);
1821 }
1822 
1823 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1824 {
1825         struct hdspm_midi *hmidi;
1826 
1827         hmidi = substream->rmidi->private_data;
1828         spin_lock_irq (&hmidi->lock);
1829         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1830         hmidi->input = substream;
1831         spin_unlock_irq (&hmidi->lock);
1832 
1833         return 0;
1834 }
1835 
1836 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1837 {
1838         struct hdspm_midi *hmidi;
1839 
1840         hmidi = substream->rmidi->private_data;
1841         spin_lock_irq (&hmidi->lock);
1842         hmidi->output = substream;
1843         spin_unlock_irq (&hmidi->lock);
1844 
1845         return 0;
1846 }
1847 
1848 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1849 {
1850         struct hdspm_midi *hmidi;
1851 
1852         snd_hdspm_midi_input_trigger (substream, 0);
1853 
1854         hmidi = substream->rmidi->private_data;
1855         spin_lock_irq (&hmidi->lock);
1856         hmidi->input = NULL;
1857         spin_unlock_irq (&hmidi->lock);
1858 
1859         return 0;
1860 }
1861 
1862 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1863 {
1864         struct hdspm_midi *hmidi;
1865 
1866         snd_hdspm_midi_output_trigger (substream, 0);
1867 
1868         hmidi = substream->rmidi->private_data;
1869         spin_lock_irq (&hmidi->lock);
1870         hmidi->output = NULL;
1871         spin_unlock_irq (&hmidi->lock);
1872 
1873         return 0;
1874 }
1875 
1876 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1877 {
1878         .open =         snd_hdspm_midi_output_open,
1879         .close =        snd_hdspm_midi_output_close,
1880         .trigger =      snd_hdspm_midi_output_trigger,
1881 };
1882 
1883 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1884 {
1885         .open =         snd_hdspm_midi_input_open,
1886         .close =        snd_hdspm_midi_input_close,
1887         .trigger =      snd_hdspm_midi_input_trigger,
1888 };
1889 
1890 static int snd_hdspm_create_midi(struct snd_card *card,
1891                                  struct hdspm *hdspm, int id)
1892 {
1893         int err;
1894         char buf[32];
1895 
1896         hdspm->midi[id].id = id;
1897         hdspm->midi[id].hdspm = hdspm;
1898         spin_lock_init (&hdspm->midi[id].lock);
1899 
1900         if (0 == id) {
1901                 if (MADIface == hdspm->io_type) {
1902                         /* MIDI-over-MADI on HDSPe MADIface */
1903                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1904                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1905                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1906                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1907                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1908                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1909                 } else {
1910                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1911                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1912                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1913                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1914                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1915                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1916                 }
1917         } else if (1 == id) {
1918                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1919                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1920                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1921                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1922                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1923                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1924         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1925                 /* MIDI-over-MADI on HDSPe MADI */
1926                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1927                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1928                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1929                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1930                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1931                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1932         } else if (2 == id) {
1933                 /* TCO MTC, read only */
1934                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1935                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1936                 hdspm->midi[2].dataOut = -1;
1937                 hdspm->midi[2].statusOut = -1;
1938                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1939                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1940         } else if (3 == id) {
1941                 /* TCO MTC on HDSPe MADI */
1942                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1943                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1944                 hdspm->midi[3].dataOut = -1;
1945                 hdspm->midi[3].statusOut = -1;
1946                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1947                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1948         }
1949 
1950         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1951                                         (MADIface == hdspm->io_type)))) {
1952                 if ((id == 0) && (MADIface == hdspm->io_type)) {
1953                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1954                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1955                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1956                 } else {
1957                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1958                 }
1959                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1960                                 &hdspm->midi[id].rmidi);
1961                 if (err < 0)
1962                         return err;
1963 
1964                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1965                                 card->id, id+1);
1966                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1967 
1968                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1969                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
1970                                 &snd_hdspm_midi_output);
1971                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1972                                 SNDRV_RAWMIDI_STREAM_INPUT,
1973                                 &snd_hdspm_midi_input);
1974 
1975                 hdspm->midi[id].rmidi->info_flags |=
1976                         SNDRV_RAWMIDI_INFO_OUTPUT |
1977                         SNDRV_RAWMIDI_INFO_INPUT |
1978                         SNDRV_RAWMIDI_INFO_DUPLEX;
1979         } else {
1980                 /* TCO MTC, read only */
1981                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1982                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1983                                 &hdspm->midi[id].rmidi);
1984                 if (err < 0)
1985                         return err;
1986 
1987                 sprintf(hdspm->midi[id].rmidi->name,
1988                                 "%s MTC %d", card->id, id+1);
1989                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1990 
1991                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1992                                 SNDRV_RAWMIDI_STREAM_INPUT,
1993                                 &snd_hdspm_midi_input);
1994 
1995                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1996         }
1997 
1998         return 0;
1999 }
2000 
2001 
2002 static void hdspm_midi_tasklet(unsigned long arg)
2003 {
2004         struct hdspm *hdspm = (struct hdspm *)arg;
2005         int i = 0;
2006 
2007         while (i < hdspm->midiPorts) {
2008                 if (hdspm->midi[i].pending)
2009                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2010 
2011                 i++;
2012         }
2013 }
2014 
2015 
2016 /*-----------------------------------------------------------------------------
2017   Status Interface
2018   ----------------------------------------------------------------------------*/
2019 
2020 /* get the system sample rate which is set */
2021 
2022 
2023 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2024 {
2025         unsigned int period, rate;
2026 
2027         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2028         rate = hdspm_calc_dds_value(hdspm, period);
2029 
2030         return rate;
2031 }
2032 
2033 /**
2034  * Calculate the real sample rate from the
2035  * current DDS value.
2036  **/
2037 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2038 {
2039         unsigned int rate;
2040 
2041         rate = hdspm_get_pll_freq(hdspm);
2042 
2043         if (rate > 207000) {
2044                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2045                 if (0 == hdspm_system_clock_mode(hdspm)) {
2046                         /* master mode, return internal sample rate */
2047                         rate = hdspm->system_sample_rate;
2048                 } else {
2049                         /* slave mode, return external sample rate */
2050                         rate = hdspm_external_sample_rate(hdspm);
2051                         if (!rate)
2052                                 rate = hdspm->system_sample_rate;
2053                 }
2054         }
2055 
2056         return rate;
2057 }
2058 
2059 
2060 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2061 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2062         .name = xname, \
2063         .index = xindex, \
2064         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2065                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2066         .info = snd_hdspm_info_system_sample_rate, \
2067         .put = snd_hdspm_put_system_sample_rate, \
2068         .get = snd_hdspm_get_system_sample_rate \
2069 }
2070 
2071 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2072                                              struct snd_ctl_elem_info *uinfo)
2073 {
2074         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2075         uinfo->count = 1;
2076         uinfo->value.integer.min = 27000;
2077         uinfo->value.integer.max = 207000;
2078         uinfo->value.integer.step = 1;
2079         return 0;
2080 }
2081 
2082 
2083 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2084                                             struct snd_ctl_elem_value *
2085                                             ucontrol)
2086 {
2087         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2088 
2089         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2090         return 0;
2091 }
2092 
2093 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2094                                             struct snd_ctl_elem_value *
2095                                             ucontrol)
2096 {
2097         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2098         int rate = ucontrol->value.integer.value[0];
2099 
2100         if (rate < 27000 || rate > 207000)
2101                 return -EINVAL;
2102         hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]);
2103         return 0;
2104 }
2105 
2106 
2107 /**
2108  * Returns the WordClock sample rate class for the given card.
2109  **/
2110 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2111 {
2112         int status;
2113 
2114         switch (hdspm->io_type) {
2115         case RayDAT:
2116         case AIO:
2117                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2118                 return (status >> 16) & 0xF;
2119                 break;
2120         default:
2121                 break;
2122         }
2123 
2124 
2125         return 0;
2126 }
2127 
2128 
2129 /**
2130  * Returns the TCO sample rate class for the given card.
2131  **/
2132 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2133 {
2134         int status;
2135 
2136         if (hdspm->tco) {
2137                 switch (hdspm->io_type) {
2138                 case RayDAT:
2139                 case AIO:
2140                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2141                         return (status >> 20) & 0xF;
2142                         break;
2143                 default:
2144                         break;
2145                 }
2146         }
2147 
2148         return 0;
2149 }
2150 
2151 
2152 /**
2153  * Returns the SYNC_IN sample rate class for the given card.
2154  **/
2155 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2156 {
2157         int status;
2158 
2159         if (hdspm->tco) {
2160                 switch (hdspm->io_type) {
2161                 case RayDAT:
2162                 case AIO:
2163                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2164                         return (status >> 12) & 0xF;
2165                         break;
2166                 default:
2167                         break;
2168                 }
2169         }
2170 
2171         return 0;
2172 }
2173 
2174 
2175 /**
2176  * Returns the sample rate class for input source <idx> for
2177  * 'new style' cards like the AIO and RayDAT.
2178  **/
2179 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2180 {
2181         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2182 
2183         return (status >> (idx*4)) & 0xF;
2184 }
2185 
2186 #define ENUMERATED_CTL_INFO(info, texts) \
2187 { \
2188         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; \
2189         uinfo->count = 1; \
2190         uinfo->value.enumerated.items = ARRAY_SIZE(texts); \
2191         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) \
2192                 uinfo->value.enumerated.item =  uinfo->value.enumerated.items - 1; \
2193         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); \
2194 }
2195 
2196 
2197 
2198 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2199 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2200         .name = xname, \
2201         .private_value = xindex, \
2202         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2203         .info = snd_hdspm_info_autosync_sample_rate, \
2204         .get = snd_hdspm_get_autosync_sample_rate \
2205 }
2206 
2207 
2208 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2209                                                struct snd_ctl_elem_info *uinfo)
2210 {
2211         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2212         return 0;
2213 }
2214 
2215 
2216 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2217                                               struct snd_ctl_elem_value *
2218                                               ucontrol)
2219 {
2220         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2221 
2222         switch (hdspm->io_type) {
2223         case RayDAT:
2224                 switch (kcontrol->private_value) {
2225                 case 0:
2226                         ucontrol->value.enumerated.item[0] =
2227                                 hdspm_get_wc_sample_rate(hdspm);
2228                         break;
2229                 case 7:
2230                         ucontrol->value.enumerated.item[0] =
2231                                 hdspm_get_tco_sample_rate(hdspm);
2232                         break;
2233                 case 8:
2234                         ucontrol->value.enumerated.item[0] =
2235                                 hdspm_get_sync_in_sample_rate(hdspm);
2236                         break;
2237                 default:
2238                         ucontrol->value.enumerated.item[0] =
2239                                 hdspm_get_s1_sample_rate(hdspm,
2240                                                 kcontrol->private_value-1);
2241                 }
2242                 break;
2243 
2244         case AIO:
2245                 switch (kcontrol->private_value) {
2246                 case 0: /* WC */
2247                         ucontrol->value.enumerated.item[0] =
2248                                 hdspm_get_wc_sample_rate(hdspm);
2249                         break;
2250                 case 4: /* TCO */
2251                         ucontrol->value.enumerated.item[0] =
2252                                 hdspm_get_tco_sample_rate(hdspm);
2253                         break;
2254                 case 5: /* SYNC_IN */
2255                         ucontrol->value.enumerated.item[0] =
2256                                 hdspm_get_sync_in_sample_rate(hdspm);
2257                         break;
2258                 default:
2259                         ucontrol->value.enumerated.item[0] =
2260                                 hdspm_get_s1_sample_rate(hdspm,
2261                                                 ucontrol->id.index-1);
2262                 }
2263                 break;
2264 
2265         case AES32:
2266 
2267                 switch (kcontrol->private_value) {
2268                 case 0: /* WC */
2269                         ucontrol->value.enumerated.item[0] =
2270                                 hdspm_get_wc_sample_rate(hdspm);
2271                         break;
2272                 case 9: /* TCO */
2273                         ucontrol->value.enumerated.item[0] =
2274                                 hdspm_get_tco_sample_rate(hdspm);
2275                         break;
2276                 case 10: /* SYNC_IN */
2277                         ucontrol->value.enumerated.item[0] =
2278                                 hdspm_get_sync_in_sample_rate(hdspm);
2279                         break;
2280                 default: /* AES1 to AES8 */
2281                         ucontrol->value.enumerated.item[0] =
2282                                 hdspm_get_s1_sample_rate(hdspm,
2283                                                 kcontrol->private_value-1);
2284                         break;
2285                 }
2286                 break;
2287 
2288         case MADI:
2289         case MADIface:
2290                 {
2291                         int rate = hdspm_external_sample_rate(hdspm);
2292                         int i, selected_rate = 0;
2293                         for (i = 1; i < 10; i++)
2294                                 if (HDSPM_bit2freq(i) == rate) {
2295                                         selected_rate = i;
2296                                         break;
2297                                 }
2298                         ucontrol->value.enumerated.item[0] = selected_rate;
2299                 }
2300                 break;
2301 
2302         default:
2303                 break;
2304         }
2305 
2306         return 0;
2307 }
2308 
2309 
2310 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2311 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2312         .name = xname, \
2313         .index = xindex, \
2314         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2315                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2316         .info = snd_hdspm_info_system_clock_mode, \
2317         .get = snd_hdspm_get_system_clock_mode, \
2318         .put = snd_hdspm_put_system_clock_mode, \
2319 }
2320 
2321 
2322 /**
2323  * Returns the system clock mode for the given card.
2324  * @returns 0 - master, 1 - slave
2325  **/
2326 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2327 {
2328         switch (hdspm->io_type) {
2329         case AIO:
2330         case RayDAT:
2331                 if (hdspm->settings_register & HDSPM_c0Master)
2332                         return 0;
2333                 break;
2334 
2335         default:
2336                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2337                         return 0;
2338         }
2339 
2340         return 1;
2341 }
2342 
2343 
2344 /**
2345  * Sets the system clock mode.
2346  * @param mode 0 - master, 1 - slave
2347  **/
2348 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2349 {
2350         switch (hdspm->io_type) {
2351         case AIO:
2352         case RayDAT:
2353                 if (0 == mode)
2354                         hdspm->settings_register |= HDSPM_c0Master;
2355                 else
2356                         hdspm->settings_register &= ~HDSPM_c0Master;
2357 
2358                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2359                 break;
2360 
2361         default:
2362                 if (0 == mode)
2363                         hdspm->control_register |= HDSPM_ClockModeMaster;
2364                 else
2365                         hdspm->control_register &= ~HDSPM_ClockModeMaster;
2366 
2367                 hdspm_write(hdspm, HDSPM_controlRegister,
2368                                 hdspm->control_register);
2369         }
2370 }
2371 
2372 
2373 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2374                                             struct snd_ctl_elem_info *uinfo)
2375 {
2376         static char *texts[] = { "Master", "AutoSync" };
2377         ENUMERATED_CTL_INFO(uinfo, texts);
2378         return 0;
2379 }
2380 
2381 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2382                                            struct snd_ctl_elem_value *ucontrol)
2383 {
2384         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2385 
2386         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2387         return 0;
2388 }
2389 
2390 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2391                                            struct snd_ctl_elem_value *ucontrol)
2392 {
2393         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2394         int val;
2395 
2396         if (!snd_hdspm_use_is_exclusive(hdspm))
2397                 return -EBUSY;
2398 
2399         val = ucontrol->value.enumerated.item[0];
2400         if (val < 0)
2401                 val = 0;
2402         else if (val > 1)
2403                 val = 1;
2404 
2405         hdspm_set_system_clock_mode(hdspm, val);
2406 
2407         return 0;
2408 }
2409 
2410 
2411 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2412 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2413         .name = xname, \
2414         .index = xindex, \
2415         .info = snd_hdspm_info_clock_source, \
2416         .get = snd_hdspm_get_clock_source, \
2417         .put = snd_hdspm_put_clock_source \
2418 }
2419 
2420 
2421 static int hdspm_clock_source(struct hdspm * hdspm)
2422 {
2423         switch (hdspm->system_sample_rate) {
2424         case 32000: return 0;
2425         case 44100: return 1;
2426         case 48000: return 2;
2427         case 64000: return 3;
2428         case 88200: return 4;
2429         case 96000: return 5;
2430         case 128000: return 6;
2431         case 176400: return 7;
2432         case 192000: return 8;
2433         }
2434 
2435         return -1;
2436 }
2437 
2438 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2439 {
2440         int rate;
2441         switch (mode) {
2442         case 0:
2443                 rate = 32000; break;
2444         case 1:
2445                 rate = 44100; break;
2446         case 2:
2447                 rate = 48000; break;
2448         case 3:
2449                 rate = 64000; break;
2450         case 4:
2451                 rate = 88200; break;
2452         case 5:
2453                 rate = 96000; break;
2454         case 6:
2455                 rate = 128000; break;
2456         case 7:
2457                 rate = 176400; break;
2458         case 8:
2459                 rate = 192000; break;
2460         default:
2461                 rate = 48000;
2462         }
2463         hdspm_set_rate(hdspm, rate, 1);
2464         return 0;
2465 }
2466 
2467 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2468                                        struct snd_ctl_elem_info *uinfo)
2469 {
2470         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2471         uinfo->count = 1;
2472         uinfo->value.enumerated.items = 9;
2473 
2474         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2475                 uinfo->value.enumerated.item =
2476                     uinfo->value.enumerated.items - 1;
2477 
2478         strcpy(uinfo->value.enumerated.name,
2479                texts_freq[uinfo->value.enumerated.item+1]);
2480 
2481         return 0;
2482 }
2483 
2484 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2485                                       struct snd_ctl_elem_value *ucontrol)
2486 {
2487         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2488 
2489         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2490         return 0;
2491 }
2492 
2493 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2494                                       struct snd_ctl_elem_value *ucontrol)
2495 {
2496         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2497         int change;
2498         int val;
2499 
2500         if (!snd_hdspm_use_is_exclusive(hdspm))
2501                 return -EBUSY;
2502         val = ucontrol->value.enumerated.item[0];
2503         if (val < 0)
2504                 val = 0;
2505         if (val > 9)
2506                 val = 9;
2507         spin_lock_irq(&hdspm->lock);
2508         if (val != hdspm_clock_source(hdspm))
2509                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2510         else
2511                 change = 0;
2512         spin_unlock_irq(&hdspm->lock);
2513         return change;
2514 }
2515 
2516 
2517 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2518 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2519         .name = xname, \
2520         .index = xindex, \
2521         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2522                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2523         .info = snd_hdspm_info_pref_sync_ref, \
2524         .get = snd_hdspm_get_pref_sync_ref, \
2525         .put = snd_hdspm_put_pref_sync_ref \
2526 }
2527 
2528 
2529 /**
2530  * Returns the current preferred sync reference setting.
2531  * The semantics of the return value are depending on the
2532  * card, please see the comments for clarification.
2533  **/
2534 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2535 {
2536         switch (hdspm->io_type) {
2537         case AES32:
2538                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2539                 case 0: return 0;  /* WC */
2540                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2541                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2542                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2543                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2544                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2545                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2546                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2547                                                     return 7; /* AES 7 */
2548                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2549                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2550                 }
2551                 break;
2552 
2553         case MADI:
2554         case MADIface:
2555                 if (hdspm->tco) {
2556                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2557                         case 0: return 0;  /* WC */
2558                         case HDSPM_SyncRef0: return 1;  /* MADI */
2559                         case HDSPM_SyncRef1: return 2;  /* TCO */
2560                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2561                                              return 3;  /* SYNC_IN */
2562                         }
2563                 } else {
2564                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2565                         case 0: return 0;  /* WC */
2566                         case HDSPM_SyncRef0: return 1;  /* MADI */
2567                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2568                                              return 2;  /* SYNC_IN */
2569                         }
2570                 }
2571                 break;
2572 
2573         case RayDAT:
2574                 if (hdspm->tco) {
2575                         switch ((hdspm->settings_register &
2576                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2577                         case 0: return 0;  /* WC */
2578                         case 3: return 1;  /* ADAT 1 */
2579                         case 4: return 2;  /* ADAT 2 */
2580                         case 5: return 3;  /* ADAT 3 */
2581                         case 6: return 4;  /* ADAT 4 */
2582                         case 1: return 5;  /* AES */
2583                         case 2: return 6;  /* SPDIF */
2584                         case 9: return 7;  /* TCO */
2585                         case 10: return 8; /* SYNC_IN */
2586                         }
2587                 } else {
2588                         switch ((hdspm->settings_register &
2589                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2590                         case 0: return 0;  /* WC */
2591                         case 3: return 1;  /* ADAT 1 */
2592                         case 4: return 2;  /* ADAT 2 */
2593                         case 5: return 3;  /* ADAT 3 */
2594                         case 6: return 4;  /* ADAT 4 */
2595                         case 1: return 5;  /* AES */
2596                         case 2: return 6;  /* SPDIF */
2597                         case 10: return 7; /* SYNC_IN */
2598                         }
2599                 }
2600 
2601                 break;
2602 
2603         case AIO:
2604                 if (hdspm->tco) {
2605                         switch ((hdspm->settings_register &
2606                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2607                         case 0: return 0;  /* WC */
2608                         case 3: return 1;  /* ADAT */
2609                         case 1: return 2;  /* AES */
2610                         case 2: return 3;  /* SPDIF */
2611                         case 9: return 4;  /* TCO */
2612                         case 10: return 5; /* SYNC_IN */
2613                         }
2614                 } else {
2615                         switch ((hdspm->settings_register &
2616                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2617                         case 0: return 0;  /* WC */
2618                         case 3: return 1;  /* ADAT */
2619                         case 1: return 2;  /* AES */
2620                         case 2: return 3;  /* SPDIF */
2621                         case 10: return 4; /* SYNC_IN */
2622                         }
2623                 }
2624 
2625                 break;
2626         }
2627 
2628         return -1;
2629 }
2630 
2631 
2632 /**
2633  * Set the preferred sync reference to <pref>. The semantics
2634  * of <pref> are depending on the card type, see the comments
2635  * for clarification.
2636  **/
2637 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2638 {
2639         int p = 0;
2640 
2641         switch (hdspm->io_type) {
2642         case AES32:
2643                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2644                 switch (pref) {
2645                 case 0: /* WC  */
2646                         break;
2647                 case 1: /* AES 1 */
2648                         hdspm->control_register |= HDSPM_SyncRef0;
2649                         break;
2650                 case 2: /* AES 2 */
2651                         hdspm->control_register |= HDSPM_SyncRef1;
2652                         break;
2653                 case 3: /* AES 3 */
2654                         hdspm->control_register |=
2655                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2656                         break;
2657                 case 4: /* AES 4 */
2658                         hdspm->control_register |= HDSPM_SyncRef2;
2659                         break;
2660                 case 5: /* AES 5 */
2661                         hdspm->control_register |=
2662                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2663                         break;
2664                 case 6: /* AES 6 */
2665                         hdspm->control_register |=
2666                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2667                         break;
2668                 case 7: /* AES 7 */
2669                         hdspm->control_register |=
2670                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2671                         break;
2672                 case 8: /* AES 8 */
2673                         hdspm->control_register |= HDSPM_SyncRef3;
2674                         break;
2675                 case 9: /* TCO */
2676                         hdspm->control_register |=
2677                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2678                         break;
2679                 default:
2680                         return -1;
2681                 }
2682 
2683                 break;
2684 
2685         case MADI:
2686         case MADIface:
2687                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2688                 if (hdspm->tco) {
2689                         switch (pref) {
2690                         case 0: /* WC */
2691                                 break;
2692                         case 1: /* MADI */
2693                                 hdspm->control_register |= HDSPM_SyncRef0;
2694                                 break;
2695                         case 2: /* TCO */
2696                                 hdspm->control_register |= HDSPM_SyncRef1;
2697                                 break;
2698                         case 3: /* SYNC_IN */
2699                                 hdspm->control_register |=
2700                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2701                                 break;
2702                         default:
2703                                 return -1;
2704                         }
2705                 } else {
2706                         switch (pref) {
2707                         case 0: /* WC */
2708                                 break;
2709                         case 1: /* MADI */
2710                                 hdspm->control_register |= HDSPM_SyncRef0;
2711                                 break;
2712                         case 2: /* SYNC_IN */
2713                                 hdspm->control_register |=
2714                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2715                                 break;
2716                         default:
2717                                 return -1;
2718                         }
2719                 }
2720 
2721                 break;
2722 
2723         case RayDAT:
2724                 if (hdspm->tco) {
2725                         switch (pref) {
2726                         case 0: p = 0; break;  /* WC */
2727                         case 1: p = 3; break;  /* ADAT 1 */
2728                         case 2: p = 4; break;  /* ADAT 2 */
2729                         case 3: p = 5; break;  /* ADAT 3 */
2730                         case 4: p = 6; break;  /* ADAT 4 */
2731                         case 5: p = 1; break;  /* AES */
2732                         case 6: p = 2; break;  /* SPDIF */
2733                         case 7: p = 9; break;  /* TCO */
2734                         case 8: p = 10; break; /* SYNC_IN */
2735                         default: return -1;
2736                         }
2737                 } else {
2738                         switch (pref) {
2739                         case 0: p = 0; break;  /* WC */
2740                         case 1: p = 3; break;  /* ADAT 1 */
2741                         case 2: p = 4; break;  /* ADAT 2 */
2742                         case 3: p = 5; break;  /* ADAT 3 */
2743                         case 4: p = 6; break;  /* ADAT 4 */
2744                         case 5: p = 1; break;  /* AES */
2745                         case 6: p = 2; break;  /* SPDIF */
2746                         case 7: p = 10; break; /* SYNC_IN */
2747                         default: return -1;
2748                         }
2749                 }
2750                 break;
2751 
2752         case AIO:
2753                 if (hdspm->tco) {
2754                         switch (pref) {
2755                         case 0: p = 0; break;  /* WC */
2756                         case 1: p = 3; break;  /* ADAT */
2757                         case 2: p = 1; break;  /* AES */
2758                         case 3: p = 2; break;  /* SPDIF */
2759                         case 4: p = 9; break;  /* TCO */
2760                         case 5: p = 10; break; /* SYNC_IN */
2761                         default: return -1;
2762                         }
2763                 } else {
2764                         switch (pref) {
2765                         case 0: p = 0; break;  /* WC */
2766                         case 1: p = 3; break;  /* ADAT */
2767                         case 2: p = 1; break;  /* AES */
2768                         case 3: p = 2; break;  /* SPDIF */
2769                         case 4: p = 10; break; /* SYNC_IN */
2770                         default: return -1;
2771                         }
2772                 }
2773                 break;
2774         }
2775 
2776         switch (hdspm->io_type) {
2777         case RayDAT:
2778         case AIO:
2779                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2780                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2781                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2782                 break;
2783 
2784         case MADI:
2785         case MADIface:
2786         case AES32:
2787                 hdspm_write(hdspm, HDSPM_controlRegister,
2788                                 hdspm->control_register);
2789         }
2790 
2791         return 0;
2792 }
2793 
2794 
2795 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2796                                         struct snd_ctl_elem_info *uinfo)
2797 {
2798         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2799 
2800         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2801         uinfo->count = 1;
2802         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2803 
2804         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2805                 uinfo->value.enumerated.item =
2806                         uinfo->value.enumerated.items - 1;
2807 
2808         strcpy(uinfo->value.enumerated.name,
2809                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2810 
2811         return 0;
2812 }
2813 
2814 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2815                                        struct snd_ctl_elem_value *ucontrol)
2816 {
2817         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2818         int psf = hdspm_pref_sync_ref(hdspm);
2819 
2820         if (psf >= 0) {
2821                 ucontrol->value.enumerated.item[0] = psf;
2822                 return 0;
2823         }
2824 
2825         return -1;
2826 }
2827 
2828 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2829                                        struct snd_ctl_elem_value *ucontrol)
2830 {
2831         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2832         int val, change = 0;
2833 
2834         if (!snd_hdspm_use_is_exclusive(hdspm))
2835                 return -EBUSY;
2836 
2837         val = ucontrol->value.enumerated.item[0];
2838 
2839         if (val < 0)
2840                 val = 0;
2841         else if (val >= hdspm->texts_autosync_items)
2842                 val = hdspm->texts_autosync_items-1;
2843 
2844         spin_lock_irq(&hdspm->lock);
2845         if (val != hdspm_pref_sync_ref(hdspm))
2846                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2847 
2848         spin_unlock_irq(&hdspm->lock);
2849         return change;
2850 }
2851 
2852 
2853 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2854 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2855         .name = xname, \
2856         .index = xindex, \
2857         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2858         .info = snd_hdspm_info_autosync_ref, \
2859         .get = snd_hdspm_get_autosync_ref, \
2860 }
2861 
2862 static int hdspm_autosync_ref(struct hdspm *hdspm)
2863 {
2864         if (AES32 == hdspm->io_type) {
2865                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2866                 unsigned int syncref =
2867                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2868                 if (syncref == 0)
2869                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2870                 if (syncref <= 8)
2871                         return syncref;
2872                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2873         } else if (MADI == hdspm->io_type) {
2874                 /* This looks at the autosync selected sync reference */
2875                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2876 
2877                 switch (status2 & HDSPM_SelSyncRefMask) {
2878                 case HDSPM_SelSyncRef_WORD:
2879                         return HDSPM_AUTOSYNC_FROM_WORD;
2880                 case HDSPM_SelSyncRef_MADI:
2881                         return HDSPM_AUTOSYNC_FROM_MADI;
2882                 case HDSPM_SelSyncRef_TCO:
2883                         return HDSPM_AUTOSYNC_FROM_TCO;
2884                 case HDSPM_SelSyncRef_SyncIn:
2885                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2886                 case HDSPM_SelSyncRef_NVALID:
2887                         return HDSPM_AUTOSYNC_FROM_NONE;
2888                 default:
2889                         return 0;
2890                 }
2891 
2892         }
2893         return 0;
2894 }
2895 
2896 
2897 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2898                                        struct snd_ctl_elem_info *uinfo)
2899 {
2900         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2901 
2902         if (AES32 == hdspm->io_type) {
2903                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2904                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2905 
2906                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2907                 uinfo->count = 1;
2908                 uinfo->value.enumerated.items = 10;
2909                 if (uinfo->value.enumerated.item >=
2910                     uinfo->value.enumerated.items)
2911                         uinfo->value.enumerated.item =
2912                                 uinfo->value.enumerated.items - 1;
2913                 strcpy(uinfo->value.enumerated.name,
2914                                 texts[uinfo->value.enumerated.item]);
2915         } else if (MADI == hdspm->io_type) {
2916                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2917                         "Sync In", "None" };
2918 
2919                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2920                 uinfo->count = 1;
2921                 uinfo->value.enumerated.items = 5;
2922                 if (uinfo->value.enumerated.item >=
2923                                 uinfo->value.enumerated.items)
2924                         uinfo->value.enumerated.item =
2925                                 uinfo->value.enumerated.items - 1;
2926                 strcpy(uinfo->value.enumerated.name,
2927                                 texts[uinfo->value.enumerated.item]);
2928         }
2929         return 0;
2930 }
2931 
2932 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2933                                       struct snd_ctl_elem_value *ucontrol)
2934 {
2935         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2936 
2937         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2938         return 0;
2939 }
2940 
2941 
2942 
2943 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
2944 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2945         .name = xname, \
2946         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
2947                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2948         .info = snd_hdspm_info_tco_video_input_format, \
2949         .get = snd_hdspm_get_tco_video_input_format, \
2950 }
2951 
2952 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
2953                                        struct snd_ctl_elem_info *uinfo)
2954 {
2955         static char *texts[] = {"No video", "NTSC", "PAL"};
2956         ENUMERATED_CTL_INFO(uinfo, texts);
2957         return 0;
2958 }
2959 
2960 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
2961                                       struct snd_ctl_elem_value *ucontrol)
2962 {
2963         u32 status;
2964         int ret = 0;
2965 
2966         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2967         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
2968         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
2969                         HDSPM_TCO1_Video_Input_Format_PAL)) {
2970         case HDSPM_TCO1_Video_Input_Format_NTSC:
2971                 /* ntsc */
2972                 ret = 1;
2973                 break;
2974         case HDSPM_TCO1_Video_Input_Format_PAL:
2975                 /* pal */
2976                 ret = 2;
2977                 break;
2978         default:
2979                 /* no video */
2980                 ret = 0;
2981                 break;
2982         }
2983         ucontrol->value.enumerated.item[0] = ret;
2984         return 0;
2985 }
2986 
2987 
2988 
2989 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
2990 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2991         .name = xname, \
2992         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
2993                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2994         .info = snd_hdspm_info_tco_ltc_frames, \
2995         .get = snd_hdspm_get_tco_ltc_frames, \
2996 }
2997 
2998 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
2999                                        struct snd_ctl_elem_info *uinfo)
3000 {
3001         static char *texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3002                                 "30 fps"};
3003         ENUMERATED_CTL_INFO(uinfo, texts);
3004         return 0;
3005 }
3006 
3007 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3008 {
3009         u32 status;
3010         int ret = 0;
3011 
3012         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3013         if (status & HDSPM_TCO1_LTC_Input_valid) {
3014                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3015                                         HDSPM_TCO1_LTC_Format_MSB)) {
3016                 case 0:
3017                         /* 24 fps */
3018                         ret = 1;
3019                         break;
3020                 case HDSPM_TCO1_LTC_Format_LSB:
3021                         /* 25 fps */
3022                         ret = 2;
3023                         break;
3024                 case HDSPM_TCO1_LTC_Format_MSB:
3025                         /* 25 fps */
3026                         ret = 3;
3027                         break;
3028                 default:
3029                         /* 30 fps */
3030                         ret = 4;
3031                         break;
3032                 }
3033         }
3034 
3035         return ret;
3036 }
3037 
3038 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3039                                       struct snd_ctl_elem_value *ucontrol)
3040 {
3041         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3042 
3043         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3044         return 0;
3045 }
3046 
3047 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3048 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3049         .name = xname, \
3050         .private_value = xindex, \
3051         .info = snd_hdspm_info_toggle_setting, \
3052         .get = snd_hdspm_get_toggle_setting, \
3053         .put = snd_hdspm_put_toggle_setting \
3054 }
3055 
3056 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3057 {
3058         return (hdspm->control_register & regmask) ? 1 : 0;
3059 }
3060 
3061 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3062 {
3063         if (out)
3064                 hdspm->control_register |= regmask;
3065         else
3066                 hdspm->control_register &= ~regmask;
3067         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3068 
3069         return 0;
3070 }
3071 
3072 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3073 
3074 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3075                                struct snd_ctl_elem_value *ucontrol)
3076 {
3077         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3078         u32 regmask = kcontrol->private_value;
3079 
3080         spin_lock_irq(&hdspm->lock);
3081         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3082         spin_unlock_irq(&hdspm->lock);
3083         return 0;
3084 }
3085 
3086 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3087                                struct snd_ctl_elem_value *ucontrol)
3088 {
3089         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3090         u32 regmask = kcontrol->private_value;
3091         int change;
3092         unsigned int val;
3093 
3094         if (!snd_hdspm_use_is_exclusive(hdspm))
3095                 return -EBUSY;
3096         val = ucontrol->value.integer.value[0] & 1;
3097         spin_lock_irq(&hdspm->lock);
3098         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3099         hdspm_set_toggle_setting(hdspm, regmask, val);
3100         spin_unlock_irq(&hdspm->lock);
3101         return change;
3102 }
3103 
3104 #define HDSPM_INPUT_SELECT(xname, xindex) \
3105 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3106         .name = xname, \
3107         .index = xindex, \
3108         .info = snd_hdspm_info_input_select, \
3109         .get = snd_hdspm_get_input_select, \
3110         .put = snd_hdspm_put_input_select \
3111 }
3112 
3113 static int hdspm_input_select(struct hdspm * hdspm)
3114 {
3115         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3116 }
3117 
3118 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3119 {
3120         if (out)
3121                 hdspm->control_register |= HDSPM_InputSelect0;
3122         else
3123                 hdspm->control_register &= ~HDSPM_InputSelect0;
3124         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3125 
3126         return 0;
3127 }
3128 
3129 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3130                                        struct snd_ctl_elem_info *uinfo)
3131 {
3132         static char *texts[] = { "optical", "coaxial" };
3133         ENUMERATED_CTL_INFO(uinfo, texts);
3134         return 0;
3135 }
3136 
3137 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3138                                       struct snd_ctl_elem_value *ucontrol)
3139 {
3140         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3141 
3142         spin_lock_irq(&hdspm->lock);
3143         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3144         spin_unlock_irq(&hdspm->lock);
3145         return 0;
3146 }
3147 
3148 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3149                                       struct snd_ctl_elem_value *ucontrol)
3150 {
3151         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3152         int change;
3153         unsigned int val;
3154 
3155         if (!snd_hdspm_use_is_exclusive(hdspm))
3156                 return -EBUSY;
3157         val = ucontrol->value.integer.value[0] & 1;
3158         spin_lock_irq(&hdspm->lock);
3159         change = (int) val != hdspm_input_select(hdspm);
3160         hdspm_set_input_select(hdspm, val);
3161         spin_unlock_irq(&hdspm->lock);
3162         return change;
3163 }
3164 
3165 
3166 #define HDSPM_DS_WIRE(xname, xindex) \
3167 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3168         .name = xname, \
3169         .index = xindex, \
3170         .info = snd_hdspm_info_ds_wire, \
3171         .get = snd_hdspm_get_ds_wire, \
3172         .put = snd_hdspm_put_ds_wire \
3173 }
3174 
3175 static int hdspm_ds_wire(struct hdspm * hdspm)
3176 {
3177         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3178 }
3179 
3180 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3181 {
3182         if (ds)
3183                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3184         else
3185                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3186         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3187 
3188         return 0;
3189 }
3190 
3191 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3192                                   struct snd_ctl_elem_info *uinfo)
3193 {
3194         static char *texts[] = { "Single", "Double" };
3195         ENUMERATED_CTL_INFO(uinfo, texts);
3196         return 0;
3197 }
3198 
3199 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3200                                  struct snd_ctl_elem_value *ucontrol)
3201 {
3202         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3203 
3204         spin_lock_irq(&hdspm->lock);
3205         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3206         spin_unlock_irq(&hdspm->lock);
3207         return 0;
3208 }
3209 
3210 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3211                                  struct snd_ctl_elem_value *ucontrol)
3212 {
3213         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3214         int change;
3215         unsigned int val;
3216 
3217         if (!snd_hdspm_use_is_exclusive(hdspm))
3218                 return -EBUSY;
3219         val = ucontrol->value.integer.value[0] & 1;
3220         spin_lock_irq(&hdspm->lock);
3221         change = (int) val != hdspm_ds_wire(hdspm);
3222         hdspm_set_ds_wire(hdspm, val);
3223         spin_unlock_irq(&hdspm->lock);
3224         return change;
3225 }
3226 
3227 
3228 #define HDSPM_QS_WIRE(xname, xindex) \
3229 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3230         .name = xname, \
3231         .index = xindex, \
3232         .info = snd_hdspm_info_qs_wire, \
3233         .get = snd_hdspm_get_qs_wire, \
3234         .put = snd_hdspm_put_qs_wire \
3235 }
3236 
3237 static int hdspm_qs_wire(struct hdspm * hdspm)
3238 {
3239         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3240                 return 1;
3241         if (hdspm->control_register & HDSPM_QS_QuadWire)
3242                 return 2;
3243         return 0;
3244 }
3245 
3246 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3247 {
3248         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3249         switch (mode) {
3250         case 0:
3251                 break;
3252         case 1:
3253                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3254                 break;
3255         case 2:
3256                 hdspm->control_register |= HDSPM_QS_QuadWire;
3257                 break;
3258         }
3259         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3260 
3261         return 0;
3262 }
3263 
3264 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3265                                        struct snd_ctl_elem_info *uinfo)
3266 {
3267         static char *texts[] = { "Single", "Double", "Quad" };
3268         ENUMERATED_CTL_INFO(uinfo, texts);
3269         return 0;
3270 }
3271 
3272 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3273                                       struct snd_ctl_elem_value *ucontrol)
3274 {
3275         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3276 
3277         spin_lock_irq(&hdspm->lock);
3278         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3279         spin_unlock_irq(&hdspm->lock);
3280         return 0;
3281 }
3282 
3283 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3284                                       struct snd_ctl_elem_value *ucontrol)
3285 {
3286         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3287         int change;
3288         int val;
3289 
3290         if (!snd_hdspm_use_is_exclusive(hdspm))
3291                 return -EBUSY;
3292         val = ucontrol->value.integer.value[0];
3293         if (val < 0)
3294                 val = 0;
3295         if (val > 2)
3296                 val = 2;
3297         spin_lock_irq(&hdspm->lock);
3298         change = val != hdspm_qs_wire(hdspm);
3299         hdspm_set_qs_wire(hdspm, val);
3300         spin_unlock_irq(&hdspm->lock);
3301         return change;
3302 }
3303 
3304 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3305 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3306         .name = xname, \
3307         .index = xindex, \
3308         .info = snd_hdspm_info_madi_speedmode, \
3309         .get = snd_hdspm_get_madi_speedmode, \
3310         .put = snd_hdspm_put_madi_speedmode \
3311 }
3312 
3313 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3314 {
3315         if (hdspm->control_register & HDSPM_QuadSpeed)
3316                 return 2;
3317         if (hdspm->control_register & HDSPM_DoubleSpeed)
3318                 return 1;
3319         return 0;
3320 }
3321 
3322 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3323 {
3324         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3325         switch (mode) {
3326         case 0:
3327                 break;
3328         case 1:
3329                 hdspm->control_register |= HDSPM_DoubleSpeed;
3330                 break;
3331         case 2:
3332                 hdspm->control_register |= HDSPM_QuadSpeed;
3333                 break;
3334         }
3335         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3336 
3337         return 0;
3338 }
3339 
3340 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3341                                        struct snd_ctl_elem_info *uinfo)
3342 {
3343         static char *texts[] = { "Single", "Double", "Quad" };
3344         ENUMERATED_CTL_INFO(uinfo, texts);
3345         return 0;
3346 }
3347 
3348 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3349                                       struct snd_ctl_elem_value *ucontrol)
3350 {
3351         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3352 
3353         spin_lock_irq(&hdspm->lock);
3354         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3355         spin_unlock_irq(&hdspm->lock);
3356         return 0;
3357 }
3358 
3359 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3360                                       struct snd_ctl_elem_value *ucontrol)
3361 {
3362         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3363         int change;
3364         int val;
3365 
3366         if (!snd_hdspm_use_is_exclusive(hdspm))
3367                 return -EBUSY;
3368         val = ucontrol->value.integer.value[0];
3369         if (val < 0)
3370                 val = 0;
3371         if (val > 2)
3372                 val = 2;
3373         spin_lock_irq(&hdspm->lock);
3374         change = val != hdspm_madi_speedmode(hdspm);
3375         hdspm_set_madi_speedmode(hdspm, val);
3376         spin_unlock_irq(&hdspm->lock);
3377         return change;
3378 }
3379 
3380 #define HDSPM_MIXER(xname, xindex) \
3381 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3382         .name = xname, \
3383         .index = xindex, \
3384         .device = 0, \
3385         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3386                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3387         .info = snd_hdspm_info_mixer, \
3388         .get = snd_hdspm_get_mixer, \
3389         .put = snd_hdspm_put_mixer \
3390 }
3391 
3392 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3393                                 struct snd_ctl_elem_info *uinfo)
3394 {
3395         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3396         uinfo->count = 3;
3397         uinfo->value.integer.min = 0;
3398         uinfo->value.integer.max = 65535;
3399         uinfo->value.integer.step = 1;
3400         return 0;
3401 }
3402 
3403 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3404                                struct snd_ctl_elem_value *ucontrol)
3405 {
3406         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3407         int source;
3408         int destination;
3409 
3410         source = ucontrol->value.integer.value[0];
3411         if (source < 0)
3412                 source = 0;
3413         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3414                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3415 
3416         destination = ucontrol->value.integer.value[1];
3417         if (destination < 0)
3418                 destination = 0;
3419         else if (destination >= HDSPM_MAX_CHANNELS)
3420                 destination = HDSPM_MAX_CHANNELS - 1;
3421 
3422         spin_lock_irq(&hdspm->lock);
3423         if (source >= HDSPM_MAX_CHANNELS)
3424                 ucontrol->value.integer.value[2] =
3425                     hdspm_read_pb_gain(hdspm, destination,
3426                                        source - HDSPM_MAX_CHANNELS);
3427         else
3428                 ucontrol->value.integer.value[2] =
3429                     hdspm_read_in_gain(hdspm, destination, source);
3430 
3431         spin_unlock_irq(&hdspm->lock);
3432 
3433         return 0;
3434 }
3435 
3436 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3437                                struct snd_ctl_elem_value *ucontrol)
3438 {
3439         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3440         int change;
3441         int source;
3442         int destination;
3443         int gain;
3444 
3445         if (!snd_hdspm_use_is_exclusive(hdspm))
3446                 return -EBUSY;
3447 
3448         source = ucontrol->value.integer.value[0];
3449         destination = ucontrol->value.integer.value[1];
3450 
3451         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3452                 return -1;
3453         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3454                 return -1;
3455 
3456         gain = ucontrol->value.integer.value[2];
3457 
3458         spin_lock_irq(&hdspm->lock);
3459 
3460         if (source >= HDSPM_MAX_CHANNELS)
3461                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3462                                                     source -
3463                                                     HDSPM_MAX_CHANNELS);
3464         else
3465                 change = gain != hdspm_read_in_gain(hdspm, destination,
3466                                                     source);
3467 
3468         if (change) {
3469                 if (source >= HDSPM_MAX_CHANNELS)
3470                         hdspm_write_pb_gain(hdspm, destination,
3471                                             source - HDSPM_MAX_CHANNELS,
3472                                             gain);
3473                 else
3474                         hdspm_write_in_gain(hdspm, destination, source,
3475                                             gain);
3476         }
3477         spin_unlock_irq(&hdspm->lock);
3478 
3479         return change;
3480 }
3481 
3482 /* The simple mixer control(s) provide gain control for the
3483    basic 1:1 mappings of playback streams to output
3484    streams.
3485 */
3486 
3487 #define HDSPM_PLAYBACK_MIXER \
3488 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3489         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3490                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3491         .info = snd_hdspm_info_playback_mixer, \
3492         .get = snd_hdspm_get_playback_mixer, \
3493         .put = snd_hdspm_put_playback_mixer \
3494 }
3495 
3496 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3497                                          struct snd_ctl_elem_info *uinfo)
3498 {
3499         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3500         uinfo->count = 1;
3501         uinfo->value.integer.min = 0;
3502         uinfo->value.integer.max = 64;
3503         uinfo->value.integer.step = 1;
3504         return 0;
3505 }
3506 
3507 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3508                                         struct snd_ctl_elem_value *ucontrol)
3509 {
3510         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3511         int channel;
3512 
3513         channel = ucontrol->id.index - 1;
3514 
3515         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3516                 return -EINVAL;
3517 
3518         spin_lock_irq(&hdspm->lock);
3519         ucontrol->value.integer.value[0] =
3520           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3521         spin_unlock_irq(&hdspm->lock);
3522 
3523         return 0;
3524 }
3525 
3526 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3527                                         struct snd_ctl_elem_value *ucontrol)
3528 {
3529         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3530         int change;
3531         int channel;
3532         int gain;
3533 
3534         if (!snd_hdspm_use_is_exclusive(hdspm))
3535                 return -EBUSY;
3536 
3537         channel = ucontrol->id.index - 1;
3538 
3539         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3540                 return -EINVAL;
3541 
3542         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3543 
3544         spin_lock_irq(&hdspm->lock);
3545         change =
3546             gain != hdspm_read_pb_gain(hdspm, channel,
3547                                        channel);
3548         if (change)
3549                 hdspm_write_pb_gain(hdspm, channel, channel,
3550                                     gain);
3551         spin_unlock_irq(&hdspm->lock);
3552         return change;
3553 }
3554 
3555 #define HDSPM_SYNC_CHECK(xname, xindex) \
3556 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3557         .name = xname, \
3558         .private_value = xindex, \
3559         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3560         .info = snd_hdspm_info_sync_check, \
3561         .get = snd_hdspm_get_sync_check \
3562 }
3563 
3564 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3565 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3566         .name = xname, \
3567         .private_value = xindex, \
3568         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3569         .info = snd_hdspm_tco_info_lock_check, \
3570         .get = snd_hdspm_get_sync_check \
3571 }
3572 
3573 
3574 
3575 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3576                                      struct snd_ctl_elem_info *uinfo)
3577 {
3578         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3579         ENUMERATED_CTL_INFO(uinfo, texts);
3580         return 0;
3581 }
3582 
3583 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3584                                      struct snd_ctl_elem_info *uinfo)
3585 {
3586         static char *texts[] = { "No Lock", "Lock" };
3587         ENUMERATED_CTL_INFO(uinfo, texts);
3588         return 0;
3589 }
3590 
3591 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3592 {
3593         int status, status2;
3594 
3595         switch (hdspm->io_type) {
3596         case AES32:
3597                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3598                 if (status & HDSPM_AES32_wcLock) {
3599                         if (status & HDSPM_AES32_wcSync)
3600                                 return 2;
3601                         else
3602                                 return 1;
3603                 }
3604                 return 0;
3605                 break;
3606 
3607         case MADI:
3608                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3609                 if (status2 & HDSPM_wcLock) {
3610                         if (status2 & HDSPM_wcSync)
3611                                 return 2;
3612                         else
3613                                 return 1;
3614                 }
3615                 return 0;
3616                 break;
3617 
3618         case RayDAT:
3619         case AIO:
3620                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3621 
3622                 if (status & 0x2000000)
3623                         return 2;
3624                 else if (status & 0x1000000)
3625                         return 1;
3626                 return 0;
3627 
3628                 break;
3629 
3630         case MADIface:
3631                 break;
3632         }
3633 
3634 
3635         return 3;
3636 }
3637 
3638 
3639 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3640 {
3641         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3642         if (status & HDSPM_madiLock) {
3643                 if (status & HDSPM_madiSync)
3644                         return 2;
3645                 else
3646                         return 1;
3647         }
3648         return 0;
3649 }
3650 
3651 
3652 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3653 {
3654         int status, lock, sync;
3655 
3656         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3657 
3658         lock = (status & (0x1<<idx)) ? 1 : 0;
3659         sync = (status & (0x100<<idx)) ? 1 : 0;
3660 
3661         if (lock && sync)
3662                 return 2;
3663         else if (lock)
3664                 return 1;
3665         return 0;
3666 }
3667 
3668 
3669 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3670 {
3671         int status, lock = 0, sync = 0;
3672 
3673         switch (hdspm->io_type) {
3674         case RayDAT:
3675         case AIO:
3676                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3677                 lock = (status & 0x400) ? 1 : 0;
3678                 sync = (status & 0x800) ? 1 : 0;
3679                 break;
3680 
3681         case MADI:
3682                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3683                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3684                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3685                 break;
3686 
3687         case AES32:
3688                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3689                 lock = (status & 0x100000) ? 1 : 0;
3690                 sync = (status & 0x200000) ? 1 : 0;
3691                 break;
3692 
3693         case MADIface:
3694                 break;
3695         }
3696 
3697         if (lock && sync)
3698                 return 2;
3699         else if (lock)
3700                 return 1;
3701 
3702         return 0;
3703 }
3704 
3705 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3706 {
3707         int status2, lock, sync;
3708         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3709 
3710         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3711         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3712 
3713         if (sync)
3714                 return 2;
3715         else if (lock)
3716                 return 1;
3717         return 0;
3718 }
3719 
3720 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3721 {
3722         u32 status;
3723         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3724 
3725         return (status & mask) ? 1 : 0;
3726 }
3727 
3728 
3729 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3730 {
3731         int status;
3732 
3733         if (hdspm->tco) {
3734                 switch (hdspm->io_type) {
3735                 case MADI:
3736                 case AES32:
3737                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3738                         if (status & HDSPM_tcoLock) {
3739                                 if (status & HDSPM_tcoSync)
3740                                         return 2;
3741                                 else
3742                                         return 1;
3743                         }
3744                         return 0;
3745 
3746                         break;
3747 
3748                 case RayDAT:
3749                 case AIO:
3750                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3751 
3752                         if (status & 0x8000000)
3753                                 return 2; /* Sync */
3754                         if (status & 0x4000000)
3755                                 return 1; /* Lock */
3756                         return 0; /* No signal */
3757                         break;
3758 
3759                 default:
3760                         break;
3761                 }
3762         }
3763 
3764         return 3; /* N/A */
3765 }
3766 
3767 
3768 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3769                                     struct snd_ctl_elem_value *ucontrol)
3770 {
3771         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3772         int val = -1;
3773 
3774         switch (hdspm->io_type) {
3775         case RayDAT:
3776                 switch (kcontrol->private_value) {
3777                 case 0: /* WC */
3778                         val = hdspm_wc_sync_check(hdspm); break;
3779                 case 7: /* TCO */
3780                         val = hdspm_tco_sync_check(hdspm); break;
3781                 case 8: /* SYNC IN */
3782                         val = hdspm_sync_in_sync_check(hdspm); break;
3783                 default:
3784                         val = hdspm_s1_sync_check(hdspm,
3785                                         kcontrol->private_value-1);
3786                 }
3787                 break;
3788 
3789         case AIO:
3790                 switch (kcontrol->private_value) {
3791                 case 0: /* WC */
3792                         val = hdspm_wc_sync_check(hdspm); break;
3793                 case 4: /* TCO */
3794                         val = hdspm_tco_sync_check(hdspm); break;
3795                 case 5: /* SYNC IN */
3796                         val = hdspm_sync_in_sync_check(hdspm); break;
3797                 default:
3798                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3799                 }
3800                 break;
3801 
3802         case MADI:
3803                 switch (kcontrol->private_value) {
3804                 case 0: /* WC */
3805                         val = hdspm_wc_sync_check(hdspm); break;
3806                 case 1: /* MADI */
3807                         val = hdspm_madi_sync_check(hdspm); break;
3808                 case 2: /* TCO */
3809                         val = hdspm_tco_sync_check(hdspm); break;
3810                 case 3: /* SYNC_IN */
3811                         val = hdspm_sync_in_sync_check(hdspm); break;
3812                 }
3813                 break;
3814 
3815         case MADIface:
3816                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3817                 break;
3818 
3819         case AES32:
3820                 switch (kcontrol->private_value) {
3821                 case 0: /* WC */
3822                         val = hdspm_wc_sync_check(hdspm); break;
3823                 case 9: /* TCO */
3824                         val = hdspm_tco_sync_check(hdspm); break;
3825                 case 10 /* SYNC IN */:
3826                         val = hdspm_sync_in_sync_check(hdspm); break;
3827                 default: /* AES1 to AES8 */
3828                          val = hdspm_aes_sync_check(hdspm,
3829                                          kcontrol->private_value-1);
3830                 }
3831                 break;
3832 
3833         }
3834 
3835         if (hdspm->tco) {
3836                 switch (kcontrol->private_value) {
3837                 case 11:
3838                         /* Check TCO for lock state of its current input */
3839                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
3840                         break;
3841                 case 12:
3842                         /* Check TCO for valid time code on LTC input. */
3843                         val = hdspm_tco_input_check(hdspm,
3844                                 HDSPM_TCO1_LTC_Input_valid);
3845                         break;
3846                 default:
3847                         break;
3848                 }
3849         }
3850 
3851         if (-1 == val)
3852                 val = 3;
3853 
3854         ucontrol->value.enumerated.item[0] = val;
3855         return 0;
3856 }
3857 
3858 
3859 
3860 /**
3861  * TCO controls
3862  **/
3863 static void hdspm_tco_write(struct hdspm *hdspm)
3864 {
3865         unsigned int tc[4] = { 0, 0, 0, 0};
3866 
3867         switch (hdspm->tco->input) {
3868         case 0:
3869                 tc[2] |= HDSPM_TCO2_set_input_MSB;
3870                 break;
3871         case 1:
3872                 tc[2] |= HDSPM_TCO2_set_input_LSB;
3873                 break;
3874         default:
3875                 break;
3876         }
3877 
3878         switch (hdspm->tco->framerate) {
3879         case 1:
3880                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3881                 break;
3882         case 2:
3883                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3884                 break;
3885         case 3:
3886                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3887                         HDSPM_TCO1_set_drop_frame_flag;
3888                 break;
3889         case 4:
3890                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3891                         HDSPM_TCO1_LTC_Format_MSB;
3892                 break;
3893         case 5:
3894                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3895                         HDSPM_TCO1_LTC_Format_MSB +
3896                         HDSPM_TCO1_set_drop_frame_flag;
3897                 break;
3898         default:
3899                 break;
3900         }
3901 
3902         switch (hdspm->tco->wordclock) {
3903         case 1:
3904                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
3905                 break;
3906         case 2:
3907                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
3908                 break;
3909         default:
3910                 break;
3911         }
3912 
3913         switch (hdspm->tco->samplerate) {
3914         case 1:
3915                 tc[2] |= HDSPM_TCO2_set_freq;
3916                 break;
3917         case 2:
3918                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
3919                 break;
3920         default:
3921                 break;
3922         }
3923 
3924         switch (hdspm->tco->pull) {
3925         case 1:
3926                 tc[2] |= HDSPM_TCO2_set_pull_up;
3927                 break;
3928         case 2:
3929                 tc[2] |= HDSPM_TCO2_set_pull_down;
3930                 break;
3931         case 3:
3932                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
3933                 break;
3934         case 4:
3935                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
3936                 break;
3937         default:
3938                 break;
3939         }
3940 
3941         if (1 == hdspm->tco->term) {
3942                 tc[2] |= HDSPM_TCO2_set_term_75R;
3943         }
3944 
3945         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
3946         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
3947         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
3948         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
3949 }
3950 
3951 
3952 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
3953 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3954         .name = xname, \
3955         .index = xindex, \
3956         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3957                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3958         .info = snd_hdspm_info_tco_sample_rate, \
3959         .get = snd_hdspm_get_tco_sample_rate, \
3960         .put = snd_hdspm_put_tco_sample_rate \
3961 }
3962 
3963 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
3964                                           struct snd_ctl_elem_info *uinfo)
3965 {
3966         static char *texts[] = { "44.1 kHz", "48 kHz" };
3967         ENUMERATED_CTL_INFO(uinfo, texts);
3968         return 0;
3969 }
3970 
3971 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
3972                                       struct snd_ctl_elem_value *ucontrol)
3973 {
3974         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3975 
3976         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
3977 
3978         return 0;
3979 }
3980 
3981 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
3982                                          struct snd_ctl_elem_value *ucontrol)
3983 {
3984         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3985 
3986         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
3987                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
3988 
3989                 hdspm_tco_write(hdspm);
3990 
3991                 return 1;
3992         }
3993 
3994         return 0;
3995 }
3996 
3997 
3998 #define HDSPM_TCO_PULL(xname, xindex) \
3999 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4000         .name = xname, \
4001         .index = xindex, \
4002         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4003                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4004         .info = snd_hdspm_info_tco_pull, \
4005         .get = snd_hdspm_get_tco_pull, \
4006         .put = snd_hdspm_put_tco_pull \
4007 }
4008 
4009 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4010                                    struct snd_ctl_elem_info *uinfo)
4011 {
4012         static char *texts[] = { "", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4013         ENUMERATED_CTL_INFO(uinfo, texts);
4014         return 0;
4015 }
4016 
4017 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4018                                   struct snd_ctl_elem_value *ucontrol)
4019 {
4020         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4021 
4022         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4023 
4024         return 0;
4025 }
4026 
4027 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4028                                   struct snd_ctl_elem_value *ucontrol)
4029 {
4030         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4031 
4032         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4033                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4034 
4035                 hdspm_tco_write(hdspm);
4036 
4037                 return 1;
4038         }
4039 
4040         return 0;
4041 }
4042 
4043 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4044 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4045         .name = xname, \
4046         .index = xindex, \
4047         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4048                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4049         .info = snd_hdspm_info_tco_wck_conversion, \
4050         .get = snd_hdspm_get_tco_wck_conversion, \
4051         .put = snd_hdspm_put_tco_wck_conversion \
4052 }
4053 
4054 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4055                                              struct snd_ctl_elem_info *uinfo)
4056 {
4057         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4058         ENUMERATED_CTL_INFO(uinfo, texts);
4059         return 0;
4060 }
4061 
4062 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4063                                             struct snd_ctl_elem_value *ucontrol)
4064 {
4065         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4066 
4067         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4068 
4069         return 0;
4070 }
4071 
4072 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4073                                             struct snd_ctl_elem_value *ucontrol)
4074 {
4075         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4076 
4077         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4078                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4079 
4080                 hdspm_tco_write(hdspm);
4081 
4082                 return 1;
4083         }
4084 
4085         return 0;
4086 }
4087 
4088 
4089 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4090 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4091         .name = xname, \
4092         .index = xindex, \
4093         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4094                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4095         .info = snd_hdspm_info_tco_frame_rate, \
4096         .get = snd_hdspm_get_tco_frame_rate, \
4097         .put = snd_hdspm_put_tco_frame_rate \
4098 }
4099 
4100 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4101                                           struct snd_ctl_elem_info *uinfo)
4102 {
4103         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4104                 "29.97 dfps", "30 fps", "30 dfps" };
4105         ENUMERATED_CTL_INFO(uinfo, texts);
4106         return 0;
4107 }
4108 
4109 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4110                                         struct snd_ctl_elem_value *ucontrol)
4111 {
4112         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4113 
4114         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4115 
4116         return 0;
4117 }
4118 
4119 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4120                                         struct snd_ctl_elem_value *ucontrol)
4121 {
4122         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4123 
4124         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4125                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4126 
4127                 hdspm_tco_write(hdspm);
4128 
4129                 return 1;
4130         }
4131 
4132         return 0;
4133 }
4134 
4135 
4136 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4137 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4138         .name = xname, \
4139         .index = xindex, \
4140         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4141                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4142         .info = snd_hdspm_info_tco_sync_source, \
4143         .get = snd_hdspm_get_tco_sync_source, \
4144         .put = snd_hdspm_put_tco_sync_source \
4145 }
4146 
4147 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4148                                           struct snd_ctl_elem_info *uinfo)
4149 {
4150         static char *texts[] = { "LTC", "Video", "WCK" };
4151         ENUMERATED_CTL_INFO(uinfo, texts);
4152         return 0;
4153 }
4154 
4155 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4156                                          struct snd_ctl_elem_value *ucontrol)
4157 {
4158         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4159 
4160         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4161 
4162         return 0;
4163 }
4164 
4165 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4166                                          struct snd_ctl_elem_value *ucontrol)
4167 {
4168         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4169 
4170         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4171                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4172 
4173                 hdspm_tco_write(hdspm);
4174 
4175                 return 1;
4176         }
4177 
4178         return 0;
4179 }
4180 
4181 
4182 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4183 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4184         .name = xname, \
4185         .index = xindex, \
4186         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4187                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4188         .info = snd_hdspm_info_tco_word_term, \
4189         .get = snd_hdspm_get_tco_word_term, \
4190         .put = snd_hdspm_put_tco_word_term \
4191 }
4192 
4193 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4194                                         struct snd_ctl_elem_info *uinfo)
4195 {
4196         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4197         uinfo->count = 1;
4198         uinfo->value.integer.min = 0;
4199         uinfo->value.integer.max = 1;
4200 
4201         return 0;
4202 }
4203 
4204 
4205 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4206                                        struct snd_ctl_elem_value *ucontrol)
4207 {
4208         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4209 
4210         ucontrol->value.integer.value[0] = hdspm->tco->term;
4211 
4212         return 0;
4213 }
4214 
4215 
4216 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4217                                        struct snd_ctl_elem_value *ucontrol)
4218 {
4219         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4220 
4221         if (hdspm->tco->term != ucontrol->value.integer.value[0]) {
4222                 hdspm->tco->term = ucontrol->value.integer.value[0];
4223 
4224                 hdspm_tco_write(hdspm);
4225 
4226                 return 1;
4227         }
4228 
4229         return 0;
4230 }
4231 
4232 
4233 
4234 
4235 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4236         HDSPM_MIXER("Mixer", 0),
4237         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4238         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4239         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4240         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4241         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4242         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4243         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4244         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4245         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4246         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4247         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4248         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4249         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4250         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4251         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4252         HDSPM_INPUT_SELECT("Input Select", 0),
4253         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4254 };
4255 
4256 
4257 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4258         HDSPM_MIXER("Mixer", 0),
4259         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4260         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4261         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4262         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4263         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4264         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4265         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4266         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4267         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4268 };
4269 
4270 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4271         HDSPM_MIXER("Mixer", 0),
4272         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4273         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4274         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4275         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4276         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4277         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4278         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4279         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4280         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4281         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4282         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4283         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4284         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4285         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4286         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4287         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4288         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4289         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4290 
4291                 /*
4292                    HDSPM_INPUT_SELECT("Input Select", 0),
4293                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4294                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4295                    HDSPM_SPDIF_IN("SPDIF In", 0);
4296                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4297                    HDSPM_INPUT_LEVEL("Input Level", 0);
4298                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4299                    HDSPM_PHONES("Phones", 0);
4300                    */
4301 };
4302 
4303 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4304         HDSPM_MIXER("Mixer", 0),
4305         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4306         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4307         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4308         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4309         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4310         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4311         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4312         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4313         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4314         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4315         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4316         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4317         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4318         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4319         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4320         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4321         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4322         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4323         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4324         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4325         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4326         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4327 };
4328 
4329 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4330         HDSPM_MIXER("Mixer", 0),
4331         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4332         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4333         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4334         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4335         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4336         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4337         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4338         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4339         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4340         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4341         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4342         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4343         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4344         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4345         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4346         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4347         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4348         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4349         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4350         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4351         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4352         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4353         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4354         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4355         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4356         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4357         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4358         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4359         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4360         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4361         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4362         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4363         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4364         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4365         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4366 };
4367 
4368 
4369 
4370 /* Control elements for the optional TCO module */
4371 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4372         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4373         HDSPM_TCO_PULL("TCO Pull", 0),
4374         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4375         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4376         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4377         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4378         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4379         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4380         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4381         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4382 };
4383 
4384 
4385 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4386 
4387 
4388 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4389 {
4390         int i;
4391 
4392         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4393                 if (hdspm->system_sample_rate > 48000) {
4394                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4395                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4396                                 SNDRV_CTL_ELEM_ACCESS_READ |
4397                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4398                 } else {
4399                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4400                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4401                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4402                 }
4403                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4404                                 SNDRV_CTL_EVENT_MASK_INFO,
4405                                 &hdspm->playback_mixer_ctls[i]->id);
4406         }
4407 
4408         return 0;
4409 }
4410 
4411 
4412 static int snd_hdspm_create_controls(struct snd_card *card,
4413                                         struct hdspm *hdspm)
4414 {
4415         unsigned int idx, limit;
4416         int err;
4417         struct snd_kcontrol *kctl;
4418         struct snd_kcontrol_new *list = NULL;
4419 
4420         switch (hdspm->io_type) {
4421         case MADI:
4422                 list = snd_hdspm_controls_madi;
4423                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4424                 break;
4425         case MADIface:
4426                 list = snd_hdspm_controls_madiface;
4427                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4428                 break;
4429         case AIO:
4430                 list = snd_hdspm_controls_aio;
4431                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4432                 break;
4433         case RayDAT:
4434                 list = snd_hdspm_controls_raydat;
4435                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4436                 break;
4437         case AES32:
4438                 list = snd_hdspm_controls_aes32;
4439                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4440                 break;
4441         }
4442 
4443         if (NULL != list) {
4444                 for (idx = 0; idx < limit; idx++) {
4445                         err = snd_ctl_add(card,
4446                                         snd_ctl_new1(&list[idx], hdspm));
4447                         if (err < 0)
4448                                 return err;
4449                 }
4450         }
4451 
4452 
4453         /* create simple 1:1 playback mixer controls */
4454         snd_hdspm_playback_mixer.name = "Chn";
4455         if (hdspm->system_sample_rate >= 128000) {
4456                 limit = hdspm->qs_out_channels;
4457         } else if (hdspm->system_sample_rate >= 64000) {
4458                 limit = hdspm->ds_out_channels;
4459         } else {
4460                 limit = hdspm->ss_out_channels;
4461         }
4462         for (idx = 0; idx < limit; ++idx) {
4463                 snd_hdspm_playback_mixer.index = idx + 1;
4464                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4465                 err = snd_ctl_add(card, kctl);
4466                 if (err < 0)
4467                         return err;
4468                 hdspm->playback_mixer_ctls[idx] = kctl;
4469         }
4470 
4471 
4472         if (hdspm->tco) {
4473                 /* add tco control elements */
4474                 list = snd_hdspm_controls_tco;
4475                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4476                 for (idx = 0; idx < limit; idx++) {
4477                         err = snd_ctl_add(card,
4478                                         snd_ctl_new1(&list[idx], hdspm));
4479                         if (err < 0)
4480                                 return err;
4481                 }
4482         }
4483 
4484         return 0;
4485 }
4486 
4487 /*------------------------------------------------------------
4488    /proc interface
4489  ------------------------------------------------------------*/
4490 
4491 static void
4492 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4493                          struct snd_info_buffer *buffer)
4494 {
4495         struct hdspm *hdspm = entry->private_data;
4496         unsigned int status, status2, control, freq;
4497 
4498         char *pref_sync_ref;
4499         char *autosync_ref;
4500         char *system_clock_mode;
4501         char *insel;
4502         int x, x2;
4503 
4504         /* TCO stuff */
4505         int a, ltc, frames, seconds, minutes, hours;
4506         unsigned int period;
4507         u64 freq_const = 0;
4508         u32 rate;
4509 
4510         status = hdspm_read(hdspm, HDSPM_statusRegister);
4511         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4512         control = hdspm->control_register;
4513         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4514 
4515         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4516                         hdspm->card_name, hdspm->card->number + 1,
4517                         hdspm->firmware_rev,
4518                         (status2 & HDSPM_version0) |
4519                         (status2 & HDSPM_version1) | (status2 &
4520                                 HDSPM_version2));
4521 
4522         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4523                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4524                         hdspm->serial);
4525 
4526         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4527                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4528 
4529         snd_iprintf(buffer, "--- System ---\n");
4530 
4531         snd_iprintf(buffer,
4532                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4533                 status & HDSPM_audioIRQPending,
4534                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4535                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4536                 hdspm->irq_count);
4537         snd_iprintf(buffer,
4538                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4539                 "estimated= %ld (bytes)\n",
4540                 ((status & HDSPM_BufferID) ? 1 : 0),
4541                 (status & HDSPM_BufferPositionMask),
4542                 (status & HDSPM_BufferPositionMask) %
4543                 (2 * (int)hdspm->period_bytes),
4544                 ((status & HDSPM_BufferPositionMask) - 64) %
4545                 (2 * (int)hdspm->period_bytes),
4546                 (long) hdspm_hw_pointer(hdspm) * 4);
4547 
4548         snd_iprintf(buffer,
4549                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4550                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4551                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4552                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4553                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4554         snd_iprintf(buffer,
4555                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4556                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4557                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4558         snd_iprintf(buffer,
4559                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4560                 "status2=0x%x\n",
4561                 hdspm->control_register, hdspm->control2_register,
4562                 status, status2);
4563         if (status & HDSPM_tco_detect) {
4564                 snd_iprintf(buffer, "TCO module detected.\n");
4565                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4566                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4567                         snd_iprintf(buffer, "  LTC valid, ");
4568                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4569                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4570                         case 0:
4571                                 snd_iprintf(buffer, "24 fps, ");
4572                                 break;
4573                         case HDSPM_TCO1_LTC_Format_LSB:
4574                                 snd_iprintf(buffer, "25 fps, ");
4575                                 break;
4576                         case HDSPM_TCO1_LTC_Format_MSB:
4577                                 snd_iprintf(buffer, "29.97 fps, ");
4578                                 break;
4579                         default:
4580                                 snd_iprintf(buffer, "30 fps, ");
4581                                 break;
4582                         }
4583                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4584                                 snd_iprintf(buffer, "drop frame\n");
4585                         } else {
4586                                 snd_iprintf(buffer, "full frame\n");
4587                         }
4588                 } else {
4589                         snd_iprintf(buffer, "  no LTC\n");
4590                 }
4591                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4592                         snd_iprintf(buffer, "  Video: NTSC\n");
4593                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4594                         snd_iprintf(buffer, "  Video: PAL\n");
4595                 } else {
4596                         snd_iprintf(buffer, "  No video\n");
4597                 }
4598                 if (a & HDSPM_TCO1_TCO_lock) {
4599                         snd_iprintf(buffer, "  Sync: lock\n");
4600                 } else {
4601                         snd_iprintf(buffer, "  Sync: no lock\n");
4602                 }
4603 
4604                 switch (hdspm->io_type) {
4605                 case MADI:
4606                 case AES32:
4607                         freq_const = 110069313433624ULL;
4608                         break;
4609                 case RayDAT:
4610                 case AIO:
4611                         freq_const = 104857600000000ULL;
4612                         break;
4613                 case MADIface:
4614                         break; /* no TCO possible */
4615                 }
4616 
4617                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4618                 snd_iprintf(buffer, "    period: %u\n", period);
4619 
4620 
4621                 /* rate = freq_const/period; */
4622                 rate = div_u64(freq_const, period);
4623 
4624                 if (control & HDSPM_QuadSpeed) {
4625                         rate *= 4;
4626                 } else if (control & HDSPM_DoubleSpeed) {
4627                         rate *= 2;
4628                 }
4629 
4630                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4631                                 (unsigned int) rate);
4632 
4633                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4634                 frames = ltc & 0xF;
4635                 ltc >>= 4;
4636                 frames += (ltc & 0x3) * 10;
4637                 ltc >>= 4;
4638                 seconds = ltc & 0xF;
4639                 ltc >>= 4;
4640                 seconds += (ltc & 0x7) * 10;
4641                 ltc >>= 4;
4642                 minutes = ltc & 0xF;
4643                 ltc >>= 4;
4644                 minutes += (ltc & 0x7) * 10;
4645                 ltc >>= 4;
4646                 hours = ltc & 0xF;
4647                 ltc >>= 4;
4648                 hours += (ltc & 0x3) * 10;
4649                 snd_iprintf(buffer,
4650                         "  LTC In: %02d:%02d:%02d:%02d\n",
4651                         hours, minutes, seconds, frames);
4652 
4653         } else {
4654                 snd_iprintf(buffer, "No TCO module detected.\n");
4655         }
4656 
4657         snd_iprintf(buffer, "--- Settings ---\n");
4658 
4659         x = hdspm_get_latency(hdspm);
4660 
4661         snd_iprintf(buffer,
4662                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4663                 x, (unsigned long) hdspm->period_bytes);
4664 
4665         snd_iprintf(buffer, "Line out: %s\n",
4666                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4667 
4668         switch (hdspm->control_register & HDSPM_InputMask) {
4669         case HDSPM_InputOptical:
4670                 insel = "Optical";
4671                 break;
4672         case HDSPM_InputCoaxial:
4673                 insel = "Coaxial";
4674                 break;
4675         default:
4676                 insel = "Unknown";
4677         }
4678 
4679         snd_iprintf(buffer,
4680                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4681                 "Auto Input %s\n",
4682                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4683                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4684                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4685 
4686 
4687         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4688                 system_clock_mode = "AutoSync";
4689         else
4690                 system_clock_mode = "Master";
4691         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4692 
4693         switch (hdspm_pref_sync_ref(hdspm)) {
4694         case HDSPM_SYNC_FROM_WORD:
4695                 pref_sync_ref = "Word Clock";
4696                 break;
4697         case HDSPM_SYNC_FROM_MADI:
4698                 pref_sync_ref = "MADI Sync";
4699                 break;
4700         case HDSPM_SYNC_FROM_TCO:
4701                 pref_sync_ref = "TCO";
4702                 break;
4703         case HDSPM_SYNC_FROM_SYNC_IN:
4704                 pref_sync_ref = "Sync In";
4705                 break;
4706         default:
4707                 pref_sync_ref = "XXXX Clock";
4708                 break;
4709         }
4710         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4711                         pref_sync_ref);
4712 
4713         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4714                         hdspm->system_sample_rate);
4715 
4716 
4717         snd_iprintf(buffer, "--- Status:\n");
4718 
4719         x = status & HDSPM_madiSync;
4720         x2 = status2 & HDSPM_wcSync;
4721 
4722         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4723                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4724                         "NoLock",
4725                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4726                         "NoLock");
4727 
4728         switch (hdspm_autosync_ref(hdspm)) {
4729         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4730                 autosync_ref = "Sync In";
4731                 break;
4732         case HDSPM_AUTOSYNC_FROM_TCO:
4733                 autosync_ref = "TCO";
4734                 break;
4735         case HDSPM_AUTOSYNC_FROM_WORD:
4736                 autosync_ref = "Word Clock";
4737                 break;
4738         case HDSPM_AUTOSYNC_FROM_MADI:
4739                 autosync_ref = "MADI Sync";
4740                 break;
4741         case HDSPM_AUTOSYNC_FROM_NONE:
4742                 autosync_ref = "Input not valid";
4743                 break;
4744         default:
4745                 autosync_ref = "---";
4746                 break;
4747         }
4748         snd_iprintf(buffer,
4749                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4750                 autosync_ref, hdspm_external_sample_rate(hdspm),
4751                 (status & HDSPM_madiFreqMask) >> 22,
4752                 (status2 & HDSPM_wcFreqMask) >> 5);
4753 
4754         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4755                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4756                 (status & HDSPM_RX_64ch) ? "64 channels" :
4757                 "56 channels");
4758 
4759         snd_iprintf(buffer, "\n");
4760 }
4761 
4762 static void
4763 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4764                           struct snd_info_buffer *buffer)
4765 {
4766         struct hdspm *hdspm = entry->private_data;
4767         unsigned int status;
4768         unsigned int status2;
4769         unsigned int timecode;
4770         unsigned int wcLock, wcSync;
4771         int pref_syncref;
4772         char *autosync_ref;
4773         int x;
4774 
4775         status = hdspm_read(hdspm, HDSPM_statusRegister);
4776         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4777         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4778 
4779         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4780                     hdspm->card_name, hdspm->card->number + 1,
4781                     hdspm->firmware_rev);
4782 
4783         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4784                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4785 
4786         snd_iprintf(buffer, "--- System ---\n");
4787 
4788         snd_iprintf(buffer,
4789                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4790                     status & HDSPM_audioIRQPending,
4791                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
4792                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
4793                     hdspm->irq_count);
4794         snd_iprintf(buffer,
4795                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
4796                     "estimated= %ld (bytes)\n",
4797                     ((status & HDSPM_BufferID) ? 1 : 0),
4798                     (status & HDSPM_BufferPositionMask),
4799                     (status & HDSPM_BufferPositionMask) %
4800                     (2 * (int)hdspm->period_bytes),
4801                     ((status & HDSPM_BufferPositionMask) - 64) %
4802                     (2 * (int)hdspm->period_bytes),
4803                     (long) hdspm_hw_pointer(hdspm) * 4);
4804 
4805         snd_iprintf(buffer,
4806                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4807                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4808                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4809                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4810                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4811         snd_iprintf(buffer,
4812                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4813                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4814                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4815         snd_iprintf(buffer,
4816                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4817                     "status2=0x%x\n",
4818                     hdspm->control_register, hdspm->control2_register,
4819                     status, status2);
4820 
4821         snd_iprintf(buffer, "--- Settings ---\n");
4822 
4823         x = hdspm_get_latency(hdspm);
4824 
4825         snd_iprintf(buffer,
4826                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4827                     x, (unsigned long) hdspm->period_bytes);
4828 
4829         snd_iprintf(buffer, "Line out: %s\n",
4830                     (hdspm->
4831                      control_register & HDSPM_LineOut) ? "on " : "off");
4832 
4833         snd_iprintf(buffer,
4834                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4835                     (hdspm->
4836                      control_register & HDSPM_clr_tms) ? "on" : "off",
4837                     (hdspm->
4838                      control_register & HDSPM_Emphasis) ? "on" : "off",
4839                     (hdspm->
4840                      control_register & HDSPM_Dolby) ? "on" : "off");
4841 
4842 
4843         pref_syncref = hdspm_pref_sync_ref(hdspm);
4844         if (pref_syncref == 0)
4845                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4846         else
4847                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4848                                 pref_syncref);
4849 
4850         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4851                     hdspm->system_sample_rate);
4852 
4853         snd_iprintf(buffer, "Double speed: %s\n",
4854                         hdspm->control_register & HDSPM_DS_DoubleWire?
4855                         "Double wire" : "Single wire");
4856         snd_iprintf(buffer, "Quad speed: %s\n",
4857                         hdspm->control_register & HDSPM_QS_DoubleWire?
4858                         "Double wire" :
4859                         hdspm->control_register & HDSPM_QS_QuadWire?
4860                         "Quad wire" : "Single wire");
4861 
4862         snd_iprintf(buffer, "--- Status:\n");
4863 
4864         wcLock = status & HDSPM_AES32_wcLock;
4865         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
4866 
4867         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
4868                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
4869                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
4870 
4871         for (x = 0; x < 8; x++) {
4872                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
4873                             x+1,
4874                             (status2 & (HDSPM_LockAES >> x)) ?
4875                             "Sync   " : "No Lock",
4876                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
4877         }
4878 
4879         switch (hdspm_autosync_ref(hdspm)) {
4880         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
4881                 autosync_ref = "None"; break;
4882         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
4883                 autosync_ref = "Word Clock"; break;
4884         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
4885                 autosync_ref = "AES1"; break;
4886         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
4887                 autosync_ref = "AES2"; break;
4888         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
4889                 autosync_ref = "AES3"; break;
4890         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
4891                 autosync_ref = "AES4"; break;
4892         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
4893                 autosync_ref = "AES5"; break;
4894         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
4895                 autosync_ref = "AES6"; break;
4896         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
4897                 autosync_ref = "AES7"; break;
4898         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
4899                 autosync_ref = "AES8"; break;
4900         default:
4901                 autosync_ref = "---"; break;
4902         }
4903         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
4904 
4905         snd_iprintf(buffer, "\n");
4906 }
4907 
4908 static void
4909 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
4910                          struct snd_info_buffer *buffer)
4911 {
4912         struct hdspm *hdspm = entry->private_data;
4913         unsigned int status1, status2, status3, control, i;
4914         unsigned int lock, sync;
4915 
4916         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
4917         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
4918         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
4919 
4920         control = hdspm->control_register;
4921 
4922         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
4923         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
4924         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
4925 
4926 
4927         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
4928 
4929         snd_iprintf(buffer, "Clock mode      : %s\n",
4930                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
4931         snd_iprintf(buffer, "System frequency: %d Hz\n",
4932                 hdspm_get_system_sample_rate(hdspm));
4933 
4934         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
4935 
4936         lock = 0x1;
4937         sync = 0x100;
4938 
4939         for (i = 0; i < 8; i++) {
4940                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
4941                                 i,
4942                                 (status1 & lock) ? 1 : 0,
4943                                 (status1 & sync) ? 1 : 0,
4944                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
4945 
4946                 lock = lock<<1;
4947                 sync = sync<<1;
4948         }
4949 
4950         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
4951                         (status1 & 0x1000000) ? 1 : 0,
4952                         (status1 & 0x2000000) ? 1 : 0,
4953                         texts_freq[(status1 >> 16) & 0xF]);
4954 
4955         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
4956                         (status1 & 0x4000000) ? 1 : 0,
4957                         (status1 & 0x8000000) ? 1 : 0,
4958                         texts_freq[(status1 >> 20) & 0xF]);
4959 
4960         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
4961                         (status3 & 0x400) ? 1 : 0,
4962                         (status3 & 0x800) ? 1 : 0,
4963                         texts_freq[(status2 >> 12) & 0xF]);
4964 
4965 }
4966 
4967 #ifdef CONFIG_SND_DEBUG
4968 static void
4969 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
4970                           struct snd_info_buffer *buffer)
4971 {
4972         struct hdspm *hdspm = entry->private_data;
4973 
4974         int j,i;
4975 
4976         for (i = 0; i < 256 /* 1024*64 */; i += j) {
4977                 snd_iprintf(buffer, "0x%08X: ", i);
4978                 for (j = 0; j < 16; j += 4)
4979                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
4980                 snd_iprintf(buffer, "\n");
4981         }
4982 }
4983 #endif
4984 
4985 
4986 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
4987                           struct snd_info_buffer *buffer)
4988 {
4989         struct hdspm *hdspm = entry->private_data;
4990         int i;
4991 
4992         snd_iprintf(buffer, "# generated by hdspm\n");
4993 
4994         for (i = 0; i < hdspm->max_channels_in; i++) {
4995                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
4996         }
4997 }
4998 
4999 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5000                           struct snd_info_buffer *buffer)
5001 {
5002         struct hdspm *hdspm = entry->private_data;
5003         int i;
5004 
5005         snd_iprintf(buffer, "# generated by hdspm\n");
5006 
5007         for (i = 0; i < hdspm->max_channels_out; i++) {
5008                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5009         }
5010 }
5011 
5012 
5013 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5014 {
5015         struct snd_info_entry *entry;
5016 
5017         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5018                 switch (hdspm->io_type) {
5019                 case AES32:
5020                         snd_info_set_text_ops(entry, hdspm,
5021                                         snd_hdspm_proc_read_aes32);
5022                         break;
5023                 case MADI:
5024                         snd_info_set_text_ops(entry, hdspm,
5025                                         snd_hdspm_proc_read_madi);
5026                         break;
5027                 case MADIface:
5028                         /* snd_info_set_text_ops(entry, hdspm,
5029                          snd_hdspm_proc_read_madiface); */
5030                         break;
5031                 case RayDAT:
5032                         snd_info_set_text_ops(entry, hdspm,
5033                                         snd_hdspm_proc_read_raydat);
5034                         break;
5035                 case AIO:
5036                         break;
5037                 }
5038         }
5039 
5040         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5041                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5042         }
5043 
5044         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5045                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5046         }
5047 
5048 #ifdef CONFIG_SND_DEBUG
5049         /* debug file to read all hdspm registers */
5050         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5051                 snd_info_set_text_ops(entry, hdspm,
5052                                 snd_hdspm_proc_read_debug);
5053 #endif
5054 }
5055 
5056 /*------------------------------------------------------------
5057    hdspm intitialize
5058  ------------------------------------------------------------*/
5059 
5060 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5061 {
5062         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5063            hold it (e.g. during module initialization).
5064            */
5065 
5066         /* set defaults:       */
5067 
5068         hdspm->settings_register = 0;
5069 
5070         switch (hdspm->io_type) {
5071         case MADI:
5072         case MADIface:
5073                 hdspm->control_register =
5074                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5075                 break;
5076 
5077         case RayDAT:
5078         case AIO:
5079                 hdspm->settings_register = 0x1 + 0x1000;
5080                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5081                  * line_out */
5082                 hdspm->control_register =
5083                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5084                 break;
5085 
5086         case AES32:
5087                 hdspm->control_register =
5088                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5089                         hdspm_encode_latency(7) | /* latency max=8192samples */
5090                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5091                         HDSPM_LineOut | /* Analog output in */
5092                         HDSPM_Professional;  /* Professional mode */
5093                 break;
5094         }
5095 
5096         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5097 
5098         if (AES32 == hdspm->io_type) {
5099                 /* No control2 register for AES32 */
5100 #ifdef SNDRV_BIG_ENDIAN
5101                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5102 #else
5103                 hdspm->control2_register = 0;
5104 #endif
5105 
5106                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5107         }
5108         hdspm_compute_period_size(hdspm);
5109 
5110         /* silence everything */
5111 
5112         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5113 
5114         if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5115                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5116         }
5117 
5118         /* set a default rate so that the channel map is set up. */
5119         hdspm_set_rate(hdspm, 48000, 1);
5120 
5121         return 0;
5122 }
5123 
5124 
5125 /*------------------------------------------------------------
5126    interrupt
5127  ------------------------------------------------------------*/
5128 
5129 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5130 {
5131         struct hdspm *hdspm = (struct hdspm *) dev_id;
5132         unsigned int status;
5133         int i, audio, midi, schedule = 0;
5134         /* cycles_t now; */
5135 
5136         status = hdspm_read(hdspm, HDSPM_statusRegister);
5137 
5138         audio = status & HDSPM_audioIRQPending;
5139         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5140                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5141 
5142         /* now = get_cycles(); */
5143         /**
5144          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5145          *          6       4096   ~256053425     ~514672358
5146          *          5       2048   ~128024983     ~257373821
5147          *          4       1024    ~64023706     ~128718089
5148          *          3        512    ~32005945      ~64385999
5149          *          2        256    ~16003039      ~32260176
5150          *          1        128     ~7998738      ~16194507
5151          *          0         64     ~3998231       ~8191558
5152          **/
5153         /*
5154            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5155            now-hdspm->last_interrupt, status & 0xFFC0);
5156            hdspm->last_interrupt = now;
5157         */
5158 
5159         if (!audio && !midi)
5160                 return IRQ_NONE;
5161 
5162         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5163         hdspm->irq_count++;
5164 
5165 
5166         if (audio) {
5167                 if (hdspm->capture_substream)
5168                         snd_pcm_period_elapsed(hdspm->capture_substream);
5169 
5170                 if (hdspm->playback_substream)
5171                         snd_pcm_period_elapsed(hdspm->playback_substream);
5172         }
5173 
5174         if (midi) {
5175                 i = 0;
5176                 while (i < hdspm->midiPorts) {
5177                         if ((hdspm_read(hdspm,
5178                                 hdspm->midi[i].statusIn) & 0xff) &&
5179                                         (status & hdspm->midi[i].irq)) {
5180                                 /* we disable interrupts for this input until
5181                                  * processing is done
5182                                  */
5183                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5184                                 hdspm_write(hdspm, HDSPM_controlRegister,
5185                                                 hdspm->control_register);
5186                                 hdspm->midi[i].pending = 1;
5187                                 schedule = 1;
5188                         }
5189 
5190                         i++;
5191                 }
5192 
5193                 if (schedule)
5194                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5195         }
5196 
5197         return IRQ_HANDLED;
5198 }
5199 
5200 /*------------------------------------------------------------
5201    pcm interface
5202   ------------------------------------------------------------*/
5203 
5204 
5205 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5206                                               *substream)
5207 {
5208         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5209         return hdspm_hw_pointer(hdspm);
5210 }
5211 
5212 
5213 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5214 {
5215         struct snd_pcm_runtime *runtime = substream->runtime;
5216         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5217         struct snd_pcm_substream *other;
5218 
5219         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5220                 other = hdspm->capture_substream;
5221         else
5222                 other = hdspm->playback_substream;
5223 
5224         if (hdspm->running)
5225                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5226         else
5227                 runtime->status->hw_ptr = 0;
5228         if (other) {
5229                 struct snd_pcm_substream *s;
5230                 struct snd_pcm_runtime *oruntime = other->runtime;
5231                 snd_pcm_group_for_each_entry(s, substream) {
5232                         if (s == other) {
5233                                 oruntime->status->hw_ptr =
5234                                         runtime->status->hw_ptr;
5235                                 break;
5236                         }
5237                 }
5238         }
5239         return 0;
5240 }
5241 
5242 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5243                                struct snd_pcm_hw_params *params)
5244 {
5245         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5246         int err;
5247         int i;
5248         pid_t this_pid;
5249         pid_t other_pid;
5250 
5251         spin_lock_irq(&hdspm->lock);
5252 
5253         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5254                 this_pid = hdspm->playback_pid;
5255                 other_pid = hdspm->capture_pid;
5256         } else {
5257                 this_pid = hdspm->capture_pid;
5258                 other_pid = hdspm->playback_pid;
5259         }
5260 
5261         if (other_pid > 0 && this_pid != other_pid) {
5262 
5263                 /* The other stream is open, and not by the same
5264                    task as this one. Make sure that the parameters
5265                    that matter are the same.
5266                    */
5267 
5268                 if (params_rate(params) != hdspm->system_sample_rate) {
5269                         spin_unlock_irq(&hdspm->lock);
5270                         _snd_pcm_hw_param_setempty(params,
5271                                         SNDRV_PCM_HW_PARAM_RATE);
5272                         return -EBUSY;
5273                 }
5274 
5275                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5276                         spin_unlock_irq(&hdspm->lock);
5277                         _snd_pcm_hw_param_setempty(params,
5278                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5279                         return -EBUSY;
5280                 }
5281 
5282         }
5283         /* We're fine. */
5284         spin_unlock_irq(&hdspm->lock);
5285 
5286         /* how to make sure that the rate matches an externally-set one ?   */
5287 
5288         spin_lock_irq(&hdspm->lock);
5289         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5290         if (err < 0) {
5291                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5292                 spin_unlock_irq(&hdspm->lock);
5293                 _snd_pcm_hw_param_setempty(params,
5294                                 SNDRV_PCM_HW_PARAM_RATE);
5295                 return err;
5296         }
5297         spin_unlock_irq(&hdspm->lock);
5298 
5299         err = hdspm_set_interrupt_interval(hdspm,
5300                         params_period_size(params));
5301         if (err < 0) {
5302                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5303                 _snd_pcm_hw_param_setempty(params,
5304                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5305                 return err;
5306         }
5307 
5308         /* Memory allocation, takashi's method, dont know if we should
5309          * spinlock
5310          */
5311         /* malloc all buffer even if not enabled to get sure */
5312         /* Update for MADI rev 204: we need to allocate for all channels,
5313          * otherwise it doesn't work at 96kHz */
5314 
5315         err =
5316                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5317         if (err < 0) {
5318                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5319                 return err;
5320         }
5321 
5322         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5323 
5324                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5325                                 params_channels(params));
5326 
5327                 for (i = 0; i < params_channels(params); ++i)
5328                         snd_hdspm_enable_out(hdspm, i, 1);
5329 
5330                 hdspm->playback_buffer =
5331                         (unsigned char *) substream->runtime->dma_area;
5332                 snd_printdd("Allocated sample buffer for playback at %p\n",
5333                                 hdspm->playback_buffer);
5334         } else {
5335                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5336                                 params_channels(params));
5337 
5338                 for (i = 0; i < params_channels(params); ++i)
5339                         snd_hdspm_enable_in(hdspm, i, 1);
5340 
5341                 hdspm->capture_buffer =
5342                         (unsigned char *) substream->runtime->dma_area;
5343                 snd_printdd("Allocated sample buffer for capture at %p\n",
5344                                 hdspm->capture_buffer);
5345         }
5346 
5347         /*
5348            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5349            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5350            "playback" : "capture",
5351            snd_pcm_sgbuf_get_addr(substream, 0));
5352            */
5353         /*
5354            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5355            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5356            "playback" : "capture",
5357            params_rate(params), params_channels(params),
5358            params_buffer_size(params));
5359            */
5360 
5361 
5362         /* Switch to native float format if requested */
5363         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5364                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5365                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5366 
5367                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5368         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5369                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5370                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5371 
5372                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5373         }
5374         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5375 
5376         return 0;
5377 }
5378 
5379 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5380 {
5381         int i;
5382         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5383 
5384         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5385 
5386                 /* params_channels(params) should be enough,
5387                    but to get sure in case of error */
5388                 for (i = 0; i < hdspm->max_channels_out; ++i)
5389                         snd_hdspm_enable_out(hdspm, i, 0);
5390 
5391                 hdspm->playback_buffer = NULL;
5392         } else {
5393                 for (i = 0; i < hdspm->max_channels_in; ++i)
5394                         snd_hdspm_enable_in(hdspm, i, 0);
5395 
5396                 hdspm->capture_buffer = NULL;
5397 
5398         }
5399 
5400         snd_pcm_lib_free_pages(substream);
5401 
5402         return 0;
5403 }
5404 
5405 
5406 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5407                 struct snd_pcm_channel_info *info)
5408 {
5409         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5410 
5411         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5412                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5413                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5414                         return -EINVAL;
5415                 }
5416 
5417                 if (hdspm->channel_map_out[info->channel] < 0) {
5418                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5419                         return -EINVAL;
5420                 }
5421 
5422                 info->offset = hdspm->channel_map_out[info->channel] *
5423                         HDSPM_CHANNEL_BUFFER_BYTES;
5424         } else {
5425                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5426                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5427                         return -EINVAL;
5428                 }
5429 
5430                 if (hdspm->channel_map_in[info->channel] < 0) {
5431                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5432                         return -EINVAL;
5433                 }
5434 
5435                 info->offset = hdspm->channel_map_in[info->channel] *
5436                         HDSPM_CHANNEL_BUFFER_BYTES;
5437         }
5438 
5439         info->first = 0;
5440         info->step = 32;
5441         return 0;
5442 }
5443 
5444 
5445 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5446                 unsigned int cmd, void *arg)
5447 {
5448         switch (cmd) {
5449         case SNDRV_PCM_IOCTL1_RESET:
5450                 return snd_hdspm_reset(substream);
5451 
5452         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5453                 {
5454                         struct snd_pcm_channel_info *info = arg;
5455                         return snd_hdspm_channel_info(substream, info);
5456                 }
5457         default:
5458                 break;
5459         }
5460 
5461         return snd_pcm_lib_ioctl(substream, cmd, arg);
5462 }
5463 
5464 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5465 {
5466         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5467         struct snd_pcm_substream *other;
5468         int running;
5469 
5470         spin_lock(&hdspm->lock);
5471         running = hdspm->running;
5472         switch (cmd) {
5473         case SNDRV_PCM_TRIGGER_START:
5474                 running |= 1 << substream->stream;
5475                 break;
5476         case SNDRV_PCM_TRIGGER_STOP:
5477                 running &= ~(1 << substream->stream);
5478                 break;
5479         default:
5480                 snd_BUG();
5481                 spin_unlock(&hdspm->lock);
5482                 return -EINVAL;
5483         }
5484         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5485                 other = hdspm->capture_substream;
5486         else
5487                 other = hdspm->playback_substream;
5488 
5489         if (other) {
5490                 struct snd_pcm_substream *s;
5491                 snd_pcm_group_for_each_entry(s, substream) {
5492                         if (s == other) {
5493                                 snd_pcm_trigger_done(s, substream);
5494                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5495                                         running |= 1 << s->stream;
5496                                 else
5497                                         running &= ~(1 << s->stream);
5498                                 goto _ok;
5499                         }
5500                 }
5501                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5502                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5503                                         && substream->stream ==
5504                                         SNDRV_PCM_STREAM_CAPTURE)
5505                                 hdspm_silence_playback(hdspm);
5506                 } else {
5507                         if (running &&
5508                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5509                                 hdspm_silence_playback(hdspm);
5510                 }
5511         } else {
5512                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5513                         hdspm_silence_playback(hdspm);
5514         }
5515 _ok:
5516         snd_pcm_trigger_done(substream, substream);
5517         if (!hdspm->running && running)
5518                 hdspm_start_audio(hdspm);
5519         else if (hdspm->running && !running)
5520                 hdspm_stop_audio(hdspm);
5521         hdspm->running = running;
5522         spin_unlock(&hdspm->lock);
5523 
5524         return 0;
5525 }
5526 
5527 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5528 {
5529         return 0;
5530 }
5531 
5532 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5533         .info = (SNDRV_PCM_INFO_MMAP |
5534                  SNDRV_PCM_INFO_MMAP_VALID |
5535                  SNDRV_PCM_INFO_NONINTERLEAVED |
5536                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5537         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5538         .rates = (SNDRV_PCM_RATE_32000 |
5539                   SNDRV_PCM_RATE_44100 |
5540                   SNDRV_PCM_RATE_48000 |
5541                   SNDRV_PCM_RATE_64000 |
5542                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5543                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5544         .rate_min = 32000,
5545         .rate_max = 192000,
5546         .channels_min = 1,
5547         .channels_max = HDSPM_MAX_CHANNELS,
5548         .buffer_bytes_max =
5549             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5550         .period_bytes_min = (32 * 4),
5551         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5552         .periods_min = 2,
5553         .periods_max = 512,
5554         .fifo_size = 0
5555 };
5556 
5557 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5558         .info = (SNDRV_PCM_INFO_MMAP |
5559                  SNDRV_PCM_INFO_MMAP_VALID |
5560                  SNDRV_PCM_INFO_NONINTERLEAVED |
5561                  SNDRV_PCM_INFO_SYNC_START),
5562         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5563         .rates = (SNDRV_PCM_RATE_32000 |
5564                   SNDRV_PCM_RATE_44100 |
5565                   SNDRV_PCM_RATE_48000 |
5566                   SNDRV_PCM_RATE_64000 |
5567                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5568                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5569         .rate_min = 32000,
5570         .rate_max = 192000,
5571         .channels_min = 1,
5572         .channels_max = HDSPM_MAX_CHANNELS,
5573         .buffer_bytes_max =
5574             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5575         .period_bytes_min = (32 * 4),
5576         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5577         .periods_min = 2,
5578         .periods_max = 512,
5579         .fifo_size = 0
5580 };
5581 
5582 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5583                                            struct snd_pcm_hw_rule *rule)
5584 {
5585         struct hdspm *hdspm = rule->private;
5586         struct snd_interval *c =
5587             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5588         struct snd_interval *r =
5589             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5590 
5591         if (r->min > 96000 && r->max <= 192000) {
5592                 struct snd_interval t = {
5593                         .min = hdspm->qs_in_channels,
5594                         .max = hdspm->qs_in_channels,
5595                         .integer = 1,
5596                 };
5597                 return snd_interval_refine(c, &t);
5598         } else if (r->min > 48000 && r->max <= 96000) {
5599                 struct snd_interval t = {
5600                         .min = hdspm->ds_in_channels,
5601                         .max = hdspm->ds_in_channels,
5602                         .integer = 1,
5603                 };
5604                 return snd_interval_refine(c, &t);
5605         } else if (r->max < 64000) {
5606                 struct snd_interval t = {
5607                         .min = hdspm->ss_in_channels,
5608                         .max = hdspm->ss_in_channels,
5609                         .integer = 1,
5610                 };
5611                 return snd_interval_refine(c, &t);
5612         }
5613 
5614         return 0;
5615 }
5616 
5617 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5618                                            struct snd_pcm_hw_rule * rule)
5619 {
5620         struct hdspm *hdspm = rule->private;
5621         struct snd_interval *c =
5622             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5623         struct snd_interval *r =
5624             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5625 
5626         if (r->min > 96000 && r->max <= 192000) {
5627                 struct snd_interval t = {
5628                         .min = hdspm->qs_out_channels,
5629                         .max = hdspm->qs_out_channels,
5630                         .integer = 1,
5631                 };
5632                 return snd_interval_refine(c, &t);
5633         } else if (r->min > 48000 && r->max <= 96000) {
5634                 struct snd_interval t = {
5635                         .min = hdspm->ds_out_channels,
5636                         .max = hdspm->ds_out_channels,
5637                         .integer = 1,
5638                 };
5639                 return snd_interval_refine(c, &t);
5640         } else if (r->max < 64000) {
5641                 struct snd_interval t = {
5642                         .min = hdspm->ss_out_channels,
5643                         .max = hdspm->ss_out_channels,
5644                         .integer = 1,
5645                 };
5646                 return snd_interval_refine(c, &t);
5647         } else {
5648         }
5649         return 0;
5650 }
5651 
5652 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5653                                            struct snd_pcm_hw_rule * rule)
5654 {
5655         struct hdspm *hdspm = rule->private;
5656         struct snd_interval *c =
5657             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5658         struct snd_interval *r =
5659             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5660 
5661         if (c->min >= hdspm->ss_in_channels) {
5662                 struct snd_interval t = {
5663                         .min = 32000,
5664                         .max = 48000,
5665                         .integer = 1,
5666                 };
5667                 return snd_interval_refine(r, &t);
5668         } else if (c->max <= hdspm->qs_in_channels) {
5669                 struct snd_interval t = {
5670                         .min = 128000,
5671                         .max = 192000,
5672                         .integer = 1,
5673                 };
5674                 return snd_interval_refine(r, &t);
5675         } else if (c->max <= hdspm->ds_in_channels) {
5676                 struct snd_interval t = {
5677                         .min = 64000,
5678                         .max = 96000,
5679                         .integer = 1,
5680                 };
5681                 return snd_interval_refine(r, &t);
5682         }
5683 
5684         return 0;
5685 }
5686 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5687                                            struct snd_pcm_hw_rule *rule)
5688 {
5689         struct hdspm *hdspm = rule->private;
5690         struct snd_interval *c =
5691             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5692         struct snd_interval *r =
5693             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5694 
5695         if (c->min >= hdspm->ss_out_channels) {
5696                 struct snd_interval t = {
5697                         .min = 32000,
5698                         .max = 48000,
5699                         .integer = 1,
5700                 };
5701                 return snd_interval_refine(r, &t);
5702         } else if (c->max <= hdspm->qs_out_channels) {
5703                 struct snd_interval t = {
5704                         .min = 128000,
5705                         .max = 192000,
5706                         .integer = 1,
5707                 };
5708                 return snd_interval_refine(r, &t);
5709         } else if (c->max <= hdspm->ds_out_channels) {
5710                 struct snd_interval t = {
5711                         .min = 64000,
5712                         .max = 96000,
5713                         .integer = 1,
5714                 };
5715                 return snd_interval_refine(r, &t);
5716         }
5717 
5718         return 0;
5719 }
5720 
5721 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5722                                       struct snd_pcm_hw_rule *rule)
5723 {
5724         unsigned int list[3];
5725         struct hdspm *hdspm = rule->private;
5726         struct snd_interval *c = hw_param_interval(params,
5727