~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/sound/soc/codecs/rt5663.c

Version: ~ [ linux-5.14-rc3 ] ~ [ linux-5.13.5 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.53 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.135 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.198 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.240 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.276 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.276 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.18.140 ] ~ [ linux-3.16.85 ] ~ [ linux-3.14.79 ] ~ [ linux-3.12.74 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * rt5663.c  --  RT5663 ALSA SoC audio codec driver
  3  *
  4  * Copyright 2016 Realtek Semiconductor Corp.
  5  * Author: Jack Yu <jack.yu@realtek.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  */
 11 #include <linux/module.h>
 12 #include <linux/moduleparam.h>
 13 #include <linux/init.h>
 14 #include <linux/delay.h>
 15 #include <linux/pm.h>
 16 #include <linux/i2c.h>
 17 #include <linux/platform_device.h>
 18 #include <linux/spi/spi.h>
 19 #include <linux/acpi.h>
 20 #include <linux/regulator/consumer.h>
 21 #include <linux/workqueue.h>
 22 #include <sound/core.h>
 23 #include <sound/pcm.h>
 24 #include <sound/pcm_params.h>
 25 #include <sound/jack.h>
 26 #include <sound/soc.h>
 27 #include <sound/soc-dapm.h>
 28 #include <sound/initval.h>
 29 #include <sound/tlv.h>
 30 
 31 #include "rt5663.h"
 32 #include "rl6231.h"
 33 
 34 #define RT5663_DEVICE_ID_2 0x6451
 35 #define RT5663_DEVICE_ID_1 0x6406
 36 
 37 #define RT5663_POWER_ON_DELAY_MS 300
 38 #define RT5663_SUPPLY_CURRENT_UA 500000
 39 
 40 enum {
 41         CODEC_VER_1,
 42         CODEC_VER_0,
 43 };
 44 
 45 struct impedance_mapping_table {
 46         unsigned int imp_min;
 47         unsigned int imp_max;
 48         unsigned int vol;
 49         unsigned int dc_offset_l_manual;
 50         unsigned int dc_offset_r_manual;
 51         unsigned int dc_offset_l_manual_mic;
 52         unsigned int dc_offset_r_manual_mic;
 53 };
 54 
 55 static const char *const rt5663_supply_names[] = {
 56         "avdd",
 57         "cpvdd",
 58 };
 59 
 60 struct rt5663_priv {
 61         struct snd_soc_component *component;
 62         struct rt5663_platform_data pdata;
 63         struct regmap *regmap;
 64         struct delayed_work jack_detect_work, jd_unplug_work;
 65         struct snd_soc_jack *hs_jack;
 66         struct timer_list btn_check_timer;
 67         struct impedance_mapping_table *imp_table;
 68         struct regulator_bulk_data supplies[ARRAY_SIZE(rt5663_supply_names)];
 69 
 70         int codec_ver;
 71         int sysclk;
 72         int sysclk_src;
 73         int lrck;
 74 
 75         int pll_src;
 76         int pll_in;
 77         int pll_out;
 78 
 79         int jack_type;
 80 };
 81 
 82 static const struct reg_sequence rt5663_patch_list[] = {
 83         { 0x002a, 0x8020 },
 84         { 0x0086, 0x0028 },
 85         { 0x0100, 0xa020 },
 86         { 0x0117, 0x0f28 },
 87         { 0x02fb, 0x8089 },
 88 };
 89 
 90 static const struct reg_default rt5663_v2_reg[] = {
 91         { 0x0000, 0x0000 },
 92         { 0x0001, 0xc8c8 },
 93         { 0x0002, 0x8080 },
 94         { 0x0003, 0x8000 },
 95         { 0x0004, 0xc80a },
 96         { 0x0005, 0x0000 },
 97         { 0x0006, 0x0000 },
 98         { 0x0007, 0x0000 },
 99         { 0x000a, 0x0000 },
100         { 0x000b, 0x0000 },
101         { 0x000c, 0x0000 },
102         { 0x000d, 0x0000 },
103         { 0x000f, 0x0808 },
104         { 0x0010, 0x4000 },
105         { 0x0011, 0x0000 },
106         { 0x0012, 0x1404 },
107         { 0x0013, 0x1000 },
108         { 0x0014, 0xa00a },
109         { 0x0015, 0x0404 },
110         { 0x0016, 0x0404 },
111         { 0x0017, 0x0011 },
112         { 0x0018, 0xafaf },
113         { 0x0019, 0xafaf },
114         { 0x001a, 0xafaf },
115         { 0x001b, 0x0011 },
116         { 0x001c, 0x2f2f },
117         { 0x001d, 0x2f2f },
118         { 0x001e, 0x2f2f },
119         { 0x001f, 0x0000 },
120         { 0x0020, 0x0000 },
121         { 0x0021, 0x0000 },
122         { 0x0022, 0x5757 },
123         { 0x0023, 0x0039 },
124         { 0x0024, 0x000b },
125         { 0x0026, 0xc0c0 },
126         { 0x0027, 0xc0c0 },
127         { 0x0028, 0xc0c0 },
128         { 0x0029, 0x8080 },
129         { 0x002a, 0xaaaa },
130         { 0x002b, 0xaaaa },
131         { 0x002c, 0xaba8 },
132         { 0x002d, 0x0000 },
133         { 0x002e, 0x0000 },
134         { 0x002f, 0x0000 },
135         { 0x0030, 0x0000 },
136         { 0x0031, 0x5000 },
137         { 0x0032, 0x0000 },
138         { 0x0033, 0x0000 },
139         { 0x0034, 0x0000 },
140         { 0x0035, 0x0000 },
141         { 0x003a, 0x0000 },
142         { 0x003b, 0x0000 },
143         { 0x003c, 0x00ff },
144         { 0x003d, 0x0000 },
145         { 0x003e, 0x00ff },
146         { 0x003f, 0x0000 },
147         { 0x0040, 0x0000 },
148         { 0x0041, 0x00ff },
149         { 0x0042, 0x0000 },
150         { 0x0043, 0x00ff },
151         { 0x0044, 0x0c0c },
152         { 0x0049, 0xc00b },
153         { 0x004a, 0x0000 },
154         { 0x004b, 0x031f },
155         { 0x004d, 0x0000 },
156         { 0x004e, 0x001f },
157         { 0x004f, 0x0000 },
158         { 0x0050, 0x001f },
159         { 0x0052, 0xf000 },
160         { 0x0061, 0x0000 },
161         { 0x0062, 0x0000 },
162         { 0x0063, 0x003e },
163         { 0x0064, 0x0000 },
164         { 0x0065, 0x0000 },
165         { 0x0066, 0x003f },
166         { 0x0067, 0x0000 },
167         { 0x006b, 0x0000 },
168         { 0x006d, 0xff00 },
169         { 0x006e, 0x2808 },
170         { 0x006f, 0x000a },
171         { 0x0070, 0x8000 },
172         { 0x0071, 0x8000 },
173         { 0x0072, 0x8000 },
174         { 0x0073, 0x7000 },
175         { 0x0074, 0x7770 },
176         { 0x0075, 0x0002 },
177         { 0x0076, 0x0001 },
178         { 0x0078, 0x00f0 },
179         { 0x0079, 0x0000 },
180         { 0x007a, 0x0000 },
181         { 0x007b, 0x0000 },
182         { 0x007c, 0x0000 },
183         { 0x007d, 0x0123 },
184         { 0x007e, 0x4500 },
185         { 0x007f, 0x8003 },
186         { 0x0080, 0x0000 },
187         { 0x0081, 0x0000 },
188         { 0x0082, 0x0000 },
189         { 0x0083, 0x0000 },
190         { 0x0084, 0x0000 },
191         { 0x0085, 0x0000 },
192         { 0x0086, 0x0008 },
193         { 0x0087, 0x0000 },
194         { 0x0088, 0x0000 },
195         { 0x0089, 0x0000 },
196         { 0x008a, 0x0000 },
197         { 0x008b, 0x0000 },
198         { 0x008c, 0x0003 },
199         { 0x008e, 0x0060 },
200         { 0x008f, 0x1000 },
201         { 0x0091, 0x0c26 },
202         { 0x0092, 0x0073 },
203         { 0x0093, 0x0000 },
204         { 0x0094, 0x0080 },
205         { 0x0098, 0x0000 },
206         { 0x0099, 0x0000 },
207         { 0x009a, 0x0007 },
208         { 0x009f, 0x0000 },
209         { 0x00a0, 0x0000 },
210         { 0x00a1, 0x0002 },
211         { 0x00a2, 0x0001 },
212         { 0x00a3, 0x0002 },
213         { 0x00a4, 0x0001 },
214         { 0x00ae, 0x2040 },
215         { 0x00af, 0x0000 },
216         { 0x00b6, 0x0000 },
217         { 0x00b7, 0x0000 },
218         { 0x00b8, 0x0000 },
219         { 0x00b9, 0x0000 },
220         { 0x00ba, 0x0002 },
221         { 0x00bb, 0x0000 },
222         { 0x00be, 0x0000 },
223         { 0x00c0, 0x0000 },
224         { 0x00c1, 0x0aaa },
225         { 0x00c2, 0xaa80 },
226         { 0x00c3, 0x0003 },
227         { 0x00c4, 0x0000 },
228         { 0x00d0, 0x0000 },
229         { 0x00d1, 0x2244 },
230         { 0x00d2, 0x0000 },
231         { 0x00d3, 0x3300 },
232         { 0x00d4, 0x2200 },
233         { 0x00d9, 0x0809 },
234         { 0x00da, 0x0000 },
235         { 0x00db, 0x0008 },
236         { 0x00dc, 0x00c0 },
237         { 0x00dd, 0x6724 },
238         { 0x00de, 0x3131 },
239         { 0x00df, 0x0008 },
240         { 0x00e0, 0x4000 },
241         { 0x00e1, 0x3131 },
242         { 0x00e2, 0x600c },
243         { 0x00ea, 0xb320 },
244         { 0x00eb, 0x0000 },
245         { 0x00ec, 0xb300 },
246         { 0x00ed, 0x0000 },
247         { 0x00ee, 0xb320 },
248         { 0x00ef, 0x0000 },
249         { 0x00f0, 0x0201 },
250         { 0x00f1, 0x0ddd },
251         { 0x00f2, 0x0ddd },
252         { 0x00f6, 0x0000 },
253         { 0x00f7, 0x0000 },
254         { 0x00f8, 0x0000 },
255         { 0x00fa, 0x0000 },
256         { 0x00fb, 0x0000 },
257         { 0x00fc, 0x0000 },
258         { 0x00fd, 0x0000 },
259         { 0x00fe, 0x10ec },
260         { 0x00ff, 0x6451 },
261         { 0x0100, 0xaaaa },
262         { 0x0101, 0x000a },
263         { 0x010a, 0xaaaa },
264         { 0x010b, 0xa0a0 },
265         { 0x010c, 0xaeae },
266         { 0x010d, 0xaaaa },
267         { 0x010e, 0xaaaa },
268         { 0x010f, 0xaaaa },
269         { 0x0110, 0xe002 },
270         { 0x0111, 0xa602 },
271         { 0x0112, 0xaaaa },
272         { 0x0113, 0x2000 },
273         { 0x0117, 0x0f00 },
274         { 0x0125, 0x0420 },
275         { 0x0132, 0x0000 },
276         { 0x0133, 0x0000 },
277         { 0x0136, 0x5555 },
278         { 0x0137, 0x5540 },
279         { 0x0138, 0x3700 },
280         { 0x0139, 0x79a1 },
281         { 0x013a, 0x2020 },
282         { 0x013b, 0x2020 },
283         { 0x013c, 0x2005 },
284         { 0x013f, 0x0000 },
285         { 0x0145, 0x0002 },
286         { 0x0146, 0x0000 },
287         { 0x0147, 0x0000 },
288         { 0x0148, 0x0000 },
289         { 0x0160, 0x4ec0 },
290         { 0x0161, 0x0080 },
291         { 0x0162, 0x0200 },
292         { 0x0163, 0x0800 },
293         { 0x0164, 0x0000 },
294         { 0x0165, 0x0000 },
295         { 0x0166, 0x0000 },
296         { 0x0167, 0x000f },
297         { 0x0168, 0x000f },
298         { 0x0170, 0x4e80 },
299         { 0x0171, 0x0080 },
300         { 0x0172, 0x0200 },
301         { 0x0173, 0x0800 },
302         { 0x0174, 0x00ff },
303         { 0x0175, 0x0000 },
304         { 0x0190, 0x4131 },
305         { 0x0191, 0x4131 },
306         { 0x0192, 0x4131 },
307         { 0x0193, 0x4131 },
308         { 0x0194, 0x0000 },
309         { 0x0195, 0x0000 },
310         { 0x0196, 0x0000 },
311         { 0x0197, 0x0000 },
312         { 0x0198, 0x0000 },
313         { 0x0199, 0x0000 },
314         { 0x01a0, 0x1e64 },
315         { 0x01a1, 0x06a3 },
316         { 0x01a2, 0x0000 },
317         { 0x01a3, 0x0000 },
318         { 0x01a4, 0x0000 },
319         { 0x01a5, 0x0000 },
320         { 0x01a6, 0x0000 },
321         { 0x01a7, 0x0000 },
322         { 0x01a8, 0x0000 },
323         { 0x01a9, 0x0000 },
324         { 0x01aa, 0x0000 },
325         { 0x01ab, 0x0000 },
326         { 0x01b5, 0x0000 },
327         { 0x01b6, 0x01c3 },
328         { 0x01b7, 0x02a0 },
329         { 0x01b8, 0x03e9 },
330         { 0x01b9, 0x1389 },
331         { 0x01ba, 0xc351 },
332         { 0x01bb, 0x0009 },
333         { 0x01bc, 0x0018 },
334         { 0x01bd, 0x002a },
335         { 0x01be, 0x004c },
336         { 0x01bf, 0x0097 },
337         { 0x01c0, 0x433d },
338         { 0x01c1, 0x0000 },
339         { 0x01c2, 0x0000 },
340         { 0x01c3, 0x0000 },
341         { 0x01c4, 0x0000 },
342         { 0x01c5, 0x0000 },
343         { 0x01c6, 0x0000 },
344         { 0x01c7, 0x0000 },
345         { 0x01c8, 0x40af },
346         { 0x01c9, 0x0702 },
347         { 0x01ca, 0x0000 },
348         { 0x01cb, 0x0000 },
349         { 0x01cc, 0x5757 },
350         { 0x01cd, 0x5757 },
351         { 0x01ce, 0x5757 },
352         { 0x01cf, 0x5757 },
353         { 0x01d0, 0x5757 },
354         { 0x01d1, 0x5757 },
355         { 0x01d2, 0x5757 },
356         { 0x01d3, 0x5757 },
357         { 0x01d4, 0x5757 },
358         { 0x01d5, 0x5757 },
359         { 0x01d6, 0x003c },
360         { 0x01da, 0x0000 },
361         { 0x01db, 0x0000 },
362         { 0x01dc, 0x0000 },
363         { 0x01de, 0x7c00 },
364         { 0x01df, 0x0320 },
365         { 0x01e0, 0x06a1 },
366         { 0x01e1, 0x0000 },
367         { 0x01e2, 0x0000 },
368         { 0x01e3, 0x0000 },
369         { 0x01e4, 0x0000 },
370         { 0x01e5, 0x0000 },
371         { 0x01e6, 0x0001 },
372         { 0x01e7, 0x0000 },
373         { 0x01e8, 0x0000 },
374         { 0x01ea, 0x0000 },
375         { 0x01eb, 0x0000 },
376         { 0x01ec, 0x0000 },
377         { 0x01ed, 0x0000 },
378         { 0x01ee, 0x0000 },
379         { 0x01ef, 0x0000 },
380         { 0x01f0, 0x0000 },
381         { 0x01f1, 0x0000 },
382         { 0x01f2, 0x0000 },
383         { 0x01f3, 0x0000 },
384         { 0x01f4, 0x0000 },
385         { 0x0200, 0x0000 },
386         { 0x0201, 0x0000 },
387         { 0x0202, 0x0000 },
388         { 0x0203, 0x0000 },
389         { 0x0204, 0x0000 },
390         { 0x0205, 0x0000 },
391         { 0x0206, 0x0000 },
392         { 0x0207, 0x0000 },
393         { 0x0208, 0x0000 },
394         { 0x0210, 0x60b1 },
395         { 0x0211, 0xa000 },
396         { 0x0212, 0x024c },
397         { 0x0213, 0xf7ff },
398         { 0x0214, 0x024c },
399         { 0x0215, 0x0102 },
400         { 0x0216, 0x00a3 },
401         { 0x0217, 0x0048 },
402         { 0x0218, 0x92c0 },
403         { 0x0219, 0x0000 },
404         { 0x021a, 0x00c8 },
405         { 0x021b, 0x0020 },
406         { 0x02fa, 0x0000 },
407         { 0x02fb, 0x0000 },
408         { 0x02fc, 0x0000 },
409         { 0x02ff, 0x0110 },
410         { 0x0300, 0x001f },
411         { 0x0301, 0x032c },
412         { 0x0302, 0x5f21 },
413         { 0x0303, 0x4000 },
414         { 0x0304, 0x4000 },
415         { 0x0305, 0x06d5 },
416         { 0x0306, 0x8000 },
417         { 0x0307, 0x0700 },
418         { 0x0310, 0x4560 },
419         { 0x0311, 0xa4a8 },
420         { 0x0312, 0x7418 },
421         { 0x0313, 0x0000 },
422         { 0x0314, 0x0006 },
423         { 0x0315, 0xffff },
424         { 0x0316, 0xc400 },
425         { 0x0317, 0x0000 },
426         { 0x0330, 0x00a6 },
427         { 0x0331, 0x04c3 },
428         { 0x0332, 0x27c8 },
429         { 0x0333, 0xbf50 },
430         { 0x0334, 0x0045 },
431         { 0x0335, 0x0007 },
432         { 0x0336, 0x7418 },
433         { 0x0337, 0x0501 },
434         { 0x0338, 0x0000 },
435         { 0x0339, 0x0010 },
436         { 0x033a, 0x1010 },
437         { 0x03c0, 0x7e00 },
438         { 0x03c1, 0x8000 },
439         { 0x03c2, 0x8000 },
440         { 0x03c3, 0x8000 },
441         { 0x03c4, 0x8000 },
442         { 0x03c5, 0x8000 },
443         { 0x03c6, 0x8000 },
444         { 0x03c7, 0x8000 },
445         { 0x03c8, 0x8000 },
446         { 0x03c9, 0x8000 },
447         { 0x03ca, 0x8000 },
448         { 0x03cb, 0x8000 },
449         { 0x03cc, 0x8000 },
450         { 0x03d0, 0x0000 },
451         { 0x03d1, 0x0000 },
452         { 0x03d2, 0x0000 },
453         { 0x03d3, 0x0000 },
454         { 0x03d4, 0x2000 },
455         { 0x03d5, 0x2000 },
456         { 0x03d6, 0x0000 },
457         { 0x03d7, 0x0000 },
458         { 0x03d8, 0x2000 },
459         { 0x03d9, 0x2000 },
460         { 0x03da, 0x2000 },
461         { 0x03db, 0x2000 },
462         { 0x03dc, 0x0000 },
463         { 0x03dd, 0x0000 },
464         { 0x03de, 0x0000 },
465         { 0x03df, 0x2000 },
466         { 0x03e0, 0x0000 },
467         { 0x03e1, 0x0000 },
468         { 0x03e2, 0x0000 },
469         { 0x03e3, 0x0000 },
470         { 0x03e4, 0x0000 },
471         { 0x03e5, 0x0000 },
472         { 0x03e6, 0x0000 },
473         { 0x03e7, 0x0000 },
474         { 0x03e8, 0x0000 },
475         { 0x03e9, 0x0000 },
476         { 0x03ea, 0x0000 },
477         { 0x03eb, 0x0000 },
478         { 0x03ec, 0x0000 },
479         { 0x03ed, 0x0000 },
480         { 0x03ee, 0x0000 },
481         { 0x03ef, 0x0000 },
482         { 0x03f0, 0x0800 },
483         { 0x03f1, 0x0800 },
484         { 0x03f2, 0x0800 },
485         { 0x03f3, 0x0800 },
486         { 0x03fe, 0x0000 },
487         { 0x03ff, 0x0000 },
488         { 0x07f0, 0x0000 },
489         { 0x07fa, 0x0000 },
490 };
491 
492 static const struct reg_default rt5663_reg[] = {
493         { 0x0000, 0x0000 },
494         { 0x0002, 0x0008 },
495         { 0x0005, 0x1000 },
496         { 0x0006, 0x1000 },
497         { 0x000a, 0x0000 },
498         { 0x0010, 0x000f },
499         { 0x0015, 0x42f1 },
500         { 0x0016, 0x0000 },
501         { 0x0018, 0x000b },
502         { 0x0019, 0xafaf },
503         { 0x001c, 0x2f2f },
504         { 0x001f, 0x0000 },
505         { 0x0022, 0x5757 },
506         { 0x0023, 0x0039 },
507         { 0x0026, 0xc0c0 },
508         { 0x0029, 0x8080 },
509         { 0x002a, 0x8020 },
510         { 0x002c, 0x000c },
511         { 0x002d, 0x0000 },
512         { 0x0040, 0x0808 },
513         { 0x0061, 0x0000 },
514         { 0x0062, 0x0000 },
515         { 0x0063, 0x003e },
516         { 0x0064, 0x0000 },
517         { 0x0065, 0x0000 },
518         { 0x0066, 0x0000 },
519         { 0x006b, 0x0000 },
520         { 0x006e, 0x0000 },
521         { 0x006f, 0x0000 },
522         { 0x0070, 0x8020 },
523         { 0x0073, 0x1000 },
524         { 0x0074, 0xe400 },
525         { 0x0075, 0x0002 },
526         { 0x0076, 0x0001 },
527         { 0x0077, 0x00f0 },
528         { 0x0078, 0x0000 },
529         { 0x0079, 0x0000 },
530         { 0x007a, 0x0123 },
531         { 0x007b, 0x8003 },
532         { 0x0080, 0x0000 },
533         { 0x0081, 0x0000 },
534         { 0x0082, 0x0000 },
535         { 0x0083, 0x0000 },
536         { 0x0084, 0x0000 },
537         { 0x0086, 0x0028 },
538         { 0x0087, 0x0000 },
539         { 0x008a, 0x0000 },
540         { 0x008b, 0x0000 },
541         { 0x008c, 0x0003 },
542         { 0x008e, 0x0008 },
543         { 0x008f, 0x1000 },
544         { 0x0090, 0x0646 },
545         { 0x0091, 0x0e3e },
546         { 0x0092, 0x1071 },
547         { 0x0093, 0x0000 },
548         { 0x0094, 0x0080 },
549         { 0x0097, 0x0000 },
550         { 0x0098, 0x0000 },
551         { 0x009a, 0x0000 },
552         { 0x009f, 0x0000 },
553         { 0x00ae, 0x6000 },
554         { 0x00af, 0x0000 },
555         { 0x00b6, 0x0000 },
556         { 0x00b7, 0x0000 },
557         { 0x00b8, 0x0000 },
558         { 0x00ba, 0x0000 },
559         { 0x00bb, 0x0000 },
560         { 0x00be, 0x0000 },
561         { 0x00bf, 0x0000 },
562         { 0x00c0, 0x0000 },
563         { 0x00c1, 0x0000 },
564         { 0x00c5, 0x0000 },
565         { 0x00cb, 0xa02f },
566         { 0x00cc, 0x0000 },
567         { 0x00cd, 0x0e02 },
568         { 0x00d9, 0x08f9 },
569         { 0x00db, 0x0008 },
570         { 0x00dc, 0x00c0 },
571         { 0x00dd, 0x6729 },
572         { 0x00de, 0x3131 },
573         { 0x00df, 0x0008 },
574         { 0x00e0, 0x4000 },
575         { 0x00e1, 0x3131 },
576         { 0x00e2, 0x0043 },
577         { 0x00e4, 0x400b },
578         { 0x00e5, 0x8031 },
579         { 0x00e6, 0x3080 },
580         { 0x00e7, 0x4100 },
581         { 0x00e8, 0x1400 },
582         { 0x00e9, 0xe00a },
583         { 0x00ea, 0x0404 },
584         { 0x00eb, 0x0404 },
585         { 0x00ec, 0xb320 },
586         { 0x00ed, 0x0000 },
587         { 0x00f4, 0x0000 },
588         { 0x00f6, 0x0000 },
589         { 0x00f8, 0x0000 },
590         { 0x00fa, 0x8000 },
591         { 0x00fd, 0x0001 },
592         { 0x00fe, 0x10ec },
593         { 0x00ff, 0x6406 },
594         { 0x0100, 0xa020 },
595         { 0x0108, 0x4444 },
596         { 0x0109, 0x4444 },
597         { 0x010a, 0xaaaa },
598         { 0x010b, 0x00a0 },
599         { 0x010c, 0x8aaa },
600         { 0x010d, 0xaaaa },
601         { 0x010e, 0x2aaa },
602         { 0x010f, 0x002a },
603         { 0x0110, 0xa0a4 },
604         { 0x0111, 0x4602 },
605         { 0x0112, 0x0101 },
606         { 0x0113, 0x2000 },
607         { 0x0114, 0x0000 },
608         { 0x0116, 0x0000 },
609         { 0x0117, 0x0f28 },
610         { 0x0118, 0x0006 },
611         { 0x0125, 0x2424 },
612         { 0x0126, 0x5550 },
613         { 0x0127, 0x0400 },
614         { 0x0128, 0x7711 },
615         { 0x0132, 0x0004 },
616         { 0x0137, 0x5441 },
617         { 0x0139, 0x79a1 },
618         { 0x013a, 0x30c0 },
619         { 0x013b, 0x2000 },
620         { 0x013c, 0x2005 },
621         { 0x013d, 0x30c0 },
622         { 0x013e, 0x0000 },
623         { 0x0140, 0x3700 },
624         { 0x0141, 0x1f00 },
625         { 0x0144, 0x0000 },
626         { 0x0145, 0x0002 },
627         { 0x0146, 0x0000 },
628         { 0x0160, 0x0e80 },
629         { 0x0161, 0x0080 },
630         { 0x0162, 0x0200 },
631         { 0x0163, 0x0800 },
632         { 0x0164, 0x0000 },
633         { 0x0165, 0x0000 },
634         { 0x0166, 0x0000 },
635         { 0x0167, 0x1417 },
636         { 0x0168, 0x0017 },
637         { 0x0169, 0x0017 },
638         { 0x0180, 0x2000 },
639         { 0x0181, 0x0000 },
640         { 0x0182, 0x0000 },
641         { 0x0183, 0x2000 },
642         { 0x0184, 0x0000 },
643         { 0x0185, 0x0000 },
644         { 0x01b0, 0x4b30 },
645         { 0x01b1, 0x0000 },
646         { 0x01b2, 0xd870 },
647         { 0x01b3, 0x0000 },
648         { 0x01b4, 0x0030 },
649         { 0x01b5, 0x5757 },
650         { 0x01b6, 0x5757 },
651         { 0x01b7, 0x5757 },
652         { 0x01b8, 0x5757 },
653         { 0x01c0, 0x433d },
654         { 0x01c1, 0x0540 },
655         { 0x01c2, 0x0000 },
656         { 0x01c3, 0x0000 },
657         { 0x01c4, 0x0000 },
658         { 0x01c5, 0x0009 },
659         { 0x01c6, 0x0018 },
660         { 0x01c7, 0x002a },
661         { 0x01c8, 0x004c },
662         { 0x01c9, 0x0097 },
663         { 0x01ca, 0x01c3 },
664         { 0x01cb, 0x03e9 },
665         { 0x01cc, 0x1389 },
666         { 0x01cd, 0xc351 },
667         { 0x01ce, 0x0000 },
668         { 0x01cf, 0x0000 },
669         { 0x01d0, 0x0000 },
670         { 0x01d1, 0x0000 },
671         { 0x01d2, 0x0000 },
672         { 0x01d3, 0x003c },
673         { 0x01d4, 0x5757 },
674         { 0x01d5, 0x5757 },
675         { 0x01d6, 0x5757 },
676         { 0x01d7, 0x5757 },
677         { 0x01d8, 0x5757 },
678         { 0x01d9, 0x5757 },
679         { 0x01da, 0x0000 },
680         { 0x01db, 0x0000 },
681         { 0x01dd, 0x0009 },
682         { 0x01de, 0x7f00 },
683         { 0x01df, 0x00c8 },
684         { 0x01e0, 0x0691 },
685         { 0x01e1, 0x0000 },
686         { 0x01e2, 0x0000 },
687         { 0x01e3, 0x0000 },
688         { 0x01e4, 0x0000 },
689         { 0x01e5, 0x0040 },
690         { 0x01e6, 0x0000 },
691         { 0x01e7, 0x0000 },
692         { 0x01e8, 0x0000 },
693         { 0x01ea, 0x0000 },
694         { 0x01eb, 0x0000 },
695         { 0x01ec, 0x0000 },
696         { 0x01ed, 0x0000 },
697         { 0x01ee, 0x0000 },
698         { 0x01ef, 0x0000 },
699         { 0x01f0, 0x0000 },
700         { 0x01f1, 0x0000 },
701         { 0x01f2, 0x0000 },
702         { 0x0200, 0x0000 },
703         { 0x0201, 0x2244 },
704         { 0x0202, 0xaaaa },
705         { 0x0250, 0x8010 },
706         { 0x0251, 0x0000 },
707         { 0x0252, 0x028a },
708         { 0x02fa, 0x0000 },
709         { 0x02fb, 0x8089 },
710         { 0x02fc, 0x0300 },
711         { 0x0300, 0x0000 },
712         { 0x03d0, 0x0000 },
713         { 0x03d1, 0x0000 },
714         { 0x03d2, 0x0000 },
715         { 0x03d3, 0x0000 },
716         { 0x03d4, 0x2000 },
717         { 0x03d5, 0x2000 },
718         { 0x03d6, 0x0000 },
719         { 0x03d7, 0x0000 },
720         { 0x03d8, 0x2000 },
721         { 0x03d9, 0x2000 },
722         { 0x03da, 0x2000 },
723         { 0x03db, 0x2000 },
724         { 0x03dc, 0x0000 },
725         { 0x03dd, 0x0000 },
726         { 0x03de, 0x0000 },
727         { 0x03df, 0x2000 },
728         { 0x03e0, 0x0000 },
729         { 0x03e1, 0x0000 },
730         { 0x03e2, 0x0000 },
731         { 0x03e3, 0x0000 },
732         { 0x03e4, 0x0000 },
733         { 0x03e5, 0x0000 },
734         { 0x03e6, 0x0000 },
735         { 0x03e7, 0x0000 },
736         { 0x03e8, 0x0000 },
737         { 0x03e9, 0x0000 },
738         { 0x03ea, 0x0000 },
739         { 0x03eb, 0x0000 },
740         { 0x03ec, 0x0000 },
741         { 0x03ed, 0x0000 },
742         { 0x03ee, 0x0000 },
743         { 0x03ef, 0x0000 },
744         { 0x03f0, 0x0800 },
745         { 0x03f1, 0x0800 },
746         { 0x03f2, 0x0800 },
747         { 0x03f3, 0x0800 },
748 };
749 
750 static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
751 {
752         switch (reg) {
753         case RT5663_RESET:
754         case RT5663_SIL_DET_CTL:
755         case RT5663_HP_IMP_GAIN_2:
756         case RT5663_AD_DA_MIXER:
757         case RT5663_FRAC_DIV_2:
758         case RT5663_MICBIAS_1:
759         case RT5663_ASRC_11_2:
760         case RT5663_ADC_EQ_1:
761         case RT5663_INT_ST_1:
762         case RT5663_INT_ST_2:
763         case RT5663_GPIO_STA1:
764         case RT5663_SIN_GEN_1:
765         case RT5663_IL_CMD_1:
766         case RT5663_IL_CMD_5:
767         case RT5663_IL_CMD_PWRSAV1:
768         case RT5663_EM_JACK_TYPE_1:
769         case RT5663_EM_JACK_TYPE_2:
770         case RT5663_EM_JACK_TYPE_3:
771         case RT5663_JD_CTRL2:
772         case RT5663_VENDOR_ID:
773         case RT5663_VENDOR_ID_1:
774         case RT5663_VENDOR_ID_2:
775         case RT5663_PLL_INT_REG:
776         case RT5663_SOFT_RAMP:
777         case RT5663_STO_DRE_1:
778         case RT5663_STO_DRE_5:
779         case RT5663_STO_DRE_6:
780         case RT5663_STO_DRE_7:
781         case RT5663_MIC_DECRO_1:
782         case RT5663_MIC_DECRO_4:
783         case RT5663_HP_IMP_SEN_1:
784         case RT5663_HP_IMP_SEN_3:
785         case RT5663_HP_IMP_SEN_4:
786         case RT5663_HP_IMP_SEN_5:
787         case RT5663_HP_CALIB_1_1:
788         case RT5663_HP_CALIB_9:
789         case RT5663_HP_CALIB_ST1:
790         case RT5663_HP_CALIB_ST2:
791         case RT5663_HP_CALIB_ST3:
792         case RT5663_HP_CALIB_ST4:
793         case RT5663_HP_CALIB_ST5:
794         case RT5663_HP_CALIB_ST6:
795         case RT5663_HP_CALIB_ST7:
796         case RT5663_HP_CALIB_ST8:
797         case RT5663_HP_CALIB_ST9:
798         case RT5663_ANA_JD:
799                 return true;
800         default:
801                 return false;
802         }
803 }
804 
805 static bool rt5663_readable_register(struct device *dev, unsigned int reg)
806 {
807         switch (reg) {
808         case RT5663_RESET:
809         case RT5663_HP_OUT_EN:
810         case RT5663_HP_LCH_DRE:
811         case RT5663_HP_RCH_DRE:
812         case RT5663_CALIB_BST:
813         case RT5663_RECMIX:
814         case RT5663_SIL_DET_CTL:
815         case RT5663_PWR_SAV_SILDET:
816         case RT5663_SIDETONE_CTL:
817         case RT5663_STO1_DAC_DIG_VOL:
818         case RT5663_STO1_ADC_DIG_VOL:
819         case RT5663_STO1_BOOST:
820         case RT5663_HP_IMP_GAIN_1:
821         case RT5663_HP_IMP_GAIN_2:
822         case RT5663_STO1_ADC_MIXER:
823         case RT5663_AD_DA_MIXER:
824         case RT5663_STO_DAC_MIXER:
825         case RT5663_DIG_SIDE_MIXER:
826         case RT5663_BYPASS_STO_DAC:
827         case RT5663_CALIB_REC_MIX:
828         case RT5663_PWR_DIG_1:
829         case RT5663_PWR_DIG_2:
830         case RT5663_PWR_ANLG_1:
831         case RT5663_PWR_ANLG_2:
832         case RT5663_PWR_ANLG_3:
833         case RT5663_PWR_MIXER:
834         case RT5663_SIG_CLK_DET:
835         case RT5663_PRE_DIV_GATING_1:
836         case RT5663_PRE_DIV_GATING_2:
837         case RT5663_I2S1_SDP:
838         case RT5663_ADDA_CLK_1:
839         case RT5663_ADDA_RST:
840         case RT5663_FRAC_DIV_1:
841         case RT5663_FRAC_DIV_2:
842         case RT5663_TDM_1:
843         case RT5663_TDM_2:
844         case RT5663_TDM_3:
845         case RT5663_TDM_4:
846         case RT5663_TDM_5:
847         case RT5663_GLB_CLK:
848         case RT5663_PLL_1:
849         case RT5663_PLL_2:
850         case RT5663_ASRC_1:
851         case RT5663_ASRC_2:
852         case RT5663_ASRC_4:
853         case RT5663_DUMMY_REG:
854         case RT5663_ASRC_8:
855         case RT5663_ASRC_9:
856         case RT5663_ASRC_11:
857         case RT5663_DEPOP_1:
858         case RT5663_DEPOP_2:
859         case RT5663_DEPOP_3:
860         case RT5663_HP_CHARGE_PUMP_1:
861         case RT5663_HP_CHARGE_PUMP_2:
862         case RT5663_MICBIAS_1:
863         case RT5663_RC_CLK:
864         case RT5663_ASRC_11_2:
865         case RT5663_DUMMY_REG_2:
866         case RT5663_REC_PATH_GAIN:
867         case RT5663_AUTO_1MRC_CLK:
868         case RT5663_ADC_EQ_1:
869         case RT5663_ADC_EQ_2:
870         case RT5663_IRQ_1:
871         case RT5663_IRQ_2:
872         case RT5663_IRQ_3:
873         case RT5663_IRQ_4:
874         case RT5663_IRQ_5:
875         case RT5663_INT_ST_1:
876         case RT5663_INT_ST_2:
877         case RT5663_GPIO_1:
878         case RT5663_GPIO_2:
879         case RT5663_GPIO_STA1:
880         case RT5663_SIN_GEN_1:
881         case RT5663_SIN_GEN_2:
882         case RT5663_SIN_GEN_3:
883         case RT5663_SOF_VOL_ZC1:
884         case RT5663_IL_CMD_1:
885         case RT5663_IL_CMD_2:
886         case RT5663_IL_CMD_3:
887         case RT5663_IL_CMD_4:
888         case RT5663_IL_CMD_5:
889         case RT5663_IL_CMD_6:
890         case RT5663_IL_CMD_7:
891         case RT5663_IL_CMD_8:
892         case RT5663_IL_CMD_PWRSAV1:
893         case RT5663_IL_CMD_PWRSAV2:
894         case RT5663_EM_JACK_TYPE_1:
895         case RT5663_EM_JACK_TYPE_2:
896         case RT5663_EM_JACK_TYPE_3:
897         case RT5663_EM_JACK_TYPE_4:
898         case RT5663_EM_JACK_TYPE_5:
899         case RT5663_EM_JACK_TYPE_6:
900         case RT5663_STO1_HPF_ADJ1:
901         case RT5663_STO1_HPF_ADJ2:
902         case RT5663_FAST_OFF_MICBIAS:
903         case RT5663_JD_CTRL1:
904         case RT5663_JD_CTRL2:
905         case RT5663_DIG_MISC:
906         case RT5663_VENDOR_ID:
907         case RT5663_VENDOR_ID_1:
908         case RT5663_VENDOR_ID_2:
909         case RT5663_DIG_VOL_ZCD:
910         case RT5663_ANA_BIAS_CUR_1:
911         case RT5663_ANA_BIAS_CUR_2:
912         case RT5663_ANA_BIAS_CUR_3:
913         case RT5663_ANA_BIAS_CUR_4:
914         case RT5663_ANA_BIAS_CUR_5:
915         case RT5663_ANA_BIAS_CUR_6:
916         case RT5663_BIAS_CUR_5:
917         case RT5663_BIAS_CUR_6:
918         case RT5663_BIAS_CUR_7:
919         case RT5663_BIAS_CUR_8:
920         case RT5663_DACREF_LDO:
921         case RT5663_DUMMY_REG_3:
922         case RT5663_BIAS_CUR_9:
923         case RT5663_DUMMY_REG_4:
924         case RT5663_VREFADJ_OP:
925         case RT5663_VREF_RECMIX:
926         case RT5663_CHARGE_PUMP_1:
927         case RT5663_CHARGE_PUMP_1_2:
928         case RT5663_CHARGE_PUMP_1_3:
929         case RT5663_CHARGE_PUMP_2:
930         case RT5663_DIG_IN_PIN1:
931         case RT5663_PAD_DRV_CTL:
932         case RT5663_PLL_INT_REG:
933         case RT5663_CHOP_DAC_L:
934         case RT5663_CHOP_ADC:
935         case RT5663_CALIB_ADC:
936         case RT5663_CHOP_DAC_R:
937         case RT5663_DUMMY_CTL_DACLR:
938         case RT5663_DUMMY_REG_5:
939         case RT5663_SOFT_RAMP:
940         case RT5663_TEST_MODE_1:
941         case RT5663_TEST_MODE_2:
942         case RT5663_TEST_MODE_3:
943         case RT5663_STO_DRE_1:
944         case RT5663_STO_DRE_2:
945         case RT5663_STO_DRE_3:
946         case RT5663_STO_DRE_4:
947         case RT5663_STO_DRE_5:
948         case RT5663_STO_DRE_6:
949         case RT5663_STO_DRE_7:
950         case RT5663_STO_DRE_8:
951         case RT5663_STO_DRE_9:
952         case RT5663_STO_DRE_10:
953         case RT5663_MIC_DECRO_1:
954         case RT5663_MIC_DECRO_2:
955         case RT5663_MIC_DECRO_3:
956         case RT5663_MIC_DECRO_4:
957         case RT5663_MIC_DECRO_5:
958         case RT5663_MIC_DECRO_6:
959         case RT5663_HP_DECRO_1:
960         case RT5663_HP_DECRO_2:
961         case RT5663_HP_DECRO_3:
962         case RT5663_HP_DECRO_4:
963         case RT5663_HP_DECOUP:
964         case RT5663_HP_IMP_SEN_MAP8:
965         case RT5663_HP_IMP_SEN_MAP9:
966         case RT5663_HP_IMP_SEN_MAP10:
967         case RT5663_HP_IMP_SEN_MAP11:
968         case RT5663_HP_IMP_SEN_1:
969         case RT5663_HP_IMP_SEN_2:
970         case RT5663_HP_IMP_SEN_3:
971         case RT5663_HP_IMP_SEN_4:
972         case RT5663_HP_IMP_SEN_5:
973         case RT5663_HP_IMP_SEN_6:
974         case RT5663_HP_IMP_SEN_7:
975         case RT5663_HP_IMP_SEN_8:
976         case RT5663_HP_IMP_SEN_9:
977         case RT5663_HP_IMP_SEN_10:
978         case RT5663_HP_IMP_SEN_11:
979         case RT5663_HP_IMP_SEN_12:
980         case RT5663_HP_IMP_SEN_13:
981         case RT5663_HP_IMP_SEN_14:
982         case RT5663_HP_IMP_SEN_15:
983         case RT5663_HP_IMP_SEN_16:
984         case RT5663_HP_IMP_SEN_17:
985         case RT5663_HP_IMP_SEN_18:
986         case RT5663_HP_IMP_SEN_19:
987         case RT5663_HP_IMPSEN_DIG5:
988         case RT5663_HP_IMPSEN_MAP1:
989         case RT5663_HP_IMPSEN_MAP2:
990         case RT5663_HP_IMPSEN_MAP3:
991         case RT5663_HP_IMPSEN_MAP4:
992         case RT5663_HP_IMPSEN_MAP5:
993         case RT5663_HP_IMPSEN_MAP7:
994         case RT5663_HP_LOGIC_1:
995         case RT5663_HP_LOGIC_2:
996         case RT5663_HP_CALIB_1:
997         case RT5663_HP_CALIB_1_1:
998         case RT5663_HP_CALIB_2:
999         case RT5663_HP_CALIB_3:
1000         case RT5663_HP_CALIB_4:
1001         case RT5663_HP_CALIB_5:
1002         case RT5663_HP_CALIB_5_1:
1003         case RT5663_HP_CALIB_6:
1004         case RT5663_HP_CALIB_7:
1005         case RT5663_HP_CALIB_9:
1006         case RT5663_HP_CALIB_10:
1007         case RT5663_HP_CALIB_11:
1008         case RT5663_HP_CALIB_ST1:
1009         case RT5663_HP_CALIB_ST2:
1010         case RT5663_HP_CALIB_ST3:
1011         case RT5663_HP_CALIB_ST4:
1012         case RT5663_HP_CALIB_ST5:
1013         case RT5663_HP_CALIB_ST6:
1014         case RT5663_HP_CALIB_ST7:
1015         case RT5663_HP_CALIB_ST8:
1016         case RT5663_HP_CALIB_ST9:
1017         case RT5663_HP_AMP_DET:
1018         case RT5663_DUMMY_REG_6:
1019         case RT5663_HP_BIAS:
1020         case RT5663_CBJ_1:
1021         case RT5663_CBJ_2:
1022         case RT5663_CBJ_3:
1023         case RT5663_DUMMY_1:
1024         case RT5663_DUMMY_2:
1025         case RT5663_DUMMY_3:
1026         case RT5663_ANA_JD:
1027         case RT5663_ADC_LCH_LPF1_A1:
1028         case RT5663_ADC_RCH_LPF1_A1:
1029         case RT5663_ADC_LCH_LPF1_H0:
1030         case RT5663_ADC_RCH_LPF1_H0:
1031         case RT5663_ADC_LCH_BPF1_A1:
1032         case RT5663_ADC_RCH_BPF1_A1:
1033         case RT5663_ADC_LCH_BPF1_A2:
1034         case RT5663_ADC_RCH_BPF1_A2:
1035         case RT5663_ADC_LCH_BPF1_H0:
1036         case RT5663_ADC_RCH_BPF1_H0:
1037         case RT5663_ADC_LCH_BPF2_A1:
1038         case RT5663_ADC_RCH_BPF2_A1:
1039         case RT5663_ADC_LCH_BPF2_A2:
1040         case RT5663_ADC_RCH_BPF2_A2:
1041         case RT5663_ADC_LCH_BPF2_H0:
1042         case RT5663_ADC_RCH_BPF2_H0:
1043         case RT5663_ADC_LCH_BPF3_A1:
1044         case RT5663_ADC_RCH_BPF3_A1:
1045         case RT5663_ADC_LCH_BPF3_A2:
1046         case RT5663_ADC_RCH_BPF3_A2:
1047         case RT5663_ADC_LCH_BPF3_H0:
1048         case RT5663_ADC_RCH_BPF3_H0:
1049         case RT5663_ADC_LCH_BPF4_A1:
1050         case RT5663_ADC_RCH_BPF4_A1:
1051         case RT5663_ADC_LCH_BPF4_A2:
1052         case RT5663_ADC_RCH_BPF4_A2:
1053         case RT5663_ADC_LCH_BPF4_H0:
1054         case RT5663_ADC_RCH_BPF4_H0:
1055         case RT5663_ADC_LCH_HPF1_A1:
1056         case RT5663_ADC_RCH_HPF1_A1:
1057         case RT5663_ADC_LCH_HPF1_H0:
1058         case RT5663_ADC_RCH_HPF1_H0:
1059         case RT5663_ADC_EQ_PRE_VOL_L:
1060         case RT5663_ADC_EQ_PRE_VOL_R:
1061         case RT5663_ADC_EQ_POST_VOL_L:
1062         case RT5663_ADC_EQ_POST_VOL_R:
1063                 return true;
1064         default:
1065                 return false;
1066         }
1067 }
1068 
1069 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1070 {
1071         switch (reg) {
1072         case RT5663_RESET:
1073         case RT5663_CBJ_TYPE_2:
1074         case RT5663_PDM_OUT_CTL:
1075         case RT5663_PDM_I2C_DATA_CTL1:
1076         case RT5663_PDM_I2C_DATA_CTL4:
1077         case RT5663_ALC_BK_GAIN:
1078         case RT5663_PLL_2:
1079         case RT5663_MICBIAS_1:
1080         case RT5663_ADC_EQ_1:
1081         case RT5663_INT_ST_1:
1082         case RT5663_GPIO_STA2:
1083         case RT5663_IL_CMD_1:
1084         case RT5663_IL_CMD_5:
1085         case RT5663_A_JD_CTRL:
1086         case RT5663_JD_CTRL2:
1087         case RT5663_VENDOR_ID:
1088         case RT5663_VENDOR_ID_1:
1089         case RT5663_VENDOR_ID_2:
1090         case RT5663_STO_DRE_1:
1091         case RT5663_STO_DRE_5:
1092         case RT5663_STO_DRE_6:
1093         case RT5663_STO_DRE_7:
1094         case RT5663_MONO_DYNA_6:
1095         case RT5663_STO1_SIL_DET:
1096         case RT5663_MONOL_SIL_DET:
1097         case RT5663_MONOR_SIL_DET:
1098         case RT5663_STO2_DAC_SIL:
1099         case RT5663_MONO_AMP_CAL_ST1:
1100         case RT5663_MONO_AMP_CAL_ST2:
1101         case RT5663_MONO_AMP_CAL_ST3:
1102         case RT5663_MONO_AMP_CAL_ST4:
1103         case RT5663_HP_IMP_SEN_2:
1104         case RT5663_HP_IMP_SEN_3:
1105         case RT5663_HP_IMP_SEN_4:
1106         case RT5663_HP_IMP_SEN_10:
1107         case RT5663_HP_CALIB_1:
1108         case RT5663_HP_CALIB_10:
1109         case RT5663_HP_CALIB_ST1:
1110         case RT5663_HP_CALIB_ST4:
1111         case RT5663_HP_CALIB_ST5:
1112         case RT5663_HP_CALIB_ST6:
1113         case RT5663_HP_CALIB_ST7:
1114         case RT5663_HP_CALIB_ST8:
1115         case RT5663_HP_CALIB_ST9:
1116         case RT5663_HP_CALIB_ST10:
1117         case RT5663_HP_CALIB_ST11:
1118                 return true;
1119         default:
1120                 return false;
1121         }
1122 }
1123 
1124 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1125 {
1126         switch (reg) {
1127         case RT5663_LOUT_CTRL:
1128         case RT5663_HP_AMP_2:
1129         case RT5663_MONO_OUT:
1130         case RT5663_MONO_GAIN:
1131         case RT5663_AEC_BST:
1132         case RT5663_IN1_IN2:
1133         case RT5663_IN3_IN4:
1134         case RT5663_INL1_INR1:
1135         case RT5663_CBJ_TYPE_2:
1136         case RT5663_CBJ_TYPE_3:
1137         case RT5663_CBJ_TYPE_4:
1138         case RT5663_CBJ_TYPE_5:
1139         case RT5663_CBJ_TYPE_8:
1140         case RT5663_DAC3_DIG_VOL:
1141         case RT5663_DAC3_CTRL:
1142         case RT5663_MONO_ADC_DIG_VOL:
1143         case RT5663_STO2_ADC_DIG_VOL:
1144         case RT5663_MONO_ADC_BST_GAIN:
1145         case RT5663_STO2_ADC_BST_GAIN:
1146         case RT5663_SIDETONE_CTRL:
1147         case RT5663_MONO1_ADC_MIXER:
1148         case RT5663_STO2_ADC_MIXER:
1149         case RT5663_MONO_DAC_MIXER:
1150         case RT5663_DAC2_SRC_CTRL:
1151         case RT5663_IF_3_4_DATA_CTL:
1152         case RT5663_IF_5_DATA_CTL:
1153         case RT5663_PDM_OUT_CTL:
1154         case RT5663_PDM_I2C_DATA_CTL1:
1155         case RT5663_PDM_I2C_DATA_CTL2:
1156         case RT5663_PDM_I2C_DATA_CTL3:
1157         case RT5663_PDM_I2C_DATA_CTL4:
1158         case RT5663_RECMIX1_NEW:
1159         case RT5663_RECMIX1L_0:
1160         case RT5663_RECMIX1L:
1161         case RT5663_RECMIX1R_0:
1162         case RT5663_RECMIX1R:
1163         case RT5663_RECMIX2_NEW:
1164         case RT5663_RECMIX2_L_2:
1165         case RT5663_RECMIX2_R:
1166         case RT5663_RECMIX2_R_2:
1167         case RT5663_CALIB_REC_LR:
1168         case RT5663_ALC_BK_GAIN:
1169         case RT5663_MONOMIX_GAIN:
1170         case RT5663_MONOMIX_IN_GAIN:
1171         case RT5663_OUT_MIXL_GAIN:
1172         case RT5663_OUT_LMIX_IN_GAIN:
1173         case RT5663_OUT_RMIX_IN_GAIN:
1174         case RT5663_OUT_RMIX_IN_GAIN1:
1175         case RT5663_LOUT_MIXER_CTRL:
1176         case RT5663_PWR_VOL:
1177         case RT5663_ADCDAC_RST:
1178         case RT5663_I2S34_SDP:
1179         case RT5663_I2S5_SDP:
1180         case RT5663_TDM_6:
1181         case RT5663_TDM_7:
1182         case RT5663_TDM_8:
1183         case RT5663_TDM_9:
1184         case RT5663_ASRC_3:
1185         case RT5663_ASRC_6:
1186         case RT5663_ASRC_7:
1187         case RT5663_PLL_TRK_13:
1188         case RT5663_I2S_M_CLK_CTL:
1189         case RT5663_FDIV_I2S34_M_CLK:
1190         case RT5663_FDIV_I2S34_M_CLK2:
1191         case RT5663_FDIV_I2S5_M_CLK:
1192         case RT5663_FDIV_I2S5_M_CLK2:
1193         case RT5663_V2_IRQ_4:
1194         case RT5663_GPIO_3:
1195         case RT5663_GPIO_4:
1196         case RT5663_GPIO_STA2:
1197         case RT5663_HP_AMP_DET1:
1198         case RT5663_HP_AMP_DET2:
1199         case RT5663_HP_AMP_DET3:
1200         case RT5663_MID_BD_HP_AMP:
1201         case RT5663_LOW_BD_HP_AMP:
1202         case RT5663_SOF_VOL_ZC2:
1203         case RT5663_ADC_STO2_ADJ1:
1204         case RT5663_ADC_STO2_ADJ2:
1205         case RT5663_A_JD_CTRL:
1206         case RT5663_JD1_TRES_CTRL:
1207         case RT5663_JD2_TRES_CTRL:
1208         case RT5663_V2_JD_CTRL2:
1209         case RT5663_DUM_REG_2:
1210         case RT5663_DUM_REG_3:
1211         case RT5663_VENDOR_ID:
1212         case RT5663_VENDOR_ID_1:
1213         case RT5663_VENDOR_ID_2:
1214         case RT5663_DACADC_DIG_VOL2:
1215         case RT5663_DIG_IN_PIN2:
1216         case RT5663_PAD_DRV_CTL1:
1217         case RT5663_SOF_RAM_DEPOP:
1218         case RT5663_VOL_TEST:
1219         case RT5663_TEST_MODE_4:
1220         case RT5663_TEST_MODE_5:
1221         case RT5663_STO_DRE_9:
1222         case RT5663_MONO_DYNA_1:
1223         case RT5663_MONO_DYNA_2:
1224         case RT5663_MONO_DYNA_3:
1225         case RT5663_MONO_DYNA_4:
1226         case RT5663_MONO_DYNA_5:
1227         case RT5663_MONO_DYNA_6:
1228         case RT5663_STO1_SIL_DET:
1229         case RT5663_MONOL_SIL_DET:
1230         case RT5663_MONOR_SIL_DET:
1231         case RT5663_STO2_DAC_SIL:
1232         case RT5663_PWR_SAV_CTL1:
1233         case RT5663_PWR_SAV_CTL2:
1234         case RT5663_PWR_SAV_CTL3:
1235         case RT5663_PWR_SAV_CTL4:
1236         case RT5663_PWR_SAV_CTL5:
1237         case RT5663_PWR_SAV_CTL6:
1238         case RT5663_MONO_AMP_CAL1:
1239         case RT5663_MONO_AMP_CAL2:
1240         case RT5663_MONO_AMP_CAL3:
1241         case RT5663_MONO_AMP_CAL4:
1242         case RT5663_MONO_AMP_CAL5:
1243         case RT5663_MONO_AMP_CAL6:
1244         case RT5663_MONO_AMP_CAL7:
1245         case RT5663_MONO_AMP_CAL_ST1:
1246         case RT5663_MONO_AMP_CAL_ST2:
1247         case RT5663_MONO_AMP_CAL_ST3:
1248         case RT5663_MONO_AMP_CAL_ST4:
1249         case RT5663_MONO_AMP_CAL_ST5:
1250         case RT5663_V2_HP_IMP_SEN_13:
1251         case RT5663_V2_HP_IMP_SEN_14:
1252         case RT5663_V2_HP_IMP_SEN_6:
1253         case RT5663_V2_HP_IMP_SEN_7:
1254         case RT5663_V2_HP_IMP_SEN_8:
1255         case RT5663_V2_HP_IMP_SEN_9:
1256         case RT5663_V2_HP_IMP_SEN_10:
1257         case RT5663_HP_LOGIC_3:
1258         case RT5663_HP_CALIB_ST10:
1259         case RT5663_HP_CALIB_ST11:
1260         case RT5663_PRO_REG_TBL_4:
1261         case RT5663_PRO_REG_TBL_5:
1262         case RT5663_PRO_REG_TBL_6:
1263         case RT5663_PRO_REG_TBL_7:
1264         case RT5663_PRO_REG_TBL_8:
1265         case RT5663_PRO_REG_TBL_9:
1266         case RT5663_SAR_ADC_INL_1:
1267         case RT5663_SAR_ADC_INL_2:
1268         case RT5663_SAR_ADC_INL_3:
1269         case RT5663_SAR_ADC_INL_4:
1270         case RT5663_SAR_ADC_INL_5:
1271         case RT5663_SAR_ADC_INL_6:
1272         case RT5663_SAR_ADC_INL_7:
1273         case RT5663_SAR_ADC_INL_8:
1274         case RT5663_SAR_ADC_INL_9:
1275         case RT5663_SAR_ADC_INL_10:
1276         case RT5663_SAR_ADC_INL_11:
1277         case RT5663_SAR_ADC_INL_12:
1278         case RT5663_DRC_CTRL_1:
1279         case RT5663_DRC1_CTRL_2:
1280         case RT5663_DRC1_CTRL_3:
1281         case RT5663_DRC1_CTRL_4:
1282         case RT5663_DRC1_CTRL_5:
1283         case RT5663_DRC1_CTRL_6:
1284         case RT5663_DRC1_HD_CTRL_1:
1285         case RT5663_DRC1_HD_CTRL_2:
1286         case RT5663_DRC1_PRI_REG_1:
1287         case RT5663_DRC1_PRI_REG_2:
1288         case RT5663_DRC1_PRI_REG_3:
1289         case RT5663_DRC1_PRI_REG_4:
1290         case RT5663_DRC1_PRI_REG_5:
1291         case RT5663_DRC1_PRI_REG_6:
1292         case RT5663_DRC1_PRI_REG_7:
1293         case RT5663_DRC1_PRI_REG_8:
1294         case RT5663_ALC_PGA_CTL_1:
1295         case RT5663_ALC_PGA_CTL_2:
1296         case RT5663_ALC_PGA_CTL_3:
1297         case RT5663_ALC_PGA_CTL_4:
1298         case RT5663_ALC_PGA_CTL_5:
1299         case RT5663_ALC_PGA_CTL_6:
1300         case RT5663_ALC_PGA_CTL_7:
1301         case RT5663_ALC_PGA_CTL_8:
1302         case RT5663_ALC_PGA_REG_1:
1303         case RT5663_ALC_PGA_REG_2:
1304         case RT5663_ALC_PGA_REG_3:
1305         case RT5663_ADC_EQ_RECOV_1:
1306         case RT5663_ADC_EQ_RECOV_2:
1307         case RT5663_ADC_EQ_RECOV_3:
1308         case RT5663_ADC_EQ_RECOV_4:
1309         case RT5663_ADC_EQ_RECOV_5:
1310         case RT5663_ADC_EQ_RECOV_6:
1311         case RT5663_ADC_EQ_RECOV_7:
1312         case RT5663_ADC_EQ_RECOV_8:
1313         case RT5663_ADC_EQ_RECOV_9:
1314         case RT5663_ADC_EQ_RECOV_10:
1315         case RT5663_ADC_EQ_RECOV_11:
1316         case RT5663_ADC_EQ_RECOV_12:
1317         case RT5663_ADC_EQ_RECOV_13:
1318         case RT5663_VID_HIDDEN:
1319         case RT5663_VID_CUSTOMER:
1320         case RT5663_SCAN_MODE:
1321         case RT5663_I2C_BYPA:
1322                 return true;
1323         case RT5663_TDM_1:
1324         case RT5663_DEPOP_3:
1325         case RT5663_ASRC_11_2:
1326         case RT5663_INT_ST_2:
1327         case RT5663_GPIO_STA1:
1328         case RT5663_SIN_GEN_1:
1329         case RT5663_SIN_GEN_2:
1330         case RT5663_SIN_GEN_3:
1331         case RT5663_IL_CMD_PWRSAV1:
1332         case RT5663_IL_CMD_PWRSAV2:
1333         case RT5663_EM_JACK_TYPE_1:
1334         case RT5663_EM_JACK_TYPE_2:
1335         case RT5663_EM_JACK_TYPE_3:
1336         case RT5663_EM_JACK_TYPE_4:
1337         case RT5663_FAST_OFF_MICBIAS:
1338         case RT5663_ANA_BIAS_CUR_1:
1339         case RT5663_ANA_BIAS_CUR_2:
1340         case RT5663_BIAS_CUR_9:
1341         case RT5663_DUMMY_REG_4:
1342         case RT5663_VREF_RECMIX:
1343         case RT5663_CHARGE_PUMP_1_2:
1344         case RT5663_CHARGE_PUMP_1_3:
1345         case RT5663_CHARGE_PUMP_2:
1346         case RT5663_CHOP_DAC_R:
1347         case RT5663_DUMMY_CTL_DACLR:
1348         case RT5663_DUMMY_REG_5:
1349         case RT5663_SOFT_RAMP:
1350         case RT5663_TEST_MODE_1:
1351         case RT5663_STO_DRE_10:
1352         case RT5663_MIC_DECRO_1:
1353         case RT5663_MIC_DECRO_2:
1354         case RT5663_MIC_DECRO_3:
1355         case RT5663_MIC_DECRO_4:
1356         case RT5663_MIC_DECRO_5:
1357         case RT5663_MIC_DECRO_6:
1358         case RT5663_HP_DECRO_1:
1359         case RT5663_HP_DECRO_2:
1360         case RT5663_HP_DECRO_3:
1361         case RT5663_HP_DECRO_4:
1362         case RT5663_HP_DECOUP:
1363         case RT5663_HP_IMPSEN_MAP4:
1364         case RT5663_HP_IMPSEN_MAP5:
1365         case RT5663_HP_IMPSEN_MAP7:
1366         case RT5663_HP_CALIB_1:
1367         case RT5663_CBJ_1:
1368         case RT5663_CBJ_2:
1369         case RT5663_CBJ_3:
1370                 return false;
1371         default:
1372                 return rt5663_readable_register(dev, reg);
1373         }
1374 }
1375 
1376 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1377 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1378 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1379 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1380 
1381 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1382 static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1383         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1384         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1385         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1386         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1387         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1388         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1389         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1390 );
1391 
1392 /* Interface data select */
1393 static const char * const rt5663_if1_adc_data_select[] = {
1394         "L/R", "R/L", "L/L", "R/R"
1395 };
1396 
1397 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1398         RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1399 
1400 static void rt5663_enable_push_button_irq(struct snd_soc_component *component,
1401         bool enable)
1402 {
1403         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1404 
1405         if (enable) {
1406                 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1407                         RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1408                 /* reset in-line command */
1409                 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1410                         RT5663_RESET_4BTN_INL_MASK,
1411                         RT5663_RESET_4BTN_INL_RESET);
1412                 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1413                         RT5663_RESET_4BTN_INL_MASK,
1414                         RT5663_RESET_4BTN_INL_NOR);
1415                 switch (rt5663->codec_ver) {
1416                 case CODEC_VER_1:
1417                         snd_soc_component_update_bits(component, RT5663_IRQ_3,
1418                                 RT5663_V2_EN_IRQ_INLINE_MASK,
1419                                 RT5663_V2_EN_IRQ_INLINE_NOR);
1420                         break;
1421                 case CODEC_VER_0:
1422                         snd_soc_component_update_bits(component, RT5663_IRQ_2,
1423                                 RT5663_EN_IRQ_INLINE_MASK,
1424                                 RT5663_EN_IRQ_INLINE_NOR);
1425                         break;
1426                 default:
1427                         dev_err(component->dev, "Unknown CODEC Version\n");
1428                 }
1429         } else {
1430                 switch (rt5663->codec_ver) {
1431                 case CODEC_VER_1:
1432                         snd_soc_component_update_bits(component, RT5663_IRQ_3,
1433                                 RT5663_V2_EN_IRQ_INLINE_MASK,
1434                                 RT5663_V2_EN_IRQ_INLINE_BYP);
1435                         break;
1436                 case CODEC_VER_0:
1437                         snd_soc_component_update_bits(component, RT5663_IRQ_2,
1438                                 RT5663_EN_IRQ_INLINE_MASK,
1439                                 RT5663_EN_IRQ_INLINE_BYP);
1440                         break;
1441                 default:
1442                         dev_err(component->dev, "Unknown CODEC Version\n");
1443                 }
1444                 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1445                         RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1446                 /* reset in-line command */
1447                 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1448                         RT5663_RESET_4BTN_INL_MASK,
1449                         RT5663_RESET_4BTN_INL_RESET);
1450                 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1451                         RT5663_RESET_4BTN_INL_MASK,
1452                         RT5663_RESET_4BTN_INL_NOR);
1453         }
1454 }
1455 
1456 /**
1457  * rt5663_v2_jack_detect - Detect headset.
1458  * @component: SoC audio component device.
1459  * @jack_insert: Jack insert or not.
1460  *
1461  * Detect whether is headset or not when jack inserted.
1462  *
1463  * Returns detect status.
1464  */
1465 
1466 static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert)
1467 {
1468         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1469         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1470         int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1471 
1472         dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1473         if (jack_insert) {
1474                 snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040);
1475                 snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484);
1476 
1477                 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1478                 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1479                 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1480                 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1481                 snd_soc_dapm_sync(dapm);
1482                 snd_soc_component_update_bits(component, RT5663_RC_CLK,
1483                         RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1484                 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8);
1485 
1486                 while (i < 5) {
1487                         msleep(sleep_time[i]);
1488                         val = snd_soc_component_read32(component, RT5663_CBJ_TYPE_2) & 0x0003;
1489                         if (val == 0x1 || val == 0x2 || val == 0x3)
1490                                 break;
1491                         dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n",
1492                                 __func__, val, sleep_time[i]);
1493                         i++;
1494                 }
1495                 dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1496                 switch (val) {
1497                 case 1:
1498                 case 2:
1499                         rt5663->jack_type = SND_JACK_HEADSET;
1500                         rt5663_enable_push_button_irq(component, true);
1501                         break;
1502                 default:
1503                         snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1504                         snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1505                         snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1506                         snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1507                         snd_soc_dapm_sync(dapm);
1508                         rt5663->jack_type = SND_JACK_HEADPHONE;
1509                         break;
1510                 }
1511         } else {
1512                 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0);
1513 
1514                 if (rt5663->jack_type == SND_JACK_HEADSET) {
1515                         rt5663_enable_push_button_irq(component, false);
1516                         snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1517                         snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1518                         snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1519                         snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1520                         snd_soc_dapm_sync(dapm);
1521                 }
1522                 rt5663->jack_type = 0;
1523         }
1524 
1525         dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1526         return rt5663->jack_type;
1527 }
1528 
1529 /**
1530  * rt5663_jack_detect - Detect headset.
1531  * @component: SoC audio component device.
1532  * @jack_insert: Jack insert or not.
1533  *
1534  * Detect whether is headset or not when jack inserted.
1535  *
1536  * Returns detect status.
1537  */
1538 static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert)
1539 {
1540         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1541         int val, i = 0;
1542 
1543         dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1544 
1545         if (jack_insert) {
1546                 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
1547                         RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1548                 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1549                         RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1550                         RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1551                         RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1552                 snd_soc_component_update_bits(component, RT5663_DUMMY_1,
1553                         RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1554                         RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1555                         RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1556                 snd_soc_component_update_bits(component, RT5663_CBJ_1,
1557                         RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1558                         RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1559                 snd_soc_component_update_bits(component, RT5663_IL_CMD_2,
1560                         RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1561                 /* BST1 power on for JD */
1562                 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1563                         RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1564                 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1565                         RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1566                         RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1567                         RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1568                 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1569                         RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1570                         RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1571                         RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1572                 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1573                         RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1574                         RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1575                         RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1576                 msleep(20);
1577                 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1578                         RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1579                         RT5663_PWR_FV1 | RT5663_PWR_FV2);
1580                 snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK,
1581                         RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1582                 snd_soc_component_update_bits(component, RT5663_IRQ_1,
1583                         RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1584                 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1585                         RT5663_EM_JD_MASK, RT5663_EM_JD_RST);
1586                 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1587                         RT5663_EM_JD_MASK, RT5663_EM_JD_NOR);
1588 
1589                 while (true) {
1590                         regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1591                         if (!(val & 0x80))
1592                                 usleep_range(10000, 10005);
1593                         else
1594                                 break;
1595 
1596                         if (i > 200)
1597                                 break;
1598                         i++;
1599                 }
1600 
1601                 val = snd_soc_component_read32(component, RT5663_EM_JACK_TYPE_2) & 0x0003;
1602                 dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1603 
1604                 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1605                         RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1606                         RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1607 
1608                 switch (val) {
1609                 case 1:
1610                 case 2:
1611                         rt5663->jack_type = SND_JACK_HEADSET;
1612                         rt5663_enable_push_button_irq(component, true);
1613 
1614                         if (rt5663->pdata.impedance_sensing_num)
1615                                 break;
1616 
1617                         if (rt5663->pdata.dc_offset_l_manual_mic) {
1618                                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1619                                         rt5663->pdata.dc_offset_l_manual_mic >>
1620                                         16);
1621                                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1622                                         rt5663->pdata.dc_offset_l_manual_mic &
1623                                         0xffff);
1624                         }
1625 
1626                         if (rt5663->pdata.dc_offset_r_manual_mic) {
1627                                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1628                                         rt5663->pdata.dc_offset_r_manual_mic >>
1629                                         16);
1630                                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1631                                         rt5663->pdata.dc_offset_r_manual_mic &
1632                                         0xffff);
1633                         }
1634                         break;
1635                 default:
1636                         rt5663->jack_type = SND_JACK_HEADPHONE;
1637                         snd_soc_component_update_bits(component,
1638                                 RT5663_PWR_ANLG_1,
1639                                 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1640                                 RT5663_PWR_VREF2_MASK, 0);
1641                         if (rt5663->pdata.impedance_sensing_num)
1642                                 break;
1643 
1644                         if (rt5663->pdata.dc_offset_l_manual) {
1645                                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1646                                         rt5663->pdata.dc_offset_l_manual >> 16);
1647                                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1648                                         rt5663->pdata.dc_offset_l_manual &
1649                                         0xffff);
1650                         }
1651 
1652                         if (rt5663->pdata.dc_offset_r_manual) {
1653                                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1654                                         rt5663->pdata.dc_offset_r_manual >> 16);
1655                                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1656                                         rt5663->pdata.dc_offset_r_manual &
1657                                         0xffff);
1658                         }
1659                         break;
1660                 }
1661         } else {
1662                 if (rt5663->jack_type == SND_JACK_HEADSET)
1663                         rt5663_enable_push_button_irq(component, false);
1664                 rt5663->jack_type = 0;
1665                 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1666                         RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1667                         RT5663_PWR_VREF2_MASK, 0);
1668         }
1669 
1670         dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1671         return rt5663->jack_type;
1672 }
1673 
1674 static int rt5663_impedance_sensing(struct snd_soc_component *component)
1675 {
1676         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1677         unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
1678 
1679         for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1680                 if (rt5663->imp_table[i].vol == 7)
1681                         break;
1682         }
1683 
1684         if (rt5663->jack_type == SND_JACK_HEADSET) {
1685                 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1686                         rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1687                 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1688                         rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1689                 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1690                         rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1691                 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1692                         rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1693         } else {
1694                 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1695                         rt5663->imp_table[i].dc_offset_l_manual >> 16);
1696                 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1697                         rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1698                 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1699                         rt5663->imp_table[i].dc_offset_r_manual >> 16);
1700                 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1701                         rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1702         }
1703 
1704         reg84 = snd_soc_component_read32(component, RT5663_ASRC_2);
1705         reg26 = snd_soc_component_read32(component, RT5663_STO1_ADC_MIXER);
1706         reg2fa = snd_soc_component_read32(component, RT5663_DUMMY_1);
1707         reg91 = snd_soc_component_read32(component, RT5663_HP_CHARGE_PUMP_1);
1708         reg10 = snd_soc_component_read32(component, RT5663_RECMIX);
1709         reg80 = snd_soc_component_read32(component, RT5663_GLB_CLK);
1710 
1711         snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0);
1712         snd_soc_component_write(component, RT5663_ASRC_2, 0);
1713         snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040);
1714         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1715                 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1716                 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1717                 RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1718         usleep_range(10000, 10005);
1719         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1720                 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1721                 RT5663_PWR_FV1 | RT5663_PWR_FV2);
1722         snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
1723                 RT5663_SCLK_SRC_RCCLK);
1724         snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1725                 RT5663_DIG_25M_CLK_EN);
1726         snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
1727         snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
1728         snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
1729         snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232);
1730         snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005);
1731         snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
1732         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030);
1733         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003);
1734         snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1735                 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
1736                 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
1737         snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1738                 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1739                 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1740                 RT5663_PWR_ADC_R1,
1741                 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1742                 RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
1743                 RT5663_PWR_ADC_R1);
1744         msleep(40);
1745         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1746                 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
1747                 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
1748         msleep(30);
1749         snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
1750         snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0);
1751         snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c);
1752         snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
1753         snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
1754         snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088);
1755         snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000);
1756         snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000);
1757         snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320);
1758         snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9);
1759         snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c);
1760         snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733);
1761         snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
1762         snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007);
1763         snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007);
1764         snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4);
1765         snd_soc_component_write(component, RT5663_RECMIX, 0x0005);
1766         snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334);
1767         snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004);
1768         snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200);
1769         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000);
1770         snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200);
1771 
1772         for (i = 0; i < 100; i++) {
1773                 msleep(20);
1774                 if (snd_soc_component_read32(component, RT5663_INT_ST_1) & 0x2)
1775                         break;
1776         }
1777 
1778         value = snd_soc_component_read32(component, RT5663_HP_IMP_SEN_4);
1779 
1780         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0);
1781         snd_soc_component_write(component, RT5663_INT_ST_1, 0);
1782         snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0);
1783         snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1784                 RT5663_DIG_25M_CLK_DIS);
1785         snd_soc_component_write(component, RT5663_GLB_CLK, reg80);
1786         snd_soc_component_write(component, RT5663_RECMIX, reg10);
1787         snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4);
1788         snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa);
1789         snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8);
1790         snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320);
1791         snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400);
1792         snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000);
1793         snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008);
1794         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1795                 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
1796         snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1797                 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1798                 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1799                 RT5663_PWR_ADC_R1, 0);
1800         snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1801                 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
1802         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
1803         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
1804         snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0);
1805         snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91);
1806         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1807                 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
1808         snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26);
1809         snd_soc_component_write(component, RT5663_ASRC_2, reg84);
1810 
1811         for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1812                 if (value >= rt5663->imp_table[i].imp_min &&
1813                         value <= rt5663->imp_table[i].imp_max)
1814                         break;
1815         }
1816 
1817         snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
1818                 rt5663->imp_table[i].vol);
1819         snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
1820                 rt5663->imp_table[i].vol);
1821 
1822         if (rt5663->jack_type == SND_JACK_HEADSET) {
1823                 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1824                         rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1825                 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1826                         rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1827                 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1828                         rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1829                 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1830                         rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1831         } else {
1832                 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1833                         rt5663->imp_table[i].dc_offset_l_manual >> 16);
1834                 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1835                         rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1836                 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1837                         rt5663->imp_table[i].dc_offset_r_manual >> 16);
1838                 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1839                         rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1840         }
1841 
1842         return 0;
1843 }
1844 
1845 static int rt5663_button_detect(struct snd_soc_component *component)
1846 {
1847         int btn_type, val;
1848 
1849         val = snd_soc_component_read32(component, RT5663_IL_CMD_5);
1850         dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val);
1851         btn_type = val & 0xfff0;
1852         snd_soc_component_write(component, RT5663_IL_CMD_5, val);
1853 
1854         return btn_type;
1855 }
1856 
1857 static irqreturn_t rt5663_irq(int irq, void *data)
1858 {
1859         struct rt5663_priv *rt5663 = data;
1860 
1861         dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
1862                 __func__);
1863 
1864         queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1865                 msecs_to_jiffies(250));
1866 
1867         return IRQ_HANDLED;
1868 }
1869 
1870 static int rt5663_set_jack_detect(struct snd_soc_component *component,
1871         struct snd_soc_jack *hs_jack, void *data)
1872 {
1873         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1874 
1875         rt5663->hs_jack = hs_jack;
1876 
1877         rt5663_irq(0, rt5663);
1878 
1879         return 0;
1880 }
1881 
1882 static bool rt5663_check_jd_status(struct snd_soc_component *component)
1883 {
1884         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1885         int val = snd_soc_component_read32(component, RT5663_INT_ST_1);
1886 
1887         dev_dbg(component->dev, "%s val=%x\n", __func__, val);
1888 
1889         /* JD1 */
1890         switch (rt5663->codec_ver) {
1891         case CODEC_VER_1:
1892                 return !(val & 0x2000);
1893         case CODEC_VER_0:
1894                 return !(val & 0x1000);
1895         default:
1896                 dev_err(component->dev, "Unknown CODEC Version\n");
1897         }
1898 
1899         return false;
1900 }
1901 
1902 static void rt5663_jack_detect_work(struct work_struct *work)
1903 {
1904         struct rt5663_priv *rt5663 =
1905                 container_of(work, struct rt5663_priv, jack_detect_work.work);
1906         struct snd_soc_component *component = rt5663->component;
1907         int btn_type, report = 0;
1908 
1909         if (!component)
1910                 return;
1911 
1912         if (rt5663_check_jd_status(component)) {
1913                 /* jack in */
1914                 if (rt5663->jack_type == 0) {
1915                         /* jack was out, report jack type */
1916                         switch (rt5663->codec_ver) {
1917                         case CODEC_VER_1:
1918                                 report = rt5663_v2_jack_detect(
1919                                                 rt5663->component, 1);
1920                                 break;
1921                         case CODEC_VER_0:
1922                                 report = rt5663_jack_detect(rt5663->component, 1);
1923                                 if (rt5663->pdata.impedance_sensing_num)
1924                                         rt5663_impedance_sensing(rt5663->component);
1925                                 break;
1926                         default:
1927                                 dev_err(component->dev, "Unknown CODEC Version\n");
1928                         }
1929 
1930                         /* Delay the jack insert report to avoid pop noise */
1931                         msleep(30);
1932                 } else {
1933                         /* jack is already in, report button event */
1934                         report = SND_JACK_HEADSET;
1935                         btn_type = rt5663_button_detect(rt5663->component);
1936                         /**
1937                          * rt5663 can report three kinds of button behavior,
1938                          * one click, double click and hold. However,
1939                          * currently we will report button pressed/released
1940                          * event. So all the three button behaviors are
1941                          * treated as button pressed.
1942                          */
1943                         switch (btn_type) {
1944                         case 0x8000:
1945                         case 0x4000:
1946                         case 0x2000:
1947                                 report |= SND_JACK_BTN_0;
1948                                 break;
1949                         case 0x1000:
1950                         case 0x0800:
1951                         case 0x0400:
1952                                 report |= SND_JACK_BTN_1;
1953                                 break;
1954                         case 0x0200:
1955                         case 0x0100:
1956                         case 0x0080:
1957                                 report |= SND_JACK_BTN_2;
1958                                 break;
1959                         case 0x0040:
1960                         case 0x0020:
1961                         case 0x0010:
1962                                 report |= SND_JACK_BTN_3;
1963                                 break;
1964                         case 0x0000: /* unpressed */
1965                                 break;
1966                         default:
1967                                 btn_type = 0;
1968                                 dev_err(rt5663->component->dev,
1969                                         "Unexpected button code 0x%04x\n",
1970                                         btn_type);
1971                                 break;
1972                         }
1973                         /* button release or spurious interrput*/
1974                         if (btn_type == 0) {
1975                                 report =  rt5663->jack_type;
1976                                 cancel_delayed_work_sync(
1977                                         &rt5663->jd_unplug_work);
1978                         } else {
1979                                 queue_delayed_work(system_wq,
1980                                         &rt5663->jd_unplug_work,
1981                                         msecs_to_jiffies(500));
1982                         }
1983                 }
1984         } else {
1985                 /* jack out */
1986                 switch (rt5663->codec_ver) {
1987                 case CODEC_VER_1:
1988                         report = rt5663_v2_jack_detect(rt5663->component, 0);
1989                         break;
1990                 case CODEC_VER_0:
1991                         report = rt5663_jack_detect(rt5663->component, 0);
1992                         break;
1993                 default:
1994                         dev_err(component->dev, "Unknown CODEC Version\n");
1995                 }
1996         }
1997         dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report);
1998         snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1999                             SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2000                             SND_JACK_BTN_2 | SND_JACK_BTN_3);
2001 }
2002 
2003 static void rt5663_jd_unplug_work(struct work_struct *work)
2004 {
2005         struct rt5663_priv *rt5663 =
2006                 container_of(work, struct rt5663_priv, jd_unplug_work.work);
2007         struct snd_soc_component *component = rt5663->component;
2008 
2009         if (!component)
2010                 return;
2011 
2012         if (!rt5663_check_jd_status(component)) {
2013                 /* jack out */
2014                 switch (rt5663->codec_ver) {
2015                 case CODEC_VER_1:
2016                         rt5663_v2_jack_detect(rt5663->component, 0);
2017                         break;
2018                 case CODEC_VER_0:
2019                         rt5663_jack_detect(rt5663->component, 0);
2020                         break;
2021                 default:
2022                         dev_err(component->dev, "Unknown CODEC Version\n");
2023                 }
2024 
2025                 snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
2026                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2027                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
2028         } else {
2029                 queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
2030                         msecs_to_jiffies(500));
2031         }
2032 }
2033 
2034 static const struct snd_kcontrol_new rt5663_snd_controls[] = {
2035         /* DAC Digital Volume */
2036         SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
2037                 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
2038                 87, 0, dac_vol_tlv),
2039         /* ADC Digital Volume Control */
2040         SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
2041                 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
2042         SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
2043                 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
2044                 63, 0, adc_vol_tlv),
2045 };
2046 
2047 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
2048         /* Headphone Output Volume */
2049         SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
2050                 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
2051                 rt5663_v2_hp_vol_tlv),
2052         /* Mic Boost Volume */
2053         SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
2054                 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
2055 };
2056 
2057 static const struct snd_kcontrol_new rt5663_specific_controls[] = {
2058         /* Mic Boost Volume*/
2059         SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
2060                 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
2061         /* Data Swap for Slot0/1 in ADCDAT1 */
2062         SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
2063 };
2064 
2065 static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
2066         /* Headphone Output Volume */
2067         SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
2068                 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
2069                 rt5663_hp_vol_tlv),
2070 };
2071 
2072 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
2073         struct snd_soc_dapm_widget *sink)
2074 {
2075         unsigned int val;
2076         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2077 
2078         val = snd_soc_component_read32(component, RT5663_GLB_CLK);
2079         val &= RT5663_SCLK_SRC_MASK;
2080         if (val == RT5663_SCLK_SRC_PLL1)
2081                 return 1;
2082         else
2083                 return 0;
2084 }
2085 
2086 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
2087         struct snd_soc_dapm_widget *sink)
2088 {
2089         unsigned int reg, shift, val;
2090         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2091         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2092 
2093         if (rt5663->codec_ver == CODEC_VER_1) {
2094                 switch (w->shift) {
2095                 case RT5663_ADC_STO1_ASRC_SHIFT:
2096                         reg = RT5663_ASRC_3;
2097                         shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
2098                         break;
2099                 case RT5663_DAC_STO1_ASRC_SHIFT:
2100                         reg = RT5663_ASRC_2;
2101                         shift = RT5663_DA_STO1_TRACK_SHIFT;
2102                         break;
2103                 default:
2104                         return 0;
2105                 }
2106         } else {
2107                 switch (w->shift) {
2108                 case RT5663_ADC_STO1_ASRC_SHIFT:
2109                         reg = RT5663_ASRC_2;
2110                         shift = RT5663_AD_STO1_TRACK_SHIFT;
2111                         break;
2112                 case RT5663_DAC_STO1_ASRC_SHIFT:
2113                         reg = RT5663_ASRC_2;
2114                         shift = RT5663_DA_STO1_TRACK_SHIFT;
2115                         break;
2116                 default:
2117                         return 0;
2118                 }
2119         }
2120 
2121         val = (snd_soc_component_read32(component, reg) >> shift) & 0x7;
2122 
2123         if (val)
2124                 return 1;
2125 
2126         return 0;
2127 }
2128 
2129 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
2130         struct snd_soc_dapm_widget *sink)
2131 {
2132         struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
2133         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2134         int da_asrc_en, ad_asrc_en;
2135 
2136         da_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2137                 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
2138         switch (rt5663->codec_ver) {
2139         case CODEC_VER_1:
2140                 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_3) &
2141                         RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
2142                 break;
2143         case CODEC_VER_0:
2144                 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2145                         RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
2146                 break;
2147         default:
2148                 dev_err(component->dev, "Unknown CODEC Version\n");
2149                 return 1;
2150         }
2151 
2152         if (da_asrc_en || ad_asrc_en)
2153                 if (rt5663->sysclk > rt5663->lrck * 384)
2154                         return 1;
2155 
2156         dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n");
2157 
2158         return 0;
2159 }
2160 
2161 /**
2162  * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
2163  * @component: SoC audio component device.
2164  * @filter_mask: mask of filters.
2165  * @clk_src: clock source
2166  *
2167  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
2168  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
2169  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
2170  * ASRC function will track i2s clock and generate a corresponding system clock
2171  * for codec. This function provides an API to select the clock source for a
2172  * set of filters specified by the mask. And the codec driver will turn on ASRC
2173  * for these filters if ASRC is selected as their clock source.
2174  */
2175 int rt5663_sel_asrc_clk_src(struct snd_soc_component *component,
2176                 unsigned int filter_mask, unsigned int clk_src)
2177 {
2178         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2179         unsigned int asrc2_mask = 0;
2180         unsigned int asrc2_value = 0;
2181         unsigned int asrc3_mask = 0;
2182         unsigned int asrc3_value = 0;
2183 
2184         switch (clk_src) {
2185         case RT5663_CLK_SEL_SYS:
2186         case RT5663_CLK_SEL_I2S1_ASRC:
2187                 break;
2188 
2189         default:
2190                 return -EINVAL;
2191         }
2192 
2193         if (filter_mask & RT5663_DA_STEREO_FILTER) {
2194                 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
2195                 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
2196         }
2197 
2198         if (filter_mask & RT5663_AD_STEREO_FILTER) {
2199                 switch (rt5663->codec_ver) {
2200                 case CODEC_VER_1:
2201                         asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
2202                         asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
2203                         break;
2204                 case CODEC_VER_0:
2205                         asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
2206                         asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
2207                         break;
2208                 default:
2209                         dev_err(component->dev, "Unknown CODEC Version\n");
2210                 }
2211         }
2212 
2213         if (asrc2_mask)
2214                 snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask,
2215                         asrc2_value);
2216 
2217         if (asrc3_mask)
2218                 snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask,
2219                         asrc3_value);
2220 
2221         return 0;
2222 }
2223 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
2224 
2225 /* Analog Mixer */
2226 static const struct snd_kcontrol_new rt5663_recmix1l[] = {
2227         SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
2228                 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
2229         SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
2230                 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
2231 };
2232 
2233 static const struct snd_kcontrol_new rt5663_recmix1r[] = {
2234         SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
2235                 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
2236 };
2237 
2238 /* Digital Mixer */
2239 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
2240         SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2241                         RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
2242         SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2243                         RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
2244 };
2245 
2246 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
2247         SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2248                         RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
2249         SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2250                         RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
2251 };
2252 
2253 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
2254         SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
2255                         RT5663_M_ADCMIX_L_SHIFT, 1, 1),
2256         SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
2257                         RT5663_M_DAC1_L_SHIFT, 1, 1),
2258 };
2259 
2260 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
2261         SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
2262                         RT5663_M_ADCMIX_R_SHIFT, 1, 1),
2263         SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
2264                         RT5663_M_DAC1_R_SHIFT, 1, 1),
2265 };
2266 
2267 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2268         SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
2269                         RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
2270 };
2271 
2272 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
2273         SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
2274                         RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
2275 };
2276 
2277 /* Out Switch */
2278 static const struct snd_kcontrol_new rt5663_hpo_switch =
2279         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2280                 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
2281 
2282 /* Stereo ADC source */
2283 static const char * const rt5663_sto1_adc_src[] = {
2284         "ADC L", "ADC R"
2285 };
2286 
2287 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2288         RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
2289 
2290 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2291         SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
2292 
2293 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2294         RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
2295 
2296 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2297         SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
2298 
2299 /* RT5663: Analog DACL1 input source */
2300 static const char * const rt5663_alg_dacl_src[] = {
2301         "DAC L", "STO DAC MIXL"
2302 };
2303 
2304 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2305         RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2306 
2307 static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2308         SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2309 
2310 /* RT5663: Analog DACR1 input source */
2311 static const char * const rt5663_alg_dacr_src[] = {
2312         "DAC R", "STO DAC MIXR"
2313 };
2314 
2315 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2316         RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2317 
2318 static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2319         SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2320 
2321 static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2322         struct snd_kcontrol *kcontrol, int event)
2323 {
2324         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2325         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2326 
2327         switch (event) {
2328         case SND_SOC_DAPM_POST_PMU:
2329                 if (rt5663->codec_ver == CODEC_VER_1) {
2330                         snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2331                                 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2332                         snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2333                                 RT5663_HP_SIG_SRC1_MASK,
2334                                 RT5663_HP_SIG_SRC1_SILENCE);
2335                 } else {
2336                         snd_soc_component_update_bits(component,
2337                                 RT5663_DACREF_LDO, 0x3e0e, 0x3a0a);
2338                         snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
2339                         snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2340                                 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2341                         snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2342                         snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba);
2343                         snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
2344                         snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766);
2345                         snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
2346                         snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
2347                         snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000,
2348                                 0x8000);
2349                         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000,
2350                                 0x3000);
2351                         snd_soc_component_update_bits(component,
2352                                 RT5663_DIG_VOL_ZCD, 0x00c0, 0x0080);
2353                 }
2354                 break;
2355 
2356         case SND_SOC_DAPM_PRE_PMD:
2357                 if (rt5663->codec_ver == CODEC_VER_1) {
2358                         snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2359                                 RT5663_HP_SIG_SRC1_MASK,
2360                                 RT5663_HP_SIG_SRC1_REG);
2361                 } else {
2362                         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0);
2363                         snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2364                                 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2365                         snd_soc_component_update_bits(component,
2366                                 RT5663_DACREF_LDO, 0x3e0e, 0);
2367                         snd_soc_component_update_bits(component,
2368                                 RT5663_DIG_VOL_ZCD, 0x00c0, 0);
2369                 }
2370                 break;
2371 
2372         default:
2373                 return 0;
2374         }
2375 
2376         return 0;
2377 }
2378 
2379 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2380         struct snd_kcontrol *kcontrol, int event)
2381 {
2382         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2383         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2384 
2385         switch (event) {
2386         case SND_SOC_DAPM_PRE_PMU:
2387                 if (rt5663->codec_ver == CODEC_VER_0) {
2388                         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030,
2389                                 0x0030);
2390                         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003,
2391                                 0x0003);
2392                 }
2393                 break;
2394 
2395         case SND_SOC_DAPM_POST_PMD:
2396                 if (rt5663->codec_ver == CODEC_VER_0) {
2397                         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
2398                         snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
2399                 }
2400                 break;
2401 
2402         default:
2403                 return 0;
2404         }
2405 
2406         return 0;
2407 }
2408 
2409 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2410         struct snd_kcontrol *kcontrol, int event)
2411 {
2412         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2413 
2414         switch (event) {
2415         case SND_SOC_DAPM_POST_PMU:
2416                 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2417                         RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2418                         RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2419                 break;
2420 
2421         case SND_SOC_DAPM_PRE_PMD:
2422                 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2423                         RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2424                 break;
2425 
2426         default:
2427                 return 0;
2428         }
2429 
2430         return 0;
2431 }
2432 
2433 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2434         struct snd_kcontrol *kcontrol, int event)
2435 {
2436         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2437 
2438         switch (event) {
2439         case SND_SOC_DAPM_POST_PMU:
2440                 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
2441                 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
2442                 break;
2443 
2444         case SND_SOC_DAPM_PRE_PMD:
2445                 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000);
2446                 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000);
2447                 break;
2448 
2449         default:
2450                 return 0;
2451         }
2452 
2453         return 0;
2454 }
2455 
2456 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2457         SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2458                 NULL, 0),
2459 
2460         /* micbias */
2461         SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2462                 RT5663_PWR_MB1_SHIFT, 0),
2463         SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2464                 RT5663_PWR_MB2_SHIFT, 0),
2465 
2466         /* Input Lines */
2467         SND_SOC_DAPM_INPUT("IN1P"),
2468         SND_SOC_DAPM_INPUT("IN1N"),
2469 
2470         /* REC Mixer Power */
2471         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2472                 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2473 
2474         /* ADCs */
2475         SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2476         SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2477                 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2478         SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2479                 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2480 
2481         /* ADC Mixer */
2482         SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2483                 0, 0, rt5663_sto1_adc_l_mix,
2484                 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2485 
2486         /* ADC Filter Power */
2487         SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2488                 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2489 
2490         /* Digital Interface */
2491         SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2492                 NULL, 0),
2493         SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2494         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2495         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2496         SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2497         SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2498 
2499         /* Audio Interface */
2500         SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2501         SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2502 
2503         /* DAC mixer before sound effect  */
2504         SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2505                 ARRAY_SIZE(rt5663_adda_l_mix)),
2506         SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2507                 ARRAY_SIZE(rt5663_adda_r_mix)),
2508         SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2509         SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2510 
2511         /* DAC Mixer */
2512         SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2513                 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2514         SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2515                 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2516         SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2517                 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2518 
2519         /* DACs */
2520         SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2521                 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2522         SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2523                 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2524         SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2525         SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2526 
2527         /* Headphone*/
2528         SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2529                 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2530                 SND_SOC_DAPM_POST_PMD),
2531         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2532                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2533 
2534         /* Output Lines */
2535         SND_SOC_DAPM_OUTPUT("HPOL"),
2536         SND_SOC_DAPM_OUTPUT("HPOR"),
2537 };
2538 
2539 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2540         SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2541                 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2542         SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2543                 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2544         SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2545                 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2546 
2547         /* ASRC */
2548         SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2549                 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2550         SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2551                 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2552         SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2553                 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2554 
2555         /* Input Lines */
2556         SND_SOC_DAPM_INPUT("IN2P"),
2557         SND_SOC_DAPM_INPUT("IN2N"),
2558 
2559         /* Boost */
2560         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2561         SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2562                 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2563         SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2564         SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2565                 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2566                 SND_SOC_DAPM_POST_PMU),
2567 
2568         /* REC Mixer */
2569         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2570                 ARRAY_SIZE(rt5663_recmix1l)),
2571         SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2572                 ARRAY_SIZE(rt5663_recmix1r)),
2573         SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2574                 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2575 
2576         /* ADC */
2577         SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2578         SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2579                 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2580 
2581         /* ADC Mux */
2582         SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2583                 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2584         SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2585                 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2586         SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2587                 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2588         SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2589                 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2590 
2591         SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2592                 &rt5663_sto1_adcl_mux),
2593         SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2594                 &rt5663_sto1_adcr_mux),
2595 
2596         /* ADC Mix */
2597         SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2598                 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2599 
2600         /* Analog DAC Clock */
2601         SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2602                 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2603 
2604         /* Headphone out */
2605         SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2606                 &rt5663_hpo_switch),
2607 };
2608 
2609 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2610         /* System Clock Pre Divider Gating */
2611         SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2612                 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2613                 SND_SOC_DAPM_PRE_PMD),
2614 
2615         /* LDO */
2616         SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2617                 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2618 
2619         /* ASRC */
2620         SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2621                 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2622         SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2623                 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2624         SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2625                 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2626 
2627         /* Boost */
2628         SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2629 
2630         /* STO ADC */
2631         SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2632         SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2633 
2634         /* Analog DAC source */
2635         SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2636         SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2637 };
2638 
2639 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2640         /* PLL */
2641         { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2642 
2643         /* ASRC */
2644         { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2645         { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2646         { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2647 
2648         { "ADC L", NULL, "ADC L Power" },
2649         { "ADC L", NULL, "ADC Clock" },
2650 
2651         { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2652 
2653         { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2654         { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2655         { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2656 
2657         { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2658         { "IF ADC", NULL, "IF1 ADC1" },
2659         { "AIFTX", NULL, "IF ADC" },
2660         { "AIFTX", NULL, "I2S" },
2661 
2662         { "AIFRX", NULL, "I2S" },
2663         { "IF DAC", NULL, "AIFRX" },
2664         { "IF1 DAC1 L", NULL, "IF DAC" },
2665         { "IF1 DAC1 R", NULL, "IF DAC" },
2666 
2667         { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2668         { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2669         { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2670         { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2671         { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2672         { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2673         { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2674 
2675         { "DAC L1", NULL, "ADDA MIXL" },
2676         { "DAC R1", NULL, "ADDA MIXR" },
2677 
2678         { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2679         { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2680         { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2681         { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2682         { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2683         { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2684 
2685         { "HP Amp", NULL, "HP Charge Pump" },
2686         { "HP Amp", NULL, "DAC L" },
2687         { "HP Amp", NULL, "DAC R" },
2688 };
2689 
2690 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2691         { "MICBIAS1", NULL, "LDO2" },
2692         { "MICBIAS2", NULL, "LDO2" },
2693 
2694         { "BST1 CBJ", NULL, "IN1P" },
2695         { "BST1 CBJ", NULL, "IN1N" },
2696         { "BST1 CBJ", NULL, "CBJ Power" },
2697 
2698         { "BST2", NULL, "IN2P" },
2699         { "BST2", NULL, "IN2N" },
2700         { "BST2", NULL, "BST2 Power" },
2701 
2702         { "RECMIX1L", "BST2 Switch", "BST2" },
2703         { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2704         { "RECMIX1L", NULL, "RECMIX1L Power" },
2705         { "RECMIX1R", "BST2 Switch", "BST2" },
2706         { "RECMIX1R", NULL, "RECMIX1R Power" },
2707 
2708         { "ADC L", NULL, "RECMIX1L" },
2709         { "ADC R", NULL, "RECMIX1R" },
2710         { "ADC R", NULL, "ADC R Power" },
2711         { "ADC R", NULL, "ADC Clock" },
2712 
2713         { "STO1 ADC L Mux", "ADC L", "ADC L" },
2714         { "STO1 ADC L Mux", "ADC R", "ADC R" },
2715         { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2716 
2717         { "STO1 ADC R Mux", "ADC L", "ADC L" },
2718         { "STO1 ADC R Mux", "ADC R", "ADC R" },
2719         { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2720         { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2721 
2722         { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2723         { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2724         { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2725 
2726         { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2727 
2728         { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2729 
2730         { "DAC L", NULL, "STO1 DAC MIXL" },
2731         { "DAC L", NULL, "LDO DAC" },
2732         { "DAC L", NULL, "DAC Clock" },
2733         { "DAC R", NULL, "STO1 DAC MIXR" },
2734         { "DAC R", NULL, "LDO DAC" },
2735         { "DAC R", NULL, "DAC Clock" },
2736 
2737         { "HPO Playback", "Switch", "HP Amp" },
2738         { "HPOL", NULL, "HPO Playback" },
2739         { "HPOR", NULL, "HPO Playback" },
2740 };
2741 
2742 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2743         { "I2S", NULL, "Pre Div Power" },
2744 
2745         { "BST1", NULL, "IN1P" },
2746         { "BST1", NULL, "IN1N" },
2747         { "BST1", NULL, "RECMIX1L Power" },
2748 
2749         { "ADC L", NULL, "BST1" },
2750 
2751         { "STO1 ADC L1", NULL, "ADC L" },
2752 
2753         { "DAC L Mux", "DAC L",  "DAC L1" },
2754         { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2755         { "DAC R Mux", "DAC R",  "DAC R1"},
2756         { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2757 
2758         { "DAC L", NULL, "DAC L Mux" },
2759         { "DAC R", NULL, "DAC R Mux" },
2760 
2761         { "HPOL", NULL, "HP Amp" },
2762         { "HPOR", NULL, "HP Amp" },
2763 };
2764 
2765 static int rt5663_hw_params(struct snd_pcm_substream *substream,
2766         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2767 {
2768         struct snd_soc_component *component = dai->component;
2769         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2770         unsigned int val_len = 0;
2771         int pre_div;
2772 
2773         rt5663->lrck = params_rate(params);
2774 
2775         dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2776                 rt5663->lrck, rt5663->sysclk);
2777 
2778         pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2779         if (pre_div < 0) {
2780                 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
2781                         rt5663->lrck, dai->id);
2782                 return -EINVAL;
2783         }
2784 
2785         dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2786 
2787         switch (params_width(params)) {
2788         case 8:
2789                 val_len = RT5663_I2S_DL_8;
2790                 break;
2791         case 16:
2792                 val_len = RT5663_I2S_DL_16;
2793                 break;
2794         case 20:
2795                 val_len = RT5663_I2S_DL_20;
2796                 break;
2797         case 24:
2798                 val_len = RT5663_I2S_DL_24;
2799                 break;
2800         default:
2801                 return -EINVAL;
2802         }
2803 
2804         snd_soc_component_update_bits(component, RT5663_I2S1_SDP,
2805                 RT5663_I2S_DL_MASK, val_len);
2806 
2807         snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1,
2808                 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2809 
2810         return 0;
2811 }
2812 
2813 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2814 {
2815         struct snd_soc_component *component = dai->component;
2816         unsigned int reg_val = 0;
2817 
2818         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2819         case SND_SOC_DAIFMT_CBM_CFM:
2820                 break;
2821         case SND_SOC_DAIFMT_CBS_CFS:
2822                 reg_val |= RT5663_I2S_MS_S;
2823                 break;
2824         default:
2825                 return -EINVAL;
2826         }
2827 
2828         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2829         case SND_SOC_DAIFMT_NB_NF:
2830                 break;
2831         case SND_SOC_DAIFMT_IB_NF:
2832                 reg_val |= RT5663_I2S_BP_INV;
2833                 break;
2834         default:
2835                 return -EINVAL;
2836         }
2837 
2838         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2839         case SND_SOC_DAIFMT_I2S:
2840                 break;
2841         case SND_SOC_DAIFMT_LEFT_J:
2842                 reg_val |= RT5663_I2S_DF_LEFT;
2843                 break;
2844         case SND_SOC_DAIFMT_DSP_A:
2845                 reg_val |= RT5663_I2S_DF_PCM_A;
2846                 break;
2847         case SND_SOC_DAIFMT_DSP_B:
2848                 reg_val |= RT5663_I2S_DF_PCM_B;
2849                 break;
2850         default:
2851                 return -EINVAL;
2852         }
2853 
2854         snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2855                 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2856 
2857         return 0;
2858 }
2859 
2860 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2861         unsigned int freq, int dir)
2862 {
2863         struct snd_soc_component *component = dai->component;
2864         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2865         unsigned int reg_val = 0;
2866 
2867         if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2868                 return 0;
2869 
2870         switch (clk_id) {
2871         case RT5663_SCLK_S_MCLK:
2872                 reg_val |= RT5663_SCLK_SRC_MCLK;
2873                 break;
2874         case RT5663_SCLK_S_PLL1:
2875                 reg_val |= RT5663_SCLK_SRC_PLL1;
2876                 break;
2877         case RT5663_SCLK_S_RCCLK:
2878                 reg_val |= RT5663_SCLK_SRC_RCCLK;
2879                 break;
2880         default:
2881                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2882                 return -EINVAL;
2883         }
2884         snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2885                 reg_val);
2886         rt5663->sysclk = freq;
2887         rt5663->sysclk_src = clk_id;
2888 
2889         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2890                 freq, clk_id);
2891 
2892         return 0;
2893 }
2894 
2895 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2896                         unsigned int freq_in, unsigned int freq_out)
2897 {
2898         struct snd_soc_component *component = dai->component;
2899         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2900         struct rl6231_pll_code pll_code;
2901         int ret;
2902         int mask, shift, val;
2903 
2904         if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2905             freq_out == rt5663->pll_out)
2906                 return 0;
2907 
2908         if (!freq_in || !freq_out) {
2909                 dev_dbg(component->dev, "PLL disabled\n");
2910 
2911                 rt5663->pll_in = 0;
2912                 rt5663->pll_out = 0;
2913                 snd_soc_component_update_bits(component, RT5663_GLB_CLK,
2914                         RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2915                 return 0;
2916         }
2917 
2918         switch (rt5663->codec_ver) {
2919         case CODEC_VER_1:
2920                 mask = RT5663_V2_PLL1_SRC_MASK;
2921                 shift = RT5663_V2_PLL1_SRC_SHIFT;
2922                 break;
2923         case CODEC_VER_0:
2924                 mask = RT5663_PLL1_SRC_MASK;
2925                 shift = RT5663_PLL1_SRC_SHIFT;
2926                 break;
2927         default:
2928                 dev_err(component->dev, "Unknown CODEC Version\n");
2929                 return -EINVAL;
2930         }
2931 
2932         switch (source) {
2933         case RT5663_PLL1_S_MCLK:
2934                 val = 0x0;
2935                 break;
2936         case RT5663_PLL1_S_BCLK1:
2937                 val = 0x1;
2938                 break;
2939         default:
2940                 dev_err(component->dev, "Unknown PLL source %d\n", source);
2941                 return -EINVAL;
2942         }
2943         snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift));
2944 
2945         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2946         if (ret < 0) {
2947                 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2948                 return ret;
2949         }
2950 
2951         dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2952                 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2953                 pll_code.k_code);
2954 
2955         snd_soc_component_write(component, RT5663_PLL_1,
2956                 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2957         snd_soc_component_write(component, RT5663_PLL_2,
2958                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2959                 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
2960 
2961         rt5663->pll_in = freq_in;
2962         rt5663->pll_out = freq_out;
2963         rt5663->pll_src = source;
2964 
2965         return 0;
2966 }
2967 
2968 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2969         unsigned int rx_mask, int slots, int slot_width)
2970 {
2971         struct snd_soc_component *component = dai->component;
2972         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2973         unsigned int val = 0, reg;
2974 
2975         if (rx_mask || tx_mask)
2976                 val |= RT5663_TDM_MODE_TDM;
2977 
2978         switch (slots) {
2979         case 4:
2980                 val |= RT5663_TDM_IN_CH_4;
2981                 val |= RT5663_TDM_OUT_CH_4;
2982                 break;
2983         case 6:
2984                 val |= RT5663_TDM_IN_CH_6;
2985                 val |= RT5663_TDM_OUT_CH_6;
2986                 break;
2987         case 8:
2988                 val |= RT5663_TDM_IN_CH_8;
2989                 val |= RT5663_TDM_OUT_CH_8;
2990                 break;
2991         case 2:
2992                 break;
2993         default:
2994                 return -EINVAL;
2995         }
2996 
2997         switch (slot_width) {
2998         case 20:
2999                 val |= RT5663_TDM_IN_LEN_20;
3000                 val |= RT5663_TDM_OUT_LEN_20;
3001                 break;
3002         case 24:
3003                 val |= RT5663_TDM_IN_LEN_24;
3004                 val |= RT5663_TDM_OUT_LEN_24;
3005                 break;
3006         case 32:
3007                 val |= RT5663_TDM_IN_LEN_32;
3008                 val |= RT5663_TDM_OUT_LEN_32;
3009                 break;
3010         case 16:
3011                 break;
3012         default:
3013                 return -EINVAL;
3014         }
3015 
3016         switch (rt5663->codec_ver) {
3017         case CODEC_VER_1:
3018                 reg = RT5663_TDM_2;
3019                 break;
3020         case CODEC_VER_0:
3021                 reg = RT5663_TDM_1;
3022                 break;
3023         default:
3024                 dev_err(component->dev, "Unknown CODEC Version\n");
3025                 return -EINVAL;
3026         }
3027 
3028         snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK |
3029                 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
3030                 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
3031 
3032         return 0;
3033 }
3034 
3035 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3036 {
3037         struct snd_soc_component *component = dai->component;
3038         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3039         unsigned int reg;
3040 
3041         dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio);
3042 
3043         if (rt5663->codec_ver == CODEC_VER_1)
3044                 reg = RT5663_TDM_9;
3045         else
3046                 reg = RT5663_TDM_5;
3047 
3048         switch (ratio) {
3049         case 32:
3050                 snd_soc_component_update_bits(component, reg,
3051                         RT5663_TDM_LENGTN_MASK,
3052                         RT5663_TDM_LENGTN_16);
3053                 break;
3054         case 40:
3055                 snd_soc_component_update_bits(component, reg,
3056                         RT5663_TDM_LENGTN_MASK,
3057                         RT5663_TDM_LENGTN_20);
3058                 break;
3059         case 48:
3060                 snd_soc_component_update_bits(component, reg,
3061                         RT5663_TDM_LENGTN_MASK,
3062                         RT5663_TDM_LENGTN_24);
3063                 break;
3064         case 64:
3065                 snd_soc_component_update_bits(component, reg,
3066                         RT5663_TDM_LENGTN_MASK,
3067                         RT5663_TDM_LENGTN_32);
3068                 break;
3069         default:
3070                 dev_err(component->dev, "Invalid ratio!\n");
3071                 return -EINVAL;
3072         }
3073 
3074         return 0;
3075 }
3076 
3077 static int rt5663_set_bias_level(struct snd_soc_component *component,
3078                         enum snd_soc_bias_level level)
3079 {
3080         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3081 
3082         switch (level) {
3083         case SND_SOC_BIAS_ON:
3084                 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3085                         RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3086                         RT5663_PWR_FV1 | RT5663_PWR_FV2);
3087                 break;
3088 
3089         case SND_SOC_BIAS_PREPARE:
3090                 if (rt5663->codec_ver == CODEC_VER_1) {
3091                         snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3092                                 RT5663_DIG_GATE_CTRL_MASK,
3093                                 RT5663_DIG_GATE_CTRL_EN);
3094                         snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3095                                 RT5663_EN_ANA_CLK_DET_MASK |
3096                                 RT5663_PWR_CLK_DET_MASK,
3097                                 RT5663_EN_ANA_CLK_DET_AUTO |
3098                                 RT5663_PWR_CLK_DET_EN);
3099                 }
3100                 break;
3101 
3102         case SND_SOC_BIAS_STANDBY:
3103                 if (rt5663->codec_ver == CODEC_VER_1)
3104                         snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3105                                 RT5663_DIG_GATE_CTRL_MASK,
3106                                 RT5663_DIG_GATE_CTRL_DIS);
3107                 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3108                         RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3109                         RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
3110                         RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
3111                         RT5663_PWR_VREF2 | RT5663_PWR_MB);
3112                 usleep_range(10000, 10005);
3113                 if (rt5663->codec_ver == CODEC_VER_1) {
3114                         snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3115                                 RT5663_EN_ANA_CLK_DET_MASK |
3116                                 RT5663_PWR_CLK_DET_MASK,
3117                                 RT5663_EN_ANA_CLK_DET_DIS |
3118                                 RT5663_PWR_CLK_DET_DIS);
3119                 }
3120                 break;
3121 
3122         case SND_SOC_BIAS_OFF:
3123                 if (rt5663->jack_type != SND_JACK_HEADSET)
3124                         snd_soc_component_update_bits(component,
3125                                 RT5663_PWR_ANLG_1,
3126                                 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3127                                 RT5663_PWR_FV1 | RT5663_PWR_FV2 |
3128                                 RT5663_PWR_MB_MASK, 0);
3129                 else
3130                         snd_soc_component_update_bits(component,
3131                                 RT5663_PWR_ANLG_1,
3132                                 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3133                                 RT5663_PWR_FV1 | RT5663_PWR_FV2);
3134                 break;
3135 
3136         default:
3137                 break;
3138         }
3139 
3140         return 0;
3141 }
3142 
3143 static int rt5663_probe(struct snd_soc_component *component)
3144 {
3145         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3146         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3147 
3148         rt5663->component = component;
3149 
3150         switch (rt5663->codec_ver) {
3151         case CODEC_VER_1:
3152                 snd_soc_dapm_new_controls(dapm,
3153                         rt5663_v2_specific_dapm_widgets,
3154                         ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
3155                 snd_soc_dapm_add_routes(dapm,
3156                         rt5663_v2_specific_dapm_routes,
3157                         ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
3158                 snd_soc_add_component_controls(component, rt5663_v2_specific_controls,
3159                         ARRAY_SIZE(rt5663_v2_specific_controls));
3160                 break;
3161         case CODEC_VER_0:
3162                 snd_soc_dapm_new_controls(dapm,
3163                         rt5663_specific_dapm_widgets,
3164                         ARRAY_SIZE(rt5663_specific_dapm_widgets));
3165                 snd_soc_dapm_add_routes(dapm,
3166                         rt5663_specific_dapm_routes,
3167                         ARRAY_SIZE(rt5663_specific_dapm_routes));
3168                 snd_soc_add_component_controls(component, rt5663_specific_controls,
3169                         ARRAY_SIZE(rt5663_specific_controls));
3170 
3171                 if (!rt5663->imp_table)
3172                         snd_soc_add_component_controls(component, rt5663_hpvol_controls,
3173                                 ARRAY_SIZE(rt5663_hpvol_controls));
3174                 break;
3175         }
3176 
3177         return 0;
3178 }
3179 
3180 static void rt5663_remove(struct snd_soc_component *component)
3181 {
3182         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3183 
3184         regmap_write(rt5663->regmap, RT5663_RESET, 0);
3185 }
3186 
3187 #ifdef CONFIG_PM
3188 static int rt5663_suspend(struct snd_soc_component *component)
3189 {
3190         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3191 
3192         regcache_cache_only(rt5663->regmap, true);
3193         regcache_mark_dirty(rt5663->regmap);
3194 
3195         return 0;
3196 }
3197 
3198 static int rt5663_resume(struct snd_soc_component *component)
3199 {
3200         struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3201 
3202         regcache_cache_only(rt5663->regmap, false);
3203         regcache_sync(rt5663->regmap);
3204 
3205         rt5663_irq(0, rt5663);
3206 
3207         return 0;
3208 }
3209 #else
3210 #define rt5663_suspend NULL
3211 #define rt5663_resume NULL
3212 #endif
3213 
3214 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3215 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3216                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3217 
3218 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
3219         .hw_params = rt5663_hw_params,
3220         .set_fmt = rt5663_set_dai_fmt,
3221         .set_sysclk = rt5663_set_dai_sysclk,
3222         .set_pll = rt5663_set_dai_pll,
3223         .set_tdm_slot = rt5663_set_tdm_slot,
3224         .set_bclk_ratio = rt5663_set_bclk_ratio,
3225 };
3226 
3227 static struct snd_soc_dai_driver rt5663_dai[] = {
3228         {
3229                 .name = "rt5663-aif",
3230                 .id = RT5663_AIF,
3231                 .playback = {
3232                         .stream_name = "AIF Playback",
3233                         .channels_min = 1,
3234                         .channels_max = 2,
3235                         .rates = RT5663_STEREO_RATES,
3236                         .formats = RT5663_FORMATS,
3237                 },
3238                 .capture = {
3239                         .stream_name = "AIF Capture",
3240                         .channels_min = 1,
3241                         .channels_max = 2,
3242                         .rates = RT5663_STEREO_RATES,
3243                         .formats = RT5663_FORMATS,
3244                 },
3245                 .ops = &rt5663_aif_dai_ops,
3246         },
3247 };
3248 
3249 static const struct snd_soc_component_driver soc_component_dev_rt5663 = {
3250         .probe                  = rt5663_probe,
3251         .remove                 = rt5663_remove,
3252         .suspend                = rt5663_suspend,
3253         .resume                 = rt5663_resume,
3254         .set_bias_level         = rt5663_set_bias_level,
3255         .controls               = rt5663_snd_controls,
3256         .num_controls           = ARRAY_SIZE(rt5663_snd_controls),
3257         .dapm_widgets           = rt5663_dapm_widgets,
3258         .num_dapm_widgets       = ARRAY_SIZE(rt5663_dapm_widgets),
3259         .dapm_routes            = rt5663_dapm_routes,
3260         .num_dapm_routes        = ARRAY_SIZE(rt5663_dapm_routes),
3261         .set_jack               = rt5663_set_jack_detect,
3262         .use_pmdown_time        = 1,
3263         .endianness             = 1,
3264         .non_legacy_dai_naming  = 1,
3265 };
3266 
3267 static const struct regmap_config rt5663_v2_regmap = {
3268         .reg_bits = 16,
3269         .val_bits = 16,
3270         .use_single_read = true,
3271         .use_single_write = true,
3272         .max_register = 0x07fa,
3273         .volatile_reg = rt5663_v2_volatile_register,
3274         .readable_reg = rt5663_v2_readable_register,
3275         .cache_type = REGCACHE_RBTREE,
3276         .reg_defaults = rt5663_v2_reg,
3277         .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
3278 };
3279 
3280 static const struct regmap_config rt5663_regmap = {
3281         .reg_bits = 16,
3282         .val_bits = 16,
3283         .use_single_read = true,
3284         .use_single_write = true,
3285         .max_register = 0x03f3,
3286         .volatile_reg = rt5663_volatile_register,
3287         .readable_reg = rt5663_readable_register,
3288         .cache_type = REGCACHE_RBTREE,
3289         .reg_defaults = rt5663_reg,
3290         .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3291 };
3292 
3293 static const struct regmap_config temp_regmap = {
3294         .name = "nocache",
3295         .reg_bits = 16,
3296         .val_bits = 16,
3297         .use_single_read = true,
3298         .use_single_write = true,
3299         .max_register = 0x03f3,
3300         .cache_type = REGCACHE_NONE,
3301 };
3302 
3303 static const struct i2c_device_id rt5663_i2c_id[] = {
3304         { "rt5663", 0 },
3305         {}
3306 };
3307 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3308 
3309 #if defined(CONFIG_OF)
3310 static const struct of_device_id rt5663_of_match[] = {
3311         { .compatible = "realtek,rt5663", },
3312         {},
3313 };
3314 MODULE_DEVICE_TABLE(of, rt5663_of_match);
3315 #endif
3316 
3317 #ifdef CONFIG_ACPI
3318 static const struct acpi_device_id rt5663_acpi_match[] = {
3319         { "10EC5663", 0},
3320         {},
3321 };
3322 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3323 #endif
3324 
3325 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
3326 {
3327         regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3328         regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3329         regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3330         regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3331         regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3332         regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3333         regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3334         regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3335         regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3336         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
3337         msleep(40);
3338         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3339         regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3340         regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
3341         msleep(500);
3342 }
3343 
3344 static void rt5663_calibrate(struct rt5663_priv *rt5663)
3345 {
3346         int value, count;
3347 
3348         regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3349         msleep(20);
3350         regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3351         regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3352         regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3353         regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3354         regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3355         regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3356         regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3357         regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3358         regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28);
3359         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3360         msleep(30);
3361         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3362         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3363         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
3364         regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3365         regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3366         regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3367         regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3368         regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3369         regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3370         regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3371 
3372         count = 0;
3373         while (true) {
3374                 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3375                 if (!(value & 0x80))
3376                         usleep_range(10000, 10005);
3377                 else
3378                         break;
3379 
3380                 if (++count > 200)
3381                         break;
3382         }
3383 
3384         regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
3385         regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3386         regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
3387         regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3388         regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3389         regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3390         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3391         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3392         regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3393         regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089);
3394         regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3395         msleep(40);
3396         regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
3397         regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3398         regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
3399         regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3400         regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3401         regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3402         regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3403         regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3404         regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
3405         regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3406         regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3407         regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3408         regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3409         regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3410         regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3411         regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3412         regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
3413         regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3414         regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3415         regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3416         regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3417         regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3418         regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3419 
3420         count = 0;
3421         while (true) {
3422                 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3423                 if (value & 0x8000)
3424                         usleep_range(10000, 10005);
3425                 else
3426                         break;
3427 
3428                 if (count > 200)
3429                         return;
3430                 count++;
3431         }
3432 
3433         regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3434         regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3435         regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3436 
3437         count = 0;
3438         while (true) {
3439                 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3440                 if (value & 0x8000)
3441                         usleep_range(10000, 10005);
3442                 else
3443                         break;
3444 
3445                 if (count > 200)
3446                         return;
3447                 count++;
3448         }
3449 
3450         regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3451         usleep_range(10000, 10005);
3452         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3453         usleep_range(10000, 10005);
3454         regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3455         usleep_range(10000, 10005);
3456         regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3457         usleep_range(10000, 10005);
3458         regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3459         usleep_range(10000, 10005);
3460         regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3461         usleep_range(10000, 10005);
3462 }
3463 
3464 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3465 {
3466         int table_size;
3467 
3468         device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3469                 &rt5663->pdata.dc_offset_l_manual);
3470         device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3471                 &rt5663->pdata.dc_offset_r_manual);
3472         device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3473                 &rt5663->pdata.dc_offset_l_manual_mic);
3474         device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3475                 &rt5663->pdata.dc_offset_r_manual_mic);
3476         device_property_read_u32(dev, "realtek,impedance_sensing_num",
3477                 &rt5663->pdata.impedance_sensing_num);
3478 
3479         if (rt5663->pdata.impedance_sensing_num) {
3480                 table_size = sizeof(struct impedance_mapping_table) *
3481                         rt5663->pdata.impedance_sensing_num;
3482                 rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
3483                 device_property_read_u32_array(dev,
3484                         "realtek,impedance_sensing_table",
3485                         (u32 *)rt5663->imp_table, table_size);
3486         }
3487 
3488         return 0;
3489 }
3490 
3491 static int rt5663_i2c_probe(struct i2c_client *i2c,
3492                     const struct i2c_device_id *id)
3493 {
3494         struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
3495         struct rt5663_priv *rt5663;
3496         int ret, i;
3497         unsigned int val;
3498         struct regmap *regmap;
3499 
3500         rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3501                 GFP_KERNEL);
3502 
3503         if (rt5663 == NULL)
3504                 return -ENOMEM;
3505 
3506         i2c_set_clientdata(i2c, rt5663);
3507 
3508         if (pdata)
3509                 rt5663->pdata = *pdata;
3510         else
3511                 rt5663_parse_dp(rt5663, &i2c->dev);
3512 
3513         for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++)
3514                 rt5663->supplies[i].supply = rt5663_supply_names[i];
3515 
3516         ret = devm_regulator_bulk_get(&i2c->dev,
3517                                       ARRAY_SIZE(rt5663->supplies),
3518                                       rt5663->supplies);
3519         if (ret) {
3520                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3521                 return ret;
3522         }
3523 
3524         /* Set load for regulator. */
3525         for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++) {
3526                 ret = regulator_set_load(rt5663->supplies[i].consumer,
3527                                          RT5663_SUPPLY_CURRENT_UA);
3528                 if (ret < 0) {
3529                         dev_err(&i2c->dev,
3530                                 "Failed to set regulator load on %s, ret: %d\n",
3531                                 rt5663->supplies[i].supply, ret);
3532                         return ret;
3533                 }
3534         }
3535 
3536         ret = regulator_bulk_enable(ARRAY_SIZE(rt5663->supplies),
3537                                     rt5663->supplies);
3538 
3539         if (ret) {
3540                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3541                 return ret;
3542         }
3543         msleep(RT5663_POWER_ON_DELAY_MS);
3544 
3545         regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3546         if (IS_ERR(regmap)) {
3547                 ret = PTR_ERR(regmap);
3548                 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3549                         ret);
3550                 goto err_enable;
3551         }
3552 
3553         ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3554         if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
3555                 dev_err(&i2c->dev,
3556                         "Device with ID register %#x is not rt5663, retry one time.\n",
3557                         val);
3558                 msleep(100);
3559                 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3560         }
3561 
3562         switch (val) {
3563         case RT5663_DEVICE_ID_2:
3564                 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3565                 rt5663->codec_ver = CODEC_VER_1;
3566                 break;
3567         case RT5663_DEVICE_ID_1:
3568                 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3569                 rt5663->codec_ver = CODEC_VER_0;
3570                 break;
3571         default:
3572                 dev_err(&i2c->dev,
3573                         "Device with ID register %#x is not rt5663\n",
3574                         val);
3575                 ret = -ENODEV;
3576                 goto err_enable;
3577         }
3578 
3579         if (IS_ERR(rt5663->regmap)) {
3580                 ret = PTR_ERR(rt5663->regmap);
3581                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3582                         ret);
3583                 goto err_enable;
3584         }
3585 
3586         /* reset and calibrate */
3587         regmap_write(rt5663->regmap, RT5663_RESET, 0);
3588         regcache_cache_bypass(rt5663->regmap, true);
3589         switch (rt5663->codec_ver) {
3590         case CODEC_VER_1:
3591                 rt5663_v2_calibrate(rt5663);
3592                 break;
3593         case CODEC_VER_0:
3594                 rt5663_calibrate(rt5663);
3595                 break;
3596         default:
3597                 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3598         }
3599         regcache_cache_bypass(rt5663->regmap, false);
3600         regmap_write(rt5663->regmap, RT5663_RESET, 0);
3601         dev_dbg(&i2c->dev, "calibrate done\n");
3602 
3603         switch (rt5663->codec_ver) {
3604         case CODEC_VER_1:
3605                 break;
3606         case CODEC_VER_0:
3607                 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3608                                             ARRAY_SIZE(rt5663_patch_list));
3609                 if (ret != 0)
3610                         dev_warn(&i2c->dev,
3611                                 "Failed to apply regmap patch: %d\n", ret);
3612                 break;
3613         default:
3614                 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3615         }
3616 
3617         /* GPIO1 as IRQ */
3618         regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3619                 RT5663_GP1_PIN_IRQ);
3620         /* 4btn inline command debounce */
3621         regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3622                 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3623 
3624         switch (rt5663->codec_ver) {
3625         case CODEC_VER_1:
3626                 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3627                 /* JD1 */
3628                 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3629                         RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3630                         RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3631                 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3632                         RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3633                 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3634                         RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3635 
3636                 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3637                         RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3638                 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3639                         RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3640                         RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3641                         RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3642                 /* Set GPIO4 and GPIO8 as input for combo jack */
3643                 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3644                         RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3645                 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3646                         RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3647                 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3648                         RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3649                         RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3650                         break;
3651         case CODEC_VER_0:
3652                 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3653                         RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3654                 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3655                         RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
3656                 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3657                         RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3658                 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3659                         RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
3660                 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3661                 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3662                         RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3663                         RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
3664                 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3665                         RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3666                 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3667                         RT5663_DATA_SWAP_ADCDAT1_MASK,
3668                         RT5663_DATA_SWAP_ADCDAT1_LL);
3669                         break;
3670         default:
3671                 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3672         }
3673 
3674         INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3675         INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
3676 
3677         if (i2c->irq) {
3678                 ret = request_irq(i2c->irq, rt5663_irq,
3679                         IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3680                         | IRQF_ONESHOT, "rt5663", rt5663);
3681                 if (ret) {
3682                         dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3683                                 __func__, ret);
3684                         goto err_enable;
3685                 }
3686         }
3687 
3688         ret = devm_snd_soc_register_component(&i2c->dev,
3689                         &soc_component_dev_rt5663,
3690                         rt5663_dai, ARRAY_SIZE(rt5663_dai));
3691 
3692         if (ret)
3693                 goto err_enable;
3694 
3695         return 0;
3696 
3697 
3698         /*
3699          * Error after enabling regulators should goto err_enable
3700          * to disable regulators.
3701          */
3702 err_enable:
3703         if (i2c->irq)
3704                 free_irq(i2c->irq, rt5663);
3705 
3706         regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3707         return ret;
3708 }
3709 
3710 static int rt5663_i2c_remove(struct i2c_client *i2c)
3711 {
3712         struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3713 
3714         if (i2c->irq)
3715                 free_irq(i2c->irq, rt5663);
3716 
3717         regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3718 
3719         return 0;
3720 }
3721 
3722 static void rt5663_i2c_shutdown(struct i2c_client *client)
3723 {
3724         struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3725 
3726         regmap_write(rt5663->regmap, RT5663_RESET, 0);
3727 }
3728 
3729 static struct i2c_driver rt5663_i2c_driver = {
3730         .driver = {
3731                 .name = "rt5663",
3732                 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3733                 .of_match_table = of_match_ptr(rt5663_of_match),
3734         },
3735         .probe = rt5663_i2c_probe,
3736         .remove = rt5663_i2c_remove,
3737         .shutdown = rt5663_i2c_shutdown,
3738         .id_table = rt5663_i2c_id,
3739 };
3740 module_i2c_driver(rt5663_i2c_driver);
3741 
3742 MODULE_DESCRIPTION("ASoC RT5663 driver");
3743 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3744 MODULE_LICENSE("GPL v2");
3745 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp