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Linux/sound/soc/rockchip/rockchip_spdif.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /* sound/soc/rockchip/rk_spdif.c
  3  *
  4  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
  5  *
  6  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
  7  * Author: Jianqun <jay.xu@rock-chips.com>
  8  * Copyright (c) 2015 Collabora Ltd.
  9  * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
 10  */
 11 
 12 #include <linux/module.h>
 13 #include <linux/delay.h>
 14 #include <linux/of_gpio.h>
 15 #include <linux/clk.h>
 16 #include <linux/pm_runtime.h>
 17 #include <linux/mfd/syscon.h>
 18 #include <linux/regmap.h>
 19 #include <sound/pcm_params.h>
 20 #include <sound/dmaengine_pcm.h>
 21 
 22 #include "rockchip_spdif.h"
 23 
 24 enum rk_spdif_type {
 25         RK_SPDIF_RK3066,
 26         RK_SPDIF_RK3188,
 27         RK_SPDIF_RK3288,
 28         RK_SPDIF_RK3366,
 29 };
 30 
 31 #define RK3288_GRF_SOC_CON2 0x24c
 32 
 33 struct rk_spdif_dev {
 34         struct device *dev;
 35 
 36         struct clk *mclk;
 37         struct clk *hclk;
 38 
 39         struct snd_dmaengine_dai_dma_data playback_dma_data;
 40 
 41         struct regmap *regmap;
 42 };
 43 
 44 static const struct of_device_id rk_spdif_match[] = {
 45         { .compatible = "rockchip,rk3066-spdif",
 46           .data = (void *)RK_SPDIF_RK3066 },
 47         { .compatible = "rockchip,rk3188-spdif",
 48           .data = (void *)RK_SPDIF_RK3188 },
 49         { .compatible = "rockchip,rk3228-spdif",
 50           .data = (void *)RK_SPDIF_RK3366 },
 51         { .compatible = "rockchip,rk3288-spdif",
 52           .data = (void *)RK_SPDIF_RK3288 },
 53         { .compatible = "rockchip,rk3328-spdif",
 54           .data = (void *)RK_SPDIF_RK3366 },
 55         { .compatible = "rockchip,rk3366-spdif",
 56           .data = (void *)RK_SPDIF_RK3366 },
 57         { .compatible = "rockchip,rk3368-spdif",
 58           .data = (void *)RK_SPDIF_RK3366 },
 59         { .compatible = "rockchip,rk3399-spdif",
 60           .data = (void *)RK_SPDIF_RK3366 },
 61         {},
 62 };
 63 MODULE_DEVICE_TABLE(of, rk_spdif_match);
 64 
 65 static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev)
 66 {
 67         struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
 68 
 69         regcache_cache_only(spdif->regmap, true);
 70         clk_disable_unprepare(spdif->mclk);
 71         clk_disable_unprepare(spdif->hclk);
 72 
 73         return 0;
 74 }
 75 
 76 static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
 77 {
 78         struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
 79         int ret;
 80 
 81         ret = clk_prepare_enable(spdif->mclk);
 82         if (ret) {
 83                 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
 84                 return ret;
 85         }
 86 
 87         ret = clk_prepare_enable(spdif->hclk);
 88         if (ret) {
 89                 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
 90                 return ret;
 91         }
 92 
 93         regcache_cache_only(spdif->regmap, false);
 94         regcache_mark_dirty(spdif->regmap);
 95 
 96         ret = regcache_sync(spdif->regmap);
 97         if (ret) {
 98                 clk_disable_unprepare(spdif->mclk);
 99                 clk_disable_unprepare(spdif->hclk);
100         }
101 
102         return ret;
103 }
104 
105 static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
106                                   struct snd_pcm_hw_params *params,
107                                   struct snd_soc_dai *dai)
108 {
109         struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
110         unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
111         int srate, mclk;
112         int ret;
113 
114         srate = params_rate(params);
115         mclk = srate * 128;
116 
117         switch (params_format(params)) {
118         case SNDRV_PCM_FORMAT_S16_LE:
119                 val |= SPDIF_CFGR_VDW_16;
120                 break;
121         case SNDRV_PCM_FORMAT_S20_3LE:
122                 val |= SPDIF_CFGR_VDW_20;
123                 break;
124         case SNDRV_PCM_FORMAT_S24_LE:
125                 val |= SPDIF_CFGR_VDW_24;
126                 break;
127         default:
128                 return -EINVAL;
129         }
130 
131         /* Set clock and calculate divider */
132         ret = clk_set_rate(spdif->mclk, mclk);
133         if (ret != 0) {
134                 dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
135                         ret);
136                 return ret;
137         }
138 
139         ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
140                 SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE |
141                 SDPIF_CFGR_VDW_MASK,
142                 val);
143 
144         return ret;
145 }
146 
147 static int rk_spdif_trigger(struct snd_pcm_substream *substream,
148                                 int cmd, struct snd_soc_dai *dai)
149 {
150         struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
151         int ret;
152 
153         switch (cmd) {
154         case SNDRV_PCM_TRIGGER_START:
155         case SNDRV_PCM_TRIGGER_RESUME:
156         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
157                 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
158                                    SPDIF_DMACR_TDE_ENABLE |
159                                    SPDIF_DMACR_TDL_MASK,
160                                    SPDIF_DMACR_TDE_ENABLE |
161                                    SPDIF_DMACR_TDL(16));
162 
163                 if (ret != 0)
164                         return ret;
165 
166                 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
167                                    SPDIF_XFER_TXS_START,
168                                    SPDIF_XFER_TXS_START);
169                 break;
170         case SNDRV_PCM_TRIGGER_SUSPEND:
171         case SNDRV_PCM_TRIGGER_STOP:
172         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
173                 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
174                                    SPDIF_DMACR_TDE_ENABLE,
175                                    SPDIF_DMACR_TDE_DISABLE);
176 
177                 if (ret != 0)
178                         return ret;
179 
180                 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
181                                    SPDIF_XFER_TXS_START,
182                                    SPDIF_XFER_TXS_STOP);
183                 break;
184         default:
185                 ret = -EINVAL;
186                 break;
187         }
188 
189         return ret;
190 }
191 
192 static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
193 {
194         struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
195 
196         dai->playback_dma_data = &spdif->playback_dma_data;
197 
198         return 0;
199 }
200 
201 static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
202         .hw_params = rk_spdif_hw_params,
203         .trigger = rk_spdif_trigger,
204 };
205 
206 static struct snd_soc_dai_driver rk_spdif_dai = {
207         .probe = rk_spdif_dai_probe,
208         .playback = {
209                 .stream_name = "Playback",
210                 .channels_min = 2,
211                 .channels_max = 2,
212                 .rates = (SNDRV_PCM_RATE_32000 |
213                           SNDRV_PCM_RATE_44100 |
214                           SNDRV_PCM_RATE_48000 |
215                           SNDRV_PCM_RATE_96000 |
216                           SNDRV_PCM_RATE_192000),
217                 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
218                             SNDRV_PCM_FMTBIT_S20_3LE |
219                             SNDRV_PCM_FMTBIT_S24_LE),
220         },
221         .ops = &rk_spdif_dai_ops,
222 };
223 
224 static const struct snd_soc_component_driver rk_spdif_component = {
225         .name = "rockchip-spdif",
226 };
227 
228 static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
229 {
230         switch (reg) {
231         case SPDIF_CFGR:
232         case SPDIF_DMACR:
233         case SPDIF_INTCR:
234         case SPDIF_XFER:
235         case SPDIF_SMPDR:
236                 return true;
237         default:
238                 return false;
239         }
240 }
241 
242 static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
243 {
244         switch (reg) {
245         case SPDIF_CFGR:
246         case SPDIF_SDBLR:
247         case SPDIF_INTCR:
248         case SPDIF_INTSR:
249         case SPDIF_XFER:
250                 return true;
251         default:
252                 return false;
253         }
254 }
255 
256 static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
257 {
258         switch (reg) {
259         case SPDIF_INTSR:
260         case SPDIF_SDBLR:
261                 return true;
262         default:
263                 return false;
264         }
265 }
266 
267 static const struct regmap_config rk_spdif_regmap_config = {
268         .reg_bits = 32,
269         .reg_stride = 4,
270         .val_bits = 32,
271         .max_register = SPDIF_SMPDR,
272         .writeable_reg = rk_spdif_wr_reg,
273         .readable_reg = rk_spdif_rd_reg,
274         .volatile_reg = rk_spdif_volatile_reg,
275         .cache_type = REGCACHE_FLAT,
276 };
277 
278 static int rk_spdif_probe(struct platform_device *pdev)
279 {
280         struct device_node *np = pdev->dev.of_node;
281         struct rk_spdif_dev *spdif;
282         const struct of_device_id *match;
283         struct resource *res;
284         void __iomem *regs;
285         int ret;
286 
287         match = of_match_node(rk_spdif_match, np);
288         if (match->data == (void *)RK_SPDIF_RK3288) {
289                 struct regmap *grf;
290 
291                 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
292                 if (IS_ERR(grf)) {
293                         dev_err(&pdev->dev,
294                                 "rockchip_spdif missing 'rockchip,grf' \n");
295                         return PTR_ERR(grf);
296                 }
297 
298                 /* Select the 8 channel SPDIF solution on RK3288 as
299                  * the 2 channel one does not appear to work
300                  */
301                 regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
302         }
303 
304         spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
305         if (!spdif)
306                 return -ENOMEM;
307 
308         spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
309         if (IS_ERR(spdif->hclk)) {
310                 dev_err(&pdev->dev, "Can't retrieve rk_spdif bus clock\n");
311                 return PTR_ERR(spdif->hclk);
312         }
313         ret = clk_prepare_enable(spdif->hclk);
314         if (ret) {
315                 dev_err(spdif->dev, "hclock enable failed %d\n", ret);
316                 return ret;
317         }
318 
319         spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
320         if (IS_ERR(spdif->mclk)) {
321                 dev_err(&pdev->dev, "Can't retrieve rk_spdif master clock\n");
322                 ret = PTR_ERR(spdif->mclk);
323                 goto err_disable_hclk;
324         }
325 
326         ret = clk_prepare_enable(spdif->mclk);
327         if (ret) {
328                 dev_err(spdif->dev, "clock enable failed %d\n", ret);
329                 goto err_disable_clocks;
330         }
331 
332         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
333         regs = devm_ioremap_resource(&pdev->dev, res);
334         if (IS_ERR(regs)) {
335                 ret = PTR_ERR(regs);
336                 goto err_disable_clocks;
337         }
338 
339         spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
340                                                   &rk_spdif_regmap_config);
341         if (IS_ERR(spdif->regmap)) {
342                 dev_err(&pdev->dev,
343                         "Failed to initialise managed register map\n");
344                 ret = PTR_ERR(spdif->regmap);
345                 goto err_disable_clocks;
346         }
347 
348         spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
349         spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
350         spdif->playback_dma_data.maxburst = 4;
351 
352         spdif->dev = &pdev->dev;
353         dev_set_drvdata(&pdev->dev, spdif);
354 
355         pm_runtime_set_active(&pdev->dev);
356         pm_runtime_enable(&pdev->dev);
357         pm_request_idle(&pdev->dev);
358 
359         ret = devm_snd_soc_register_component(&pdev->dev,
360                                               &rk_spdif_component,
361                                               &rk_spdif_dai, 1);
362         if (ret) {
363                 dev_err(&pdev->dev, "Could not register DAI\n");
364                 goto err_pm_runtime;
365         }
366 
367         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
368         if (ret) {
369                 dev_err(&pdev->dev, "Could not register PCM\n");
370                 goto err_pm_runtime;
371         }
372 
373         return 0;
374 
375 err_pm_runtime:
376         pm_runtime_disable(&pdev->dev);
377 err_disable_clocks:
378         clk_disable_unprepare(spdif->mclk);
379 err_disable_hclk:
380         clk_disable_unprepare(spdif->hclk);
381 
382         return ret;
383 }
384 
385 static int rk_spdif_remove(struct platform_device *pdev)
386 {
387         struct rk_spdif_dev *spdif = dev_get_drvdata(&pdev->dev);
388 
389         pm_runtime_disable(&pdev->dev);
390         if (!pm_runtime_status_suspended(&pdev->dev))
391                 rk_spdif_runtime_suspend(&pdev->dev);
392 
393         clk_disable_unprepare(spdif->mclk);
394         clk_disable_unprepare(spdif->hclk);
395 
396         return 0;
397 }
398 
399 static const struct dev_pm_ops rk_spdif_pm_ops = {
400         SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
401                            NULL)
402 };
403 
404 static struct platform_driver rk_spdif_driver = {
405         .probe = rk_spdif_probe,
406         .remove = rk_spdif_remove,
407         .driver = {
408                 .name = "rockchip-spdif",
409                 .of_match_table = of_match_ptr(rk_spdif_match),
410                 .pm = &rk_spdif_pm_ops,
411         },
412 };
413 module_platform_driver(rk_spdif_driver);
414 
415 MODULE_ALIAS("platform:rockchip-spdif");
416 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
417 MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
418 MODULE_LICENSE("GPL v2");
419 

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