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Linux/sound/soc/ti/davinci-mcasp.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  4  *
  5  * Multi-channel Audio Serial Port Driver
  6  *
  7  * Author: Nirmal Pandey <n-pandey@ti.com>,
  8  *         Suresh Rajashekara <suresh.r@ti.com>
  9  *         Steve Chen <schen@.mvista.com>
 10  *
 11  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 12  * Copyright:   (C) 2009  Texas Instruments, India
 13  */
 14 
 15 #include <linux/init.h>
 16 #include <linux/module.h>
 17 #include <linux/device.h>
 18 #include <linux/slab.h>
 19 #include <linux/delay.h>
 20 #include <linux/io.h>
 21 #include <linux/clk.h>
 22 #include <linux/pm_runtime.h>
 23 #include <linux/of.h>
 24 #include <linux/of_platform.h>
 25 #include <linux/of_device.h>
 26 #include <linux/platform_data/davinci_asp.h>
 27 #include <linux/math64.h>
 28 #include <linux/bitmap.h>
 29 #include <linux/gpio/driver.h>
 30 
 31 #include <sound/asoundef.h>
 32 #include <sound/core.h>
 33 #include <sound/pcm.h>
 34 #include <sound/pcm_params.h>
 35 #include <sound/initval.h>
 36 #include <sound/soc.h>
 37 #include <sound/dmaengine_pcm.h>
 38 
 39 #include "edma-pcm.h"
 40 #include "sdma-pcm.h"
 41 #include "davinci-mcasp.h"
 42 
 43 #define MCASP_MAX_AFIFO_DEPTH   64
 44 
 45 #ifdef CONFIG_PM
 46 static u32 context_regs[] = {
 47         DAVINCI_MCASP_TXFMCTL_REG,
 48         DAVINCI_MCASP_RXFMCTL_REG,
 49         DAVINCI_MCASP_TXFMT_REG,
 50         DAVINCI_MCASP_RXFMT_REG,
 51         DAVINCI_MCASP_ACLKXCTL_REG,
 52         DAVINCI_MCASP_ACLKRCTL_REG,
 53         DAVINCI_MCASP_AHCLKXCTL_REG,
 54         DAVINCI_MCASP_AHCLKRCTL_REG,
 55         DAVINCI_MCASP_PDIR_REG,
 56         DAVINCI_MCASP_PFUNC_REG,
 57         DAVINCI_MCASP_RXMASK_REG,
 58         DAVINCI_MCASP_TXMASK_REG,
 59         DAVINCI_MCASP_RXTDM_REG,
 60         DAVINCI_MCASP_TXTDM_REG,
 61 };
 62 
 63 struct davinci_mcasp_context {
 64         u32     config_regs[ARRAY_SIZE(context_regs)];
 65         u32     afifo_regs[2]; /* for read/write fifo control registers */
 66         u32     *xrsr_regs; /* for serializer configuration */
 67         bool    pm_state;
 68 };
 69 #endif
 70 
 71 struct davinci_mcasp_ruledata {
 72         struct davinci_mcasp *mcasp;
 73         int serializers;
 74 };
 75 
 76 struct davinci_mcasp {
 77         struct snd_dmaengine_dai_dma_data dma_data[2];
 78         void __iomem *base;
 79         u32 fifo_base;
 80         struct device *dev;
 81         struct snd_pcm_substream *substreams[2];
 82         unsigned int dai_fmt;
 83 
 84         /* McASP specific data */
 85         int     tdm_slots;
 86         u32     tdm_mask[2];
 87         int     slot_width;
 88         u8      op_mode;
 89         u8      dismod;
 90         u8      num_serializer;
 91         u8      *serial_dir;
 92         u8      version;
 93         u8      bclk_div;
 94         int     streams;
 95         u32     irq_request[2];
 96         int     dma_request[2];
 97 
 98         int     sysclk_freq;
 99         bool    bclk_master;
100         u32     auxclk_fs_ratio;
101 
102         unsigned long pdir; /* Pin direction bitfield */
103 
104         /* McASP FIFO related */
105         u8      txnumevt;
106         u8      rxnumevt;
107 
108         bool    dat_port;
109 
110         /* Used for comstraint setting on the second stream */
111         u32     channels;
112 
113 #ifdef CONFIG_GPIOLIB
114         struct gpio_chip gpio_chip;
115 #endif
116 
117 #ifdef CONFIG_PM
118         struct davinci_mcasp_context context;
119 #endif
120 
121         struct davinci_mcasp_ruledata ruledata[2];
122         struct snd_pcm_hw_constraint_list chconstr[2];
123 };
124 
125 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
126                                   u32 val)
127 {
128         void __iomem *reg = mcasp->base + offset;
129         __raw_writel(__raw_readl(reg) | val, reg);
130 }
131 
132 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
133                                   u32 val)
134 {
135         void __iomem *reg = mcasp->base + offset;
136         __raw_writel((__raw_readl(reg) & ~(val)), reg);
137 }
138 
139 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
140                                   u32 val, u32 mask)
141 {
142         void __iomem *reg = mcasp->base + offset;
143         __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
144 }
145 
146 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
147                                  u32 val)
148 {
149         __raw_writel(val, mcasp->base + offset);
150 }
151 
152 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
153 {
154         return (u32)__raw_readl(mcasp->base + offset);
155 }
156 
157 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
158 {
159         int i = 0;
160 
161         mcasp_set_bits(mcasp, ctl_reg, val);
162 
163         /* programming GBLCTL needs to read back from GBLCTL and verfiy */
164         /* loop count is to avoid the lock-up */
165         for (i = 0; i < 1000; i++) {
166                 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
167                         break;
168         }
169 
170         if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
171                 printk(KERN_ERR "GBLCTL write error\n");
172 }
173 
174 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
175 {
176         u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
177         u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
178 
179         return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
180 }
181 
182 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
183 {
184         u32 bit = PIN_BIT_AMUTE;
185 
186         for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
187                 if (enable)
188                         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
189                 else
190                         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
191         }
192 }
193 
194 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
195 {
196         u32 bit;
197 
198         for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
199                 if (enable)
200                         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
201                 else
202                         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
203         }
204 }
205 
206 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
207 {
208         if (mcasp->rxnumevt) {  /* enable FIFO */
209                 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
210 
211                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
212                 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
213         }
214 
215         /* Start clocks */
216         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
217         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
218         /*
219          * When ASYNC == 0 the transmit and receive sections operate
220          * synchronously from the transmit clock and frame sync. We need to make
221          * sure that the TX signlas are enabled when starting reception.
222          */
223         if (mcasp_is_synchronous(mcasp)) {
224                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
225                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
226                 mcasp_set_clk_pdir(mcasp, true);
227         }
228 
229         /* Activate serializer(s) */
230         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
231         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
232         /* Release RX state machine */
233         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
234         /* Release Frame Sync generator */
235         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
236         if (mcasp_is_synchronous(mcasp))
237                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
238 
239         /* enable receive IRQs */
240         mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
241                        mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
242 }
243 
244 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
245 {
246         u32 cnt;
247 
248         if (mcasp->txnumevt) {  /* enable FIFO */
249                 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
250 
251                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
252                 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
253         }
254 
255         /* Start clocks */
256         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
257         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
258         mcasp_set_clk_pdir(mcasp, true);
259 
260         /* Activate serializer(s) */
261         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
262         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
263 
264         /* wait for XDATA to be cleared */
265         cnt = 0;
266         while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
267                (cnt < 100000))
268                 cnt++;
269 
270         mcasp_set_axr_pdir(mcasp, true);
271 
272         /* Release TX state machine */
273         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
274         /* Release Frame Sync generator */
275         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
276 
277         /* enable transmit IRQs */
278         mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
279                        mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
280 }
281 
282 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
283 {
284         mcasp->streams++;
285 
286         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
287                 mcasp_start_tx(mcasp);
288         else
289                 mcasp_start_rx(mcasp);
290 }
291 
292 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
293 {
294         /* disable IRQ sources */
295         mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
296                        mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
297 
298         /*
299          * In synchronous mode stop the TX clocks if no other stream is
300          * running
301          */
302         if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
303                 mcasp_set_clk_pdir(mcasp, false);
304                 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
305         }
306 
307         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
308         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
309 
310         if (mcasp->rxnumevt) {  /* disable FIFO */
311                 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
312 
313                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
314         }
315 }
316 
317 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
318 {
319         u32 val = 0;
320 
321         /* disable IRQ sources */
322         mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
323                        mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
324 
325         /*
326          * In synchronous mode keep TX clocks running if the capture stream is
327          * still running.
328          */
329         if (mcasp_is_synchronous(mcasp) && mcasp->streams)
330                 val =  TXHCLKRST | TXCLKRST | TXFSRST;
331         else
332                 mcasp_set_clk_pdir(mcasp, false);
333 
334 
335         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
336         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
337 
338         if (mcasp->txnumevt) {  /* disable FIFO */
339                 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
340 
341                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
342         }
343 
344         mcasp_set_axr_pdir(mcasp, false);
345 }
346 
347 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
348 {
349         mcasp->streams--;
350 
351         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
352                 mcasp_stop_tx(mcasp);
353         else
354                 mcasp_stop_rx(mcasp);
355 }
356 
357 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
358 {
359         struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
360         struct snd_pcm_substream *substream;
361         u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
362         u32 handled_mask = 0;
363         u32 stat;
364 
365         stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
366         if (stat & XUNDRN & irq_mask) {
367                 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
368                 handled_mask |= XUNDRN;
369 
370                 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
371                 if (substream)
372                         snd_pcm_stop_xrun(substream);
373         }
374 
375         if (!handled_mask)
376                 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
377                          stat);
378 
379         if (stat & XRERR)
380                 handled_mask |= XRERR;
381 
382         /* Ack the handled event only */
383         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
384 
385         return IRQ_RETVAL(handled_mask);
386 }
387 
388 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
389 {
390         struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
391         struct snd_pcm_substream *substream;
392         u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
393         u32 handled_mask = 0;
394         u32 stat;
395 
396         stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
397         if (stat & ROVRN & irq_mask) {
398                 dev_warn(mcasp->dev, "Receive buffer overflow\n");
399                 handled_mask |= ROVRN;
400 
401                 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
402                 if (substream)
403                         snd_pcm_stop_xrun(substream);
404         }
405 
406         if (!handled_mask)
407                 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
408                          stat);
409 
410         if (stat & XRERR)
411                 handled_mask |= XRERR;
412 
413         /* Ack the handled event only */
414         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
415 
416         return IRQ_RETVAL(handled_mask);
417 }
418 
419 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
420 {
421         struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
422         irqreturn_t ret = IRQ_NONE;
423 
424         if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
425                 ret = davinci_mcasp_tx_irq_handler(irq, data);
426 
427         if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
428                 ret |= davinci_mcasp_rx_irq_handler(irq, data);
429 
430         return ret;
431 }
432 
433 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
434                                          unsigned int fmt)
435 {
436         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
437         int ret = 0;
438         u32 data_delay;
439         bool fs_pol_rising;
440         bool inv_fs = false;
441 
442         if (!fmt)
443                 return 0;
444 
445         pm_runtime_get_sync(mcasp->dev);
446         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
447         case SND_SOC_DAIFMT_DSP_A:
448                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
449                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
450                 /* 1st data bit occur one ACLK cycle after the frame sync */
451                 data_delay = 1;
452                 break;
453         case SND_SOC_DAIFMT_DSP_B:
454         case SND_SOC_DAIFMT_AC97:
455                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
456                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
457                 /* No delay after FS */
458                 data_delay = 0;
459                 break;
460         case SND_SOC_DAIFMT_I2S:
461                 /* configure a full-word SYNC pulse (LRCLK) */
462                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
463                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
464                 /* 1st data bit occur one ACLK cycle after the frame sync */
465                 data_delay = 1;
466                 /* FS need to be inverted */
467                 inv_fs = true;
468                 break;
469         case SND_SOC_DAIFMT_LEFT_J:
470                 /* configure a full-word SYNC pulse (LRCLK) */
471                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
472                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
473                 /* No delay after FS */
474                 data_delay = 0;
475                 break;
476         default:
477                 ret = -EINVAL;
478                 goto out;
479         }
480 
481         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
482                        FSXDLY(3));
483         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
484                        FSRDLY(3));
485 
486         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
487         case SND_SOC_DAIFMT_CBS_CFS:
488                 /* codec is clock and frame slave */
489                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
490                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
491 
492                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
493                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
494 
495                 /* BCLK */
496                 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
497                 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
498                 /* Frame Sync */
499                 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
500                 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
501 
502                 mcasp->bclk_master = 1;
503                 break;
504         case SND_SOC_DAIFMT_CBS_CFM:
505                 /* codec is clock slave and frame master */
506                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
507                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
508 
509                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
510                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
511 
512                 /* BCLK */
513                 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
514                 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
515                 /* Frame Sync */
516                 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
517                 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
518 
519                 mcasp->bclk_master = 1;
520                 break;
521         case SND_SOC_DAIFMT_CBM_CFS:
522                 /* codec is clock master and frame slave */
523                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
524                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
525 
526                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
527                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
528 
529                 /* BCLK */
530                 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
531                 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
532                 /* Frame Sync */
533                 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
534                 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
535 
536                 mcasp->bclk_master = 0;
537                 break;
538         case SND_SOC_DAIFMT_CBM_CFM:
539                 /* codec is clock and frame master */
540                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
541                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
542 
543                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
544                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
545 
546                 /* BCLK */
547                 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
548                 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
549                 /* Frame Sync */
550                 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
551                 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
552 
553                 mcasp->bclk_master = 0;
554                 break;
555         default:
556                 ret = -EINVAL;
557                 goto out;
558         }
559 
560         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
561         case SND_SOC_DAIFMT_IB_NF:
562                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
563                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
564                 fs_pol_rising = true;
565                 break;
566         case SND_SOC_DAIFMT_NB_IF:
567                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
568                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
569                 fs_pol_rising = false;
570                 break;
571         case SND_SOC_DAIFMT_IB_IF:
572                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
573                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
574                 fs_pol_rising = false;
575                 break;
576         case SND_SOC_DAIFMT_NB_NF:
577                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
578                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
579                 fs_pol_rising = true;
580                 break;
581         default:
582                 ret = -EINVAL;
583                 goto out;
584         }
585 
586         if (inv_fs)
587                 fs_pol_rising = !fs_pol_rising;
588 
589         if (fs_pol_rising) {
590                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
591                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
592         } else {
593                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
594                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
595         }
596 
597         mcasp->dai_fmt = fmt;
598 out:
599         pm_runtime_put(mcasp->dev);
600         return ret;
601 }
602 
603 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
604                                       int div, bool explicit)
605 {
606         pm_runtime_get_sync(mcasp->dev);
607         switch (div_id) {
608         case MCASP_CLKDIV_AUXCLK:                       /* MCLK divider */
609                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
610                                AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
611                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
612                                AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
613                 break;
614 
615         case MCASP_CLKDIV_BCLK:                 /* BCLK divider */
616                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
617                                ACLKXDIV(div - 1), ACLKXDIV_MASK);
618                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
619                                ACLKRDIV(div - 1), ACLKRDIV_MASK);
620                 if (explicit)
621                         mcasp->bclk_div = div;
622                 break;
623 
624         case MCASP_CLKDIV_BCLK_FS_RATIO:
625                 /*
626                  * BCLK/LRCLK ratio descries how many bit-clock cycles
627                  * fit into one frame. The clock ratio is given for a
628                  * full period of data (for I2S format both left and
629                  * right channels), so it has to be divided by number
630                  * of tdm-slots (for I2S - divided by 2).
631                  * Instead of storing this ratio, we calculate a new
632                  * tdm_slot width by dividing the the ratio by the
633                  * number of configured tdm slots.
634                  */
635                 mcasp->slot_width = div / mcasp->tdm_slots;
636                 if (div % mcasp->tdm_slots)
637                         dev_warn(mcasp->dev,
638                                  "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
639                                  __func__, div, mcasp->tdm_slots);
640                 break;
641 
642         default:
643                 return -EINVAL;
644         }
645 
646         pm_runtime_put(mcasp->dev);
647         return 0;
648 }
649 
650 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
651                                     int div)
652 {
653         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
654 
655         return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
656 }
657 
658 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
659                                     unsigned int freq, int dir)
660 {
661         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
662 
663         pm_runtime_get_sync(mcasp->dev);
664         if (dir == SND_SOC_CLOCK_OUT) {
665                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
666                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
667                 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
668         } else {
669                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
670                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
671                 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
672         }
673 
674         mcasp->sysclk_freq = freq;
675 
676         pm_runtime_put(mcasp->dev);
677         return 0;
678 }
679 
680 /* All serializers must have equal number of channels */
681 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
682                                        int serializers)
683 {
684         struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
685         unsigned int *list = (unsigned int *) cl->list;
686         int slots = mcasp->tdm_slots;
687         int i, count = 0;
688 
689         if (mcasp->tdm_mask[stream])
690                 slots = hweight32(mcasp->tdm_mask[stream]);
691 
692         for (i = 1; i <= slots; i++)
693                 list[count++] = i;
694 
695         for (i = 2; i <= serializers; i++)
696                 list[count++] = i*slots;
697 
698         cl->count = count;
699 
700         return 0;
701 }
702 
703 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
704 {
705         int rx_serializers = 0, tx_serializers = 0, ret, i;
706 
707         for (i = 0; i < mcasp->num_serializer; i++)
708                 if (mcasp->serial_dir[i] == TX_MODE)
709                         tx_serializers++;
710                 else if (mcasp->serial_dir[i] == RX_MODE)
711                         rx_serializers++;
712 
713         ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
714                                           tx_serializers);
715         if (ret)
716                 return ret;
717 
718         ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
719                                           rx_serializers);
720 
721         return ret;
722 }
723 
724 
725 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
726                                       unsigned int tx_mask,
727                                       unsigned int rx_mask,
728                                       int slots, int slot_width)
729 {
730         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
731 
732         dev_dbg(mcasp->dev,
733                  "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
734                  __func__, tx_mask, rx_mask, slots, slot_width);
735 
736         if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
737                 dev_err(mcasp->dev,
738                         "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
739                         tx_mask, rx_mask, slots);
740                 return -EINVAL;
741         }
742 
743         if (slot_width &&
744             (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
745                 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
746                         __func__, slot_width);
747                 return -EINVAL;
748         }
749 
750         mcasp->tdm_slots = slots;
751         mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
752         mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
753         mcasp->slot_width = slot_width;
754 
755         return davinci_mcasp_set_ch_constraints(mcasp);
756 }
757 
758 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
759                                        int sample_width)
760 {
761         u32 fmt;
762         u32 tx_rotate = (sample_width / 4) & 0x7;
763         u32 mask = (1ULL << sample_width) - 1;
764         u32 slot_width = sample_width;
765 
766         /*
767          * For captured data we should not rotate, inversion and masking is
768          * enoguh to get the data to the right position:
769          * Format         data from bus         after reverse (XRBUF)
770          * S16_LE:      |LSB|MSB|xxx|xxx|       |xxx|xxx|MSB|LSB|
771          * S24_3LE:     |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
772          * S24_LE:      |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
773          * S32_LE:      |LSB|DAT|DAT|MSB|       |MSB|DAT|DAT|LSB|
774          */
775         u32 rx_rotate = 0;
776 
777         /*
778          * Setting the tdm slot width either with set_clkdiv() or
779          * set_tdm_slot() allows us to for example send 32 bits per
780          * channel to the codec, while only 16 of them carry audio
781          * payload.
782          */
783         if (mcasp->slot_width) {
784                 /*
785                  * When we have more bclk then it is needed for the
786                  * data, we need to use the rotation to move the
787                  * received samples to have correct alignment.
788                  */
789                 slot_width = mcasp->slot_width;
790                 rx_rotate = (slot_width - sample_width) / 4;
791         }
792 
793         /* mapping of the XSSZ bit-field as described in the datasheet */
794         fmt = (slot_width >> 1) - 1;
795 
796         if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
797                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
798                                RXSSZ(0x0F));
799                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
800                                TXSSZ(0x0F));
801                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
802                                TXROT(7));
803                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
804                                RXROT(7));
805                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
806         }
807 
808         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
809 
810         return 0;
811 }
812 
813 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
814                                  int period_words, int channels)
815 {
816         struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
817         int i;
818         u8 tx_ser = 0;
819         u8 rx_ser = 0;
820         u8 slots = mcasp->tdm_slots;
821         u8 max_active_serializers = (channels + slots - 1) / slots;
822         int active_serializers, numevt;
823         u32 reg;
824         /* Default configuration */
825         if (mcasp->version < MCASP_VERSION_3)
826                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
827 
828         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
829                 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
830                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
831         } else {
832                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
833                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
834         }
835 
836         for (i = 0; i < mcasp->num_serializer; i++) {
837                 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
838                                mcasp->serial_dir[i]);
839                 if (mcasp->serial_dir[i] == TX_MODE &&
840                                         tx_ser < max_active_serializers) {
841                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
842                                        mcasp->dismod, DISMOD_MASK);
843                         set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
844                         tx_ser++;
845                 } else if (mcasp->serial_dir[i] == RX_MODE &&
846                                         rx_ser < max_active_serializers) {
847                         clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
848                         rx_ser++;
849                 } else {
850                         /* Inactive or unused pin, set it to inactive */
851                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
852                                        SRMOD_INACTIVE, SRMOD_MASK);
853                         /* If unused, set DISMOD for the pin */
854                         if (mcasp->serial_dir[i] != INACTIVE_MODE)
855                                 mcasp_mod_bits(mcasp,
856                                                DAVINCI_MCASP_XRSRCTL_REG(i),
857                                                mcasp->dismod, DISMOD_MASK);
858                         clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
859                 }
860         }
861 
862         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
863                 active_serializers = tx_ser;
864                 numevt = mcasp->txnumevt;
865                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
866         } else {
867                 active_serializers = rx_ser;
868                 numevt = mcasp->rxnumevt;
869                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
870         }
871 
872         if (active_serializers < max_active_serializers) {
873                 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
874                          "enabled in mcasp (%d)\n", channels,
875                          active_serializers * slots);
876                 return -EINVAL;
877         }
878 
879         /* AFIFO is not in use */
880         if (!numevt) {
881                 /* Configure the burst size for platform drivers */
882                 if (active_serializers > 1) {
883                         /*
884                          * If more than one serializers are in use we have one
885                          * DMA request to provide data for all serializers.
886                          * For example if three serializers are enabled the DMA
887                          * need to transfer three words per DMA request.
888                          */
889                         dma_data->maxburst = active_serializers;
890                 } else {
891                         dma_data->maxburst = 0;
892                 }
893                 return 0;
894         }
895 
896         if (period_words % active_serializers) {
897                 dev_err(mcasp->dev, "Invalid combination of period words and "
898                         "active serializers: %d, %d\n", period_words,
899                         active_serializers);
900                 return -EINVAL;
901         }
902 
903         /*
904          * Calculate the optimal AFIFO depth for platform side:
905          * The number of words for numevt need to be in steps of active
906          * serializers.
907          */
908         numevt = (numevt / active_serializers) * active_serializers;
909 
910         while (period_words % numevt && numevt > 0)
911                 numevt -= active_serializers;
912         if (numevt <= 0)
913                 numevt = active_serializers;
914 
915         mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
916         mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
917 
918         /* Configure the burst size for platform drivers */
919         if (numevt == 1)
920                 numevt = 0;
921         dma_data->maxburst = numevt;
922 
923         return 0;
924 }
925 
926 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
927                               int channels)
928 {
929         int i, active_slots;
930         int total_slots;
931         int active_serializers;
932         u32 mask = 0;
933         u32 busel = 0;
934 
935         total_slots = mcasp->tdm_slots;
936 
937         /*
938          * If more than one serializer is needed, then use them with
939          * all the specified tdm_slots. Otherwise, one serializer can
940          * cope with the transaction using just as many slots as there
941          * are channels in the stream.
942          */
943         if (mcasp->tdm_mask[stream]) {
944                 active_slots = hweight32(mcasp->tdm_mask[stream]);
945                 active_serializers = (channels + active_slots - 1) /
946                         active_slots;
947                 if (active_serializers == 1)
948                         active_slots = channels;
949                 for (i = 0; i < total_slots; i++) {
950                         if ((1 << i) & mcasp->tdm_mask[stream]) {
951                                 mask |= (1 << i);
952                                 if (--active_slots <= 0)
953                                         break;
954                         }
955                 }
956         } else {
957                 active_serializers = (channels + total_slots - 1) / total_slots;
958                 if (active_serializers == 1)
959                         active_slots = channels;
960                 else
961                         active_slots = total_slots;
962 
963                 for (i = 0; i < active_slots; i++)
964                         mask |= (1 << i);
965         }
966 
967         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
968 
969         if (!mcasp->dat_port)
970                 busel = TXSEL;
971 
972         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
973                 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
974                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
975                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
976                                FSXMOD(total_slots), FSXMOD(0x1FF));
977         } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
978                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
979                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
980                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
981                                FSRMOD(total_slots), FSRMOD(0x1FF));
982                 /*
983                  * If McASP is set to be TX/RX synchronous and the playback is
984                  * not running already we need to configure the TX slots in
985                  * order to have correct FSX on the bus
986                  */
987                 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
988                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
989                                        FSXMOD(total_slots), FSXMOD(0x1FF));
990         }
991 
992         return 0;
993 }
994 
995 /* S/PDIF */
996 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
997                               unsigned int rate)
998 {
999         u32 cs_value = 0;
1000         u8 *cs_bytes = (u8*) &cs_value;
1001 
1002         /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
1003            and LSB first */
1004         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
1005 
1006         /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1007         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1008 
1009         /* Set the TX tdm : for all the slots */
1010         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1011 
1012         /* Set the TX clock controls : div = 1 and internal */
1013         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1014 
1015         mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1016 
1017         /* Only 44100 and 48000 are valid, both have the same setting */
1018         mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
1019 
1020         /* Enable the DIT */
1021         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1022 
1023         /* Set S/PDIF channel status bits */
1024         cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1025         cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1026 
1027         switch (rate) {
1028         case 22050:
1029                 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1030                 break;
1031         case 24000:
1032                 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1033                 break;
1034         case 32000:
1035                 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1036                 break;
1037         case 44100:
1038                 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1039                 break;
1040         case 48000:
1041                 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1042                 break;
1043         case 88200:
1044                 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1045                 break;
1046         case 96000:
1047                 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1048                 break;
1049         case 176400:
1050                 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1051                 break;
1052         case 192000:
1053                 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1054                 break;
1055         default:
1056                 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1057                 return -EINVAL;
1058         }
1059 
1060         mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1061         mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1062 
1063         return 0;
1064 }
1065 
1066 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1067                                       unsigned int sysclk_freq,
1068                                       unsigned int bclk_freq, bool set)
1069 {
1070         u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1071         int div = sysclk_freq / bclk_freq;
1072         int rem = sysclk_freq % bclk_freq;
1073         int error_ppm;
1074         int aux_div = 1;
1075 
1076         if (div > (ACLKXDIV_MASK + 1)) {
1077                 if (reg & AHCLKXE) {
1078                         aux_div = div / (ACLKXDIV_MASK + 1);
1079                         if (div % (ACLKXDIV_MASK + 1))
1080                                 aux_div++;
1081 
1082                         sysclk_freq /= aux_div;
1083                         div = sysclk_freq / bclk_freq;
1084                         rem = sysclk_freq % bclk_freq;
1085                 } else if (set) {
1086                         dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1087                                  sysclk_freq);
1088                 }
1089         }
1090 
1091         if (rem != 0) {
1092                 if (div == 0 ||
1093                     ((sysclk_freq / div) - bclk_freq) >
1094                     (bclk_freq - (sysclk_freq / (div+1)))) {
1095                         div++;
1096                         rem = rem - bclk_freq;
1097                 }
1098         }
1099         error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1100                      (int)bclk_freq)) / div - 1000000;
1101 
1102         if (set) {
1103                 if (error_ppm)
1104                         dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1105                                  error_ppm);
1106 
1107                 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1108                 if (reg & AHCLKXE)
1109                         __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1110                                                    aux_div, 0);
1111         }
1112 
1113         return error_ppm;
1114 }
1115 
1116 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1117 {
1118         if (!mcasp->txnumevt)
1119                 return 0;
1120 
1121         return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1122 }
1123 
1124 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1125 {
1126         if (!mcasp->rxnumevt)
1127                 return 0;
1128 
1129         return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1130 }
1131 
1132 static snd_pcm_sframes_t davinci_mcasp_delay(
1133                         struct snd_pcm_substream *substream,
1134                         struct snd_soc_dai *cpu_dai)
1135 {
1136         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1137         u32 fifo_use;
1138 
1139         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1140                 fifo_use = davinci_mcasp_tx_delay(mcasp);
1141         else
1142                 fifo_use = davinci_mcasp_rx_delay(mcasp);
1143 
1144         /*
1145          * Divide the used locations with the channel count to get the
1146          * FIFO usage in samples (don't care about partial samples in the
1147          * buffer).
1148          */
1149         return fifo_use / substream->runtime->channels;
1150 }
1151 
1152 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1153                                         struct snd_pcm_hw_params *params,
1154                                         struct snd_soc_dai *cpu_dai)
1155 {
1156         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1157         int word_length;
1158         int channels = params_channels(params);
1159         int period_size = params_period_size(params);
1160         int ret;
1161 
1162         ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1163         if (ret)
1164                 return ret;
1165 
1166         /*
1167          * If mcasp is BCLK master, and a BCLK divider was not provided by
1168          * the machine driver, we need to calculate the ratio.
1169          */
1170         if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1171                 int slots = mcasp->tdm_slots;
1172                 int rate = params_rate(params);
1173                 int sbits = params_width(params);
1174 
1175                 if (mcasp->slot_width)
1176                         sbits = mcasp->slot_width;
1177 
1178                 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1179                                            rate * sbits * slots, true);
1180         }
1181 
1182         ret = mcasp_common_hw_param(mcasp, substream->stream,
1183                                     period_size * channels, channels);
1184         if (ret)
1185                 return ret;
1186 
1187         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1188                 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1189         else
1190                 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1191                                          channels);
1192 
1193         if (ret)
1194                 return ret;
1195 
1196         switch (params_format(params)) {
1197         case SNDRV_PCM_FORMAT_U8:
1198         case SNDRV_PCM_FORMAT_S8:
1199                 word_length = 8;
1200                 break;
1201 
1202         case SNDRV_PCM_FORMAT_U16_LE:
1203         case SNDRV_PCM_FORMAT_S16_LE:
1204                 word_length = 16;
1205                 break;
1206 
1207         case SNDRV_PCM_FORMAT_U24_3LE:
1208         case SNDRV_PCM_FORMAT_S24_3LE:
1209                 word_length = 24;
1210                 break;
1211 
1212         case SNDRV_PCM_FORMAT_U24_LE:
1213         case SNDRV_PCM_FORMAT_S24_LE:
1214                 word_length = 24;
1215                 break;
1216 
1217         case SNDRV_PCM_FORMAT_U32_LE:
1218         case SNDRV_PCM_FORMAT_S32_LE:
1219                 word_length = 32;
1220                 break;
1221 
1222         default:
1223                 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1224                 return -EINVAL;
1225         }
1226 
1227         davinci_config_channel_size(mcasp, word_length);
1228 
1229         if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1230                 mcasp->channels = channels;
1231 
1232         return 0;
1233 }
1234 
1235 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1236                                      int cmd, struct snd_soc_dai *cpu_dai)
1237 {
1238         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1239         int ret = 0;
1240 
1241         switch (cmd) {
1242         case SNDRV_PCM_TRIGGER_RESUME:
1243         case SNDRV_PCM_TRIGGER_START:
1244         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1245                 davinci_mcasp_start(mcasp, substream->stream);
1246                 break;
1247         case SNDRV_PCM_TRIGGER_SUSPEND:
1248         case SNDRV_PCM_TRIGGER_STOP:
1249         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1250                 davinci_mcasp_stop(mcasp, substream->stream);
1251                 break;
1252 
1253         default:
1254                 ret = -EINVAL;
1255         }
1256 
1257         return ret;
1258 }
1259 
1260 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1261                                             struct snd_pcm_hw_rule *rule)
1262 {
1263         struct davinci_mcasp_ruledata *rd = rule->private;
1264         struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1265         struct snd_mask nfmt;
1266         int i, slot_width;
1267 
1268         snd_mask_none(&nfmt);
1269         slot_width = rd->mcasp->slot_width;
1270 
1271         for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1272                 if (snd_mask_test(fmt, i)) {
1273                         if (snd_pcm_format_width(i) <= slot_width) {
1274                                 snd_mask_set(&nfmt, i);
1275                         }
1276                 }
1277         }
1278 
1279         return snd_mask_refine(fmt, &nfmt);
1280 }
1281 
1282 static const unsigned int davinci_mcasp_dai_rates[] = {
1283         8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1284         88200, 96000, 176400, 192000,
1285 };
1286 
1287 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1288 
1289 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1290                                       struct snd_pcm_hw_rule *rule)
1291 {
1292         struct davinci_mcasp_ruledata *rd = rule->private;
1293         struct snd_interval *ri =
1294                 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1295         int sbits = params_width(params);
1296         int slots = rd->mcasp->tdm_slots;
1297         struct snd_interval range;
1298         int i;
1299 
1300         if (rd->mcasp->slot_width)
1301                 sbits = rd->mcasp->slot_width;
1302 
1303         snd_interval_any(&range);
1304         range.empty = 1;
1305 
1306         for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1307                 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1308                         uint bclk_freq = sbits * slots *
1309                                          davinci_mcasp_dai_rates[i];
1310                         unsigned int sysclk_freq;
1311                         int ppm;
1312 
1313                         if (rd->mcasp->auxclk_fs_ratio)
1314                                 sysclk_freq =  davinci_mcasp_dai_rates[i] *
1315                                                rd->mcasp->auxclk_fs_ratio;
1316                         else
1317                                 sysclk_freq = rd->mcasp->sysclk_freq;
1318 
1319                         ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1320                                                          bclk_freq, false);
1321                         if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1322                                 if (range.empty) {
1323                                         range.min = davinci_mcasp_dai_rates[i];
1324                                         range.empty = 0;
1325                                 }
1326                                 range.max = davinci_mcasp_dai_rates[i];
1327                         }
1328                 }
1329         }
1330 
1331         dev_dbg(rd->mcasp->dev,
1332                 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1333                 ri->min, ri->max, range.min, range.max, sbits, slots);
1334 
1335         return snd_interval_refine(hw_param_interval(params, rule->var),
1336                                    &range);
1337 }
1338 
1339 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1340                                         struct snd_pcm_hw_rule *rule)
1341 {
1342         struct davinci_mcasp_ruledata *rd = rule->private;
1343         struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1344         struct snd_mask nfmt;
1345         int rate = params_rate(params);
1346         int slots = rd->mcasp->tdm_slots;
1347         int i, count = 0;
1348 
1349         snd_mask_none(&nfmt);
1350 
1351         for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1352                 if (snd_mask_test(fmt, i)) {
1353                         uint sbits = snd_pcm_format_width(i);
1354                         unsigned int sysclk_freq;
1355                         int ppm;
1356 
1357                         if (rd->mcasp->auxclk_fs_ratio)
1358                                 sysclk_freq =  rate *
1359                                                rd->mcasp->auxclk_fs_ratio;
1360                         else
1361                                 sysclk_freq = rd->mcasp->sysclk_freq;
1362 
1363                         if (rd->mcasp->slot_width)
1364                                 sbits = rd->mcasp->slot_width;
1365 
1366                         ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1367                                                          sbits * slots * rate,
1368                                                          false);
1369                         if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1370                                 snd_mask_set(&nfmt, i);
1371                                 count++;
1372                         }
1373                 }
1374         }
1375         dev_dbg(rd->mcasp->dev,
1376                 "%d possible sample format for %d Hz and %d tdm slots\n",
1377                 count, rate, slots);
1378 
1379         return snd_mask_refine(fmt, &nfmt);
1380 }
1381 
1382 static int davinci_mcasp_hw_rule_min_periodsize(
1383                 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1384 {
1385         struct snd_interval *period_size = hw_param_interval(params,
1386                                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1387         struct snd_interval frames;
1388 
1389         snd_interval_any(&frames);
1390         frames.min = 64;
1391         frames.integer = 1;
1392 
1393         return snd_interval_refine(period_size, &frames);
1394 }
1395 
1396 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1397                                  struct snd_soc_dai *cpu_dai)
1398 {
1399         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1400         struct davinci_mcasp_ruledata *ruledata =
1401                                         &mcasp->ruledata[substream->stream];
1402         u32 max_channels = 0;
1403         int i, dir, ret;
1404         int tdm_slots = mcasp->tdm_slots;
1405 
1406         /* Do not allow more then one stream per direction */
1407         if (mcasp->substreams[substream->stream])
1408                 return -EBUSY;
1409 
1410         mcasp->substreams[substream->stream] = substream;
1411 
1412         if (mcasp->tdm_mask[substream->stream])
1413                 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1414 
1415         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1416                 return 0;
1417 
1418         /*
1419          * Limit the maximum allowed channels for the first stream:
1420          * number of serializers for the direction * tdm slots per serializer
1421          */
1422         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1423                 dir = TX_MODE;
1424         else
1425                 dir = RX_MODE;
1426 
1427         for (i = 0; i < mcasp->num_serializer; i++) {
1428                 if (mcasp->serial_dir[i] == dir)
1429                         max_channels++;
1430         }
1431         ruledata->serializers = max_channels;
1432         ruledata->mcasp = mcasp;
1433         max_channels *= tdm_slots;
1434         /*
1435          * If the already active stream has less channels than the calculated
1436          * limnit based on the seirializers * tdm_slots, we need to use that as
1437          * a constraint for the second stream.
1438          * Otherwise (first stream or less allowed channels) we use the
1439          * calculated constraint.
1440          */
1441         if (mcasp->channels && mcasp->channels < max_channels)
1442                 max_channels = mcasp->channels;
1443         /*
1444          * But we can always allow channels upto the amount of
1445          * the available tdm_slots.
1446          */
1447         if (max_channels < tdm_slots)
1448                 max_channels = tdm_slots;
1449 
1450         snd_pcm_hw_constraint_minmax(substream->runtime,
1451                                      SNDRV_PCM_HW_PARAM_CHANNELS,
1452                                      0, max_channels);
1453 
1454         snd_pcm_hw_constraint_list(substream->runtime,
1455                                    0, SNDRV_PCM_HW_PARAM_CHANNELS,
1456                                    &mcasp->chconstr[substream->stream]);
1457 
1458         if (mcasp->slot_width) {
1459                 /* Only allow formats require <= slot_width bits on the bus */
1460                 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1461                                           SNDRV_PCM_HW_PARAM_FORMAT,
1462                                           davinci_mcasp_hw_rule_slot_width,
1463                                           ruledata,
1464                                           SNDRV_PCM_HW_PARAM_FORMAT, -1);
1465                 if (ret)
1466                         return ret;
1467         }
1468 
1469         /*
1470          * If we rely on implicit BCLK divider setting we should
1471          * set constraints based on what we can provide.
1472          */
1473         if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1474                 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1475                                           SNDRV_PCM_HW_PARAM_RATE,
1476                                           davinci_mcasp_hw_rule_rate,
1477                                           ruledata,
1478                                           SNDRV_PCM_HW_PARAM_FORMAT, -1);
1479                 if (ret)
1480                         return ret;
1481                 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1482                                           SNDRV_PCM_HW_PARAM_FORMAT,
1483                                           davinci_mcasp_hw_rule_format,
1484                                           ruledata,
1485                                           SNDRV_PCM_HW_PARAM_RATE, -1);
1486                 if (ret)
1487                         return ret;
1488         }
1489 
1490         snd_pcm_hw_rule_add(substream->runtime, 0,
1491                             SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1492                             davinci_mcasp_hw_rule_min_periodsize, NULL,
1493                             SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1494 
1495         return 0;
1496 }
1497 
1498 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1499                                    struct snd_soc_dai *cpu_dai)
1500 {
1501         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1502 
1503         mcasp->substreams[substream->stream] = NULL;
1504 
1505         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1506                 return;
1507 
1508         if (!cpu_dai->active)
1509                 mcasp->channels = 0;
1510 }
1511 
1512 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1513         .startup        = davinci_mcasp_startup,
1514         .shutdown       = davinci_mcasp_shutdown,
1515         .trigger        = davinci_mcasp_trigger,
1516         .delay          = davinci_mcasp_delay,
1517         .hw_params      = davinci_mcasp_hw_params,
1518         .set_fmt        = davinci_mcasp_set_dai_fmt,
1519         .set_clkdiv     = davinci_mcasp_set_clkdiv,
1520         .set_sysclk     = davinci_mcasp_set_sysclk,
1521         .set_tdm_slot   = davinci_mcasp_set_tdm_slot,
1522 };
1523 
1524 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1525 {
1526         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1527 
1528         dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1529         dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1530 
1531         return 0;
1532 }
1533 
1534 #define DAVINCI_MCASP_RATES     SNDRV_PCM_RATE_8000_192000
1535 
1536 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1537                                 SNDRV_PCM_FMTBIT_U8 | \
1538                                 SNDRV_PCM_FMTBIT_S16_LE | \
1539                                 SNDRV_PCM_FMTBIT_U16_LE | \
1540                                 SNDRV_PCM_FMTBIT_S24_LE | \
1541                                 SNDRV_PCM_FMTBIT_U24_LE | \
1542                                 SNDRV_PCM_FMTBIT_S24_3LE | \
1543                                 SNDRV_PCM_FMTBIT_U24_3LE | \
1544                                 SNDRV_PCM_FMTBIT_S32_LE | \
1545                                 SNDRV_PCM_FMTBIT_U32_LE)
1546 
1547 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1548         {
1549                 .name           = "davinci-mcasp.0",
1550                 .probe          = davinci_mcasp_dai_probe,
1551                 .playback       = {
1552                         .channels_min   = 1,
1553                         .channels_max   = 32 * 16,
1554                         .rates          = DAVINCI_MCASP_RATES,
1555                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1556                 },
1557                 .capture        = {
1558                         .channels_min   = 1,
1559                         .channels_max   = 32 * 16,
1560                         .rates          = DAVINCI_MCASP_RATES,
1561                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1562                 },
1563                 .ops            = &davinci_mcasp_dai_ops,
1564 
1565                 .symmetric_samplebits   = 1,
1566                 .symmetric_rates        = 1,
1567         },
1568         {
1569                 .name           = "davinci-mcasp.1",
1570                 .probe          = davinci_mcasp_dai_probe,
1571                 .playback       = {
1572                         .channels_min   = 1,
1573                         .channels_max   = 384,
1574                         .rates          = DAVINCI_MCASP_RATES,
1575                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1576                 },
1577                 .ops            = &davinci_mcasp_dai_ops,
1578         },
1579 
1580 };
1581 
1582 static const struct snd_soc_component_driver davinci_mcasp_component = {
1583         .name           = "davinci-mcasp",
1584 };
1585 
1586 /* Some HW specific values and defaults. The rest is filled in from DT. */
1587 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1588         .tx_dma_offset = 0x400,
1589         .rx_dma_offset = 0x400,
1590         .version = MCASP_VERSION_1,
1591 };
1592 
1593 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1594         .tx_dma_offset = 0x2000,
1595         .rx_dma_offset = 0x2000,
1596         .version = MCASP_VERSION_2,
1597 };
1598 
1599 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1600         .tx_dma_offset = 0,
1601         .rx_dma_offset = 0,
1602         .version = MCASP_VERSION_3,
1603 };
1604 
1605 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1606         /* The CFG port offset will be calculated if it is needed */
1607         .tx_dma_offset = 0,
1608         .rx_dma_offset = 0,
1609         .version = MCASP_VERSION_4,
1610 };
1611 
1612 static const struct of_device_id mcasp_dt_ids[] = {
1613         {
1614                 .compatible = "ti,dm646x-mcasp-audio",
1615                 .data = &dm646x_mcasp_pdata,
1616         },
1617         {
1618                 .compatible = "ti,da830-mcasp-audio",
1619                 .data = &da830_mcasp_pdata,
1620         },
1621         {
1622                 .compatible = "ti,am33xx-mcasp-audio",
1623                 .data = &am33xx_mcasp_pdata,
1624         },
1625         {
1626                 .compatible = "ti,dra7-mcasp-audio",
1627                 .data = &dra7_mcasp_pdata,
1628         },
1629         { /* sentinel */ }
1630 };
1631 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1632 
1633 static int mcasp_reparent_fck(struct platform_device *pdev)
1634 {
1635         struct device_node *node = pdev->dev.of_node;
1636         struct clk *gfclk, *parent_clk;
1637         const char *parent_name;
1638         int ret;
1639 
1640         if (!node)
1641                 return 0;
1642 
1643         parent_name = of_get_property(node, "fck_parent", NULL);
1644         if (!parent_name)
1645                 return 0;
1646 
1647         dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1648 
1649         gfclk = clk_get(&pdev->dev, "fck");
1650         if (IS_ERR(gfclk)) {
1651                 dev_err(&pdev->dev, "failed to get fck\n");
1652                 return PTR_ERR(gfclk);
1653         }
1654 
1655         parent_clk = clk_get(NULL, parent_name);
1656         if (IS_ERR(parent_clk)) {
1657                 dev_err(&pdev->dev, "failed to get parent clock\n");
1658                 ret = PTR_ERR(parent_clk);
1659                 goto err1;
1660         }
1661 
1662         ret = clk_set_parent(gfclk, parent_clk);
1663         if (ret) {
1664                 dev_err(&pdev->dev, "failed to reparent fck\n");
1665                 goto err2;
1666         }
1667 
1668 err2:
1669         clk_put(parent_clk);
1670 err1:
1671         clk_put(gfclk);
1672         return ret;
1673 }
1674 
1675 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1676                                                 struct platform_device *pdev)
1677 {
1678         struct device_node *np = pdev->dev.of_node;
1679         struct davinci_mcasp_pdata *pdata = NULL;
1680         const struct of_device_id *match =
1681                         of_match_device(mcasp_dt_ids, &pdev->dev);
1682         struct of_phandle_args dma_spec;
1683 
1684         const u32 *of_serial_dir32;
1685         u32 val;
1686         int i, ret = 0;
1687 
1688         if (pdev->dev.platform_data) {
1689                 pdata = pdev->dev.platform_data;
1690                 pdata->dismod = DISMOD_LOW;
1691                 return pdata;
1692         } else if (match) {
1693                 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1694                                      GFP_KERNEL);
1695                 if (!pdata) {
1696                         ret = -ENOMEM;
1697                         return pdata;
1698                 }
1699         } else {
1700                 /* control shouldn't reach here. something is wrong */
1701                 ret = -EINVAL;
1702                 goto nodata;
1703         }
1704 
1705         ret = of_property_read_u32(np, "op-mode", &val);
1706         if (ret >= 0)
1707                 pdata->op_mode = val;
1708 
1709         ret = of_property_read_u32(np, "tdm-slots", &val);
1710         if (ret >= 0) {
1711                 if (val < 2 || val > 32) {
1712                         dev_err(&pdev->dev,
1713                                 "tdm-slots must be in rage [2-32]\n");
1714                         ret = -EINVAL;
1715                         goto nodata;
1716                 }
1717 
1718                 pdata->tdm_slots = val;
1719         }
1720 
1721         of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1722         val /= sizeof(u32);
1723         if (of_serial_dir32) {
1724                 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1725                                                  (sizeof(*of_serial_dir) * val),
1726                                                  GFP_KERNEL);
1727                 if (!of_serial_dir) {
1728                         ret = -ENOMEM;
1729                         goto nodata;
1730                 }
1731 
1732                 for (i = 0; i < val; i++)
1733                         of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1734 
1735                 pdata->num_serializer = val;
1736                 pdata->serial_dir = of_serial_dir;
1737         }
1738 
1739         ret = of_property_match_string(np, "dma-names", "tx");
1740         if (ret < 0)
1741                 goto nodata;
1742 
1743         ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1744                                          &dma_spec);
1745         if (ret < 0)
1746                 goto nodata;
1747 
1748         pdata->tx_dma_channel = dma_spec.args[0];
1749 
1750         /* RX is not valid in DIT mode */
1751         if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1752                 ret = of_property_match_string(np, "dma-names", "rx");
1753                 if (ret < 0)
1754                         goto nodata;
1755 
1756                 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1757                                                  &dma_spec);
1758                 if (ret < 0)
1759                         goto nodata;
1760 
1761                 pdata->rx_dma_channel = dma_spec.args[0];
1762         }
1763 
1764         ret = of_property_read_u32(np, "tx-num-evt", &val);
1765         if (ret >= 0)
1766                 pdata->txnumevt = val;
1767 
1768         ret = of_property_read_u32(np, "rx-num-evt", &val);
1769         if (ret >= 0)
1770                 pdata->rxnumevt = val;
1771 
1772         ret = of_property_read_u32(np, "sram-size-playback", &val);
1773         if (ret >= 0)
1774                 pdata->sram_size_playback = val;
1775 
1776         ret = of_property_read_u32(np, "sram-size-capture", &val);
1777         if (ret >= 0)
1778                 pdata->sram_size_capture = val;
1779 
1780         ret = of_property_read_u32(np, "dismod", &val);
1781         if (ret >= 0) {
1782                 if (val == 0 || val == 2 || val == 3) {
1783                         pdata->dismod = DISMOD_VAL(val);
1784                 } else {
1785                         dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1786                         pdata->dismod = DISMOD_LOW;
1787                 }
1788         } else {
1789                 pdata->dismod = DISMOD_LOW;
1790         }
1791 
1792         return  pdata;
1793 
1794 nodata:
1795         if (ret < 0) {
1796                 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1797                         ret);
1798                 pdata = NULL;
1799         }
1800         return  pdata;
1801 }
1802 
1803 enum {
1804         PCM_EDMA,
1805         PCM_SDMA,
1806 };
1807 static const char *sdma_prefix = "ti,omap";
1808 
1809 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1810 {
1811         struct dma_chan *chan;
1812         const char *tmp;
1813         int ret = PCM_EDMA;
1814 
1815         if (!mcasp->dev->of_node)
1816                 return PCM_EDMA;
1817 
1818         tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1819         chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1820         if (IS_ERR(chan)) {
1821                 if (PTR_ERR(chan) != -EPROBE_DEFER)
1822                         dev_err(mcasp->dev,
1823                                 "Can't verify DMA configuration (%ld)\n",
1824                                 PTR_ERR(chan));
1825                 return PTR_ERR(chan);
1826         }
1827         if (WARN_ON(!chan->device || !chan->device->dev))
1828                 return -EINVAL;
1829 
1830         if (chan->device->dev->of_node)
1831                 ret = of_property_read_string(chan->device->dev->of_node,
1832                                               "compatible", &tmp);
1833         else
1834                 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1835 
1836         dma_release_channel(chan);
1837         if (ret)
1838                 return ret;
1839 
1840         dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1841         if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1842                 return PCM_SDMA;
1843 
1844         return PCM_EDMA;
1845 }
1846 
1847 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1848 {
1849         int i;
1850         u32 offset = 0;
1851 
1852         if (pdata->version != MCASP_VERSION_4)
1853                 return pdata->tx_dma_offset;
1854 
1855         for (i = 0; i < pdata->num_serializer; i++) {
1856                 if (pdata->serial_dir[i] == TX_MODE) {
1857                         if (!offset) {
1858                                 offset = DAVINCI_MCASP_TXBUF_REG(i);
1859                         } else {
1860                                 pr_err("%s: Only one serializer allowed!\n",
1861                                        __func__);
1862                                 break;
1863                         }
1864                 }
1865         }
1866 
1867         return offset;
1868 }
1869 
1870 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1871 {
1872         int i;
1873         u32 offset = 0;
1874 
1875         if (pdata->version != MCASP_VERSION_4)
1876                 return pdata->rx_dma_offset;
1877 
1878         for (i = 0; i < pdata->num_serializer; i++) {
1879                 if (pdata->serial_dir[i] == RX_MODE) {
1880                         if (!offset) {
1881                                 offset = DAVINCI_MCASP_RXBUF_REG(i);
1882                         } else {
1883                                 pr_err("%s: Only one serializer allowed!\n",
1884                                        __func__);
1885                                 break;
1886                         }
1887                 }
1888         }
1889 
1890         return offset;
1891 }
1892 
1893 #ifdef CONFIG_GPIOLIB
1894 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
1895 {
1896         struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1897 
1898         if (mcasp->num_serializer && offset < mcasp->num_serializer &&
1899             mcasp->serial_dir[offset] != INACTIVE_MODE) {
1900                 dev_err(mcasp->dev, "AXR%u pin is  used for audio\n", offset);
1901                 return -EBUSY;
1902         }
1903 
1904         /* Do not change the PIN yet */
1905 
1906         return pm_runtime_get_sync(mcasp->dev);
1907 }
1908 
1909 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
1910 {
1911         struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1912 
1913         /* Set the direction to input */
1914         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1915 
1916         /* Set the pin as McASP pin */
1917         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1918 
1919         pm_runtime_put_sync(mcasp->dev);
1920 }
1921 
1922 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
1923                                             unsigned offset, int value)
1924 {
1925         struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1926         u32 val;
1927 
1928         if (value)
1929                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1930         else
1931                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1932 
1933         val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
1934         if (!(val & BIT(offset))) {
1935                 /* Set the pin as GPIO pin */
1936                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1937 
1938                 /* Set the direction to output */
1939                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1940         }
1941 
1942         return 0;
1943 }
1944 
1945 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
1946                                   int value)
1947 {
1948         struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1949 
1950         if (value)
1951                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1952         else
1953                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1954 }
1955 
1956 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
1957                                            unsigned offset)
1958 {
1959         struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1960         u32 val;
1961 
1962         val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
1963         if (!(val & BIT(offset))) {
1964                 /* Set the direction to input */
1965                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1966 
1967                 /* Set the pin as GPIO pin */
1968                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1969         }
1970 
1971         return 0;
1972 }
1973 
1974 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
1975 {
1976         struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1977         u32 val;
1978 
1979         val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
1980         if (val & BIT(offset))
1981                 return 1;
1982 
1983         return 0;
1984 }
1985 
1986 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
1987                                             unsigned offset)
1988 {
1989         struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1990         u32 val;
1991 
1992         val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1993         if (val & BIT(offset))
1994                 return 0;
1995 
1996         return 1;
1997 }
1998 
1999 static const struct gpio_chip davinci_mcasp_template_chip = {
2000         .owner                  = THIS_MODULE,
2001         .request                = davinci_mcasp_gpio_request,
2002         .free                   = davinci_mcasp_gpio_free,
2003         .direction_output       = davinci_mcasp_gpio_direction_out,
2004         .set                    = davinci_mcasp_gpio_set,
2005         .direction_input        = davinci_mcasp_gpio_direction_in,
2006         .get                    = davinci_mcasp_gpio_get,
2007         .get_direction          = davinci_mcasp_gpio_get_direction,
2008         .base                   = -1,
2009         .ngpio                  = 32,
2010 };
2011 
2012 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2013 {
2014         if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
2015                 return 0;
2016 
2017         mcasp->gpio_chip = davinci_mcasp_template_chip;
2018         mcasp->gpio_chip.label = dev_name(mcasp->dev);
2019         mcasp->gpio_chip.parent = mcasp->dev;
2020 #ifdef CONFIG_OF_GPIO
2021         mcasp->gpio_chip.of_node = mcasp->dev->of_node;
2022 #endif
2023 
2024         return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2025 }
2026 
2027 #else /* CONFIG_GPIOLIB */
2028 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2029 {
2030         return 0;
2031 }
2032 #endif /* CONFIG_GPIOLIB */
2033 
2034 static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
2035 {
2036         struct device_node *np = mcasp->dev->of_node;
2037         int ret;
2038         u32 val;
2039 
2040         if (!np)
2041                 return 0;
2042 
2043         ret = of_property_read_u32(np, "auxclk-fs-ratio", &val);
2044         if (ret >= 0)
2045                 mcasp->auxclk_fs_ratio = val;
2046 
2047         return 0;
2048 }
2049 
2050 static int davinci_mcasp_probe(struct platform_device *pdev)
2051 {
2052         struct snd_dmaengine_dai_dma_data *dma_data;
2053         struct resource *mem, *res, *dat;
2054         struct davinci_mcasp_pdata *pdata;
2055         struct davinci_mcasp *mcasp;
2056         char *irq_name;
2057         int *dma;
2058         int irq;
2059         int ret;
2060 
2061         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2062                 dev_err(&pdev->dev, "No platform data supplied\n");
2063                 return -EINVAL;
2064         }
2065 
2066         mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2067                            GFP_KERNEL);
2068         if (!mcasp)
2069                 return  -ENOMEM;
2070 
2071         pdata = davinci_mcasp_set_pdata_from_of(pdev);
2072         if (!pdata) {
2073                 dev_err(&pdev->dev, "no platform data\n");
2074                 return -EINVAL;
2075         }
2076 
2077         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
2078         if (!mem) {
2079                 dev_warn(mcasp->dev,
2080                          "\"mpu\" mem resource not found, using index 0\n");
2081                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2082                 if (!mem) {
2083                         dev_err(&pdev->dev, "no mem resource?\n");
2084                         return -ENODEV;
2085                 }
2086         }
2087 
2088         mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2089         if (IS_ERR(mcasp->base))
2090                 return PTR_ERR(mcasp->base);
2091 
2092         pm_runtime_enable(&pdev->dev);
2093 
2094         mcasp->op_mode = pdata->op_mode;
2095         /* sanity check for tdm slots parameter */
2096         if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
2097                 if (pdata->tdm_slots < 2) {
2098                         dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2099                                 pdata->tdm_slots);
2100                         mcasp->tdm_slots = 2;
2101                 } else if (pdata->tdm_slots > 32) {
2102                         dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2103                                 pdata->tdm_slots);
2104                         mcasp->tdm_slots = 32;
2105                 } else {
2106                         mcasp->tdm_slots = pdata->tdm_slots;
2107                 }
2108         }
2109 
2110         mcasp->num_serializer = pdata->num_serializer;
2111 #ifdef CONFIG_PM
2112         mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
2113                                         mcasp->num_serializer, sizeof(u32),
2114                                         GFP_KERNEL);
2115         if (!mcasp->context.xrsr_regs) {
2116                 ret = -ENOMEM;
2117                 goto err;
2118         }
2119 #endif
2120         mcasp->serial_dir = pdata->serial_dir;
2121         mcasp->version = pdata->version;
2122         mcasp->txnumevt = pdata->txnumevt;
2123         mcasp->rxnumevt = pdata->rxnumevt;
2124         mcasp->dismod = pdata->dismod;
2125 
2126         mcasp->dev = &pdev->dev;
2127 
2128         irq = platform_get_irq_byname(pdev, "common");
2129         if (irq >= 0) {
2130                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
2131                                           dev_name(&pdev->dev));
2132                 if (!irq_name) {
2133                         ret = -ENOMEM;
2134                         goto err;
2135                 }
2136                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2137                                                 davinci_mcasp_common_irq_handler,
2138                                                 IRQF_ONESHOT | IRQF_SHARED,
2139                                                 irq_name, mcasp);
2140                 if (ret) {
2141                         dev_err(&pdev->dev, "common IRQ request failed\n");
2142                         goto err;
2143                 }
2144 
2145                 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2146                 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2147         }
2148 
2149         irq = platform_get_irq_byname(pdev, "rx");
2150         if (irq >= 0) {
2151                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
2152                                           dev_name(&pdev->dev));
2153                 if (!irq_name) {
2154                         ret = -ENOMEM;
2155                         goto err;
2156                 }
2157                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2158                                                 davinci_mcasp_rx_irq_handler,
2159                                                 IRQF_ONESHOT, irq_name, mcasp);
2160                 if (ret) {
2161                         dev_err(&pdev->dev, "RX IRQ request failed\n");
2162                         goto err;
2163                 }
2164 
2165                 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2166         }
2167 
2168         irq = platform_get_irq_byname(pdev, "tx");
2169         if (irq >= 0) {
2170                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
2171                                           dev_name(&pdev->dev));
2172                 if (!irq_name) {
2173                         ret = -ENOMEM;
2174                         goto err;
2175                 }
2176                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2177                                                 davinci_mcasp_tx_irq_handler,
2178                                                 IRQF_ONESHOT, irq_name, mcasp);
2179                 if (ret) {
2180                         dev_err(&pdev->dev, "TX IRQ request failed\n");
2181                         goto err;
2182                 }
2183 
2184                 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2185         }
2186 
2187         dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
2188         if (dat)
2189                 mcasp->dat_port = true;
2190 
2191         dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2192         if (dat)
2193                 dma_data->addr = dat->start;
2194         else
2195                 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
2196 
2197         dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
2198         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
2199         if (res)
2200                 *dma = res->start;
2201         else
2202                 *dma = pdata->tx_dma_channel;
2203 
2204         /* dmaengine filter data for DT and non-DT boot */
2205         if (pdev->dev.of_node)
2206                 dma_data->filter_data = "tx";
2207         else
2208                 dma_data->filter_data = dma;
2209 
2210         /* RX is not valid in DIT mode */
2211         if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2212                 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2213                 if (dat)
2214                         dma_data->addr = dat->start;
2215                 else
2216                         dma_data->addr =
2217                                 mem->start + davinci_mcasp_rxdma_offset(pdata);
2218 
2219                 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
2220                 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2221                 if (res)
2222                         *dma = res->start;
2223                 else
2224                         *dma = pdata->rx_dma_channel;
2225 
2226                 /* dmaengine filter data for DT and non-DT boot */
2227                 if (pdev->dev.of_node)
2228                         dma_data->filter_data = "rx";
2229                 else
2230                         dma_data->filter_data = dma;
2231         }
2232 
2233         if (mcasp->version < MCASP_VERSION_3) {
2234                 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2235                 /* dma_params->dma_addr is pointing to the data port address */
2236                 mcasp->dat_port = true;
2237         } else {
2238                 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2239         }
2240 
2241         /* Allocate memory for long enough list for all possible
2242          * scenarios. Maximum number tdm slots is 32 and there cannot
2243          * be more serializers than given in the configuration.  The
2244          * serializer directions could be taken into account, but it
2245          * would make code much more complex and save only couple of
2246          * bytes.
2247          */
2248         mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2249                 devm_kcalloc(mcasp->dev,
2250                              32 + mcasp->num_serializer - 1,
2251                              sizeof(unsigned int),
2252                              GFP_KERNEL);
2253 
2254         mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2255                 devm_kcalloc(mcasp->dev,
2256                              32 + mcasp->num_serializer - 1,
2257                              sizeof(unsigned int),
2258                              GFP_KERNEL);
2259 
2260         if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2261             !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2262                 ret = -ENOMEM;
2263                 goto err;
2264         }
2265 
2266         ret = davinci_mcasp_set_ch_constraints(mcasp);
2267         if (ret)
2268                 goto err;
2269 
2270         dev_set_drvdata(&pdev->dev, mcasp);
2271 
2272         mcasp_reparent_fck(pdev);
2273 
2274         /* All PINS as McASP */
2275         pm_runtime_get_sync(mcasp->dev);
2276         mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2277         pm_runtime_put(mcasp->dev);
2278 
2279         ret = davinci_mcasp_init_gpiochip(mcasp);
2280         if (ret)
2281                 goto err;
2282 
2283         ret = davinci_mcasp_get_dt_params(mcasp);
2284         if (ret)
2285                 return -EINVAL;
2286 
2287         ret = devm_snd_soc_register_component(&pdev->dev,
2288                                         &davinci_mcasp_component,
2289                                         &davinci_mcasp_dai[pdata->op_mode], 1);
2290 
2291         if (ret != 0)
2292                 goto err;
2293 
2294         ret = davinci_mcasp_get_dma_type(mcasp);
2295         switch (ret) {
2296         case PCM_EDMA:
2297                 ret = edma_pcm_platform_register(&pdev->dev);
2298                 break;
2299         case PCM_SDMA:
2300                 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
2301                 break;
2302         default:
2303                 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2304         case -EPROBE_DEFER:
2305                 goto err;
2306                 break;
2307         }
2308 
2309         if (ret) {
2310                 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2311                 goto err;
2312         }
2313 
2314         return 0;
2315 
2316 err:
2317         pm_runtime_disable(&pdev->dev);
2318         return ret;
2319 }
2320 
2321 static int davinci_mcasp_remove(struct platform_device *pdev)
2322 {
2323         pm_runtime_disable(&pdev->dev);
2324 
2325         return 0;
2326 }
2327 
2328 #ifdef CONFIG_PM
2329 static int davinci_mcasp_runtime_suspend(struct device *dev)
2330 {
2331         struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2332         struct davinci_mcasp_context *context = &mcasp->context;
2333         u32 reg;
2334         int i;
2335 
2336         for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2337                 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2338 
2339         if (mcasp->txnumevt) {
2340                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2341                 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2342         }
2343         if (mcasp->rxnumevt) {
2344                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2345                 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2346         }
2347 
2348         for (i = 0; i < mcasp->num_serializer; i++)
2349                 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2350                                                 DAVINCI_MCASP_XRSRCTL_REG(i));
2351 
2352         return 0;
2353 }
2354 
2355 static int davinci_mcasp_runtime_resume(struct device *dev)
2356 {
2357         struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2358         struct davinci_mcasp_context *context = &mcasp->context;
2359         u32 reg;
2360         int i;
2361 
2362         for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2363                 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2364 
2365         if (mcasp->txnumevt) {
2366                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2367                 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2368         }
2369         if (mcasp->rxnumevt) {
2370                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2371                 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2372         }
2373 
2374         for (i = 0; i < mcasp->num_serializer; i++)
2375                 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2376                               context->xrsr_regs[i]);
2377 
2378         return 0;
2379 }
2380 
2381 #endif
2382 
2383 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2384         SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2385                            davinci_mcasp_runtime_resume,
2386                            NULL)
2387 };
2388 
2389 static struct platform_driver davinci_mcasp_driver = {
2390         .probe          = davinci_mcasp_probe,
2391         .remove         = davinci_mcasp_remove,
2392         .driver         = {
2393                 .name   = "davinci-mcasp",
2394                 .pm     = &davinci_mcasp_pm_ops,
2395                 .of_match_table = mcasp_dt_ids,
2396         },
2397 };
2398 
2399 module_platform_driver(davinci_mcasp_driver);
2400 
2401 MODULE_AUTHOR("Steve Chen");
2402 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2403 MODULE_LICENSE("GPL");
2404 

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