~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/virt/kvm/arm/vgic/vgic-mmio-v3.c

Version: ~ [ linux-5.13-rc7 ] ~ [ linux-5.12.12 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.45 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.127 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.195 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.237 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.273 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.273 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.18.140 ] ~ [ linux-3.16.85 ] ~ [ linux-3.14.79 ] ~ [ linux-3.12.74 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * VGICv3 MMIO handling functions
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope that it will be useful,
  9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11  * GNU General Public License for more details.
 12  */
 13 
 14 #include <linux/irqchip/arm-gic-v3.h>
 15 #include <linux/kvm.h>
 16 #include <linux/kvm_host.h>
 17 #include <kvm/iodev.h>
 18 #include <kvm/arm_vgic.h>
 19 
 20 #include <asm/kvm_emulate.h>
 21 #include <asm/kvm_arm.h>
 22 #include <asm/kvm_mmu.h>
 23 
 24 #include "vgic.h"
 25 #include "vgic-mmio.h"
 26 
 27 /* extract @num bytes at @offset bytes offset in data */
 28 unsigned long extract_bytes(u64 data, unsigned int offset,
 29                             unsigned int num)
 30 {
 31         return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
 32 }
 33 
 34 /* allows updates of any half of a 64-bit register (or the whole thing) */
 35 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
 36                      unsigned long val)
 37 {
 38         int lower = (offset & 4) * 8;
 39         int upper = lower + 8 * len - 1;
 40 
 41         reg &= ~GENMASK_ULL(upper, lower);
 42         val &= GENMASK_ULL(len * 8 - 1, 0);
 43 
 44         return reg | ((u64)val << lower);
 45 }
 46 
 47 bool vgic_has_its(struct kvm *kvm)
 48 {
 49         struct vgic_dist *dist = &kvm->arch.vgic;
 50 
 51         if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
 52                 return false;
 53 
 54         return dist->has_its;
 55 }
 56 
 57 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
 58                                             gpa_t addr, unsigned int len)
 59 {
 60         u32 value = 0;
 61 
 62         switch (addr & 0x0c) {
 63         case GICD_CTLR:
 64                 if (vcpu->kvm->arch.vgic.enabled)
 65                         value |= GICD_CTLR_ENABLE_SS_G1;
 66                 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
 67                 break;
 68         case GICD_TYPER:
 69                 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 70                 value = (value >> 5) - 1;
 71                 if (vgic_has_its(vcpu->kvm)) {
 72                         value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
 73                         value |= GICD_TYPER_LPIS;
 74                 } else {
 75                         value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
 76                 }
 77                 break;
 78         case GICD_IIDR:
 79                 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 80                 break;
 81         default:
 82                 return 0;
 83         }
 84 
 85         return value;
 86 }
 87 
 88 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
 89                                     gpa_t addr, unsigned int len,
 90                                     unsigned long val)
 91 {
 92         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 93         bool was_enabled = dist->enabled;
 94 
 95         switch (addr & 0x0c) {
 96         case GICD_CTLR:
 97                 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
 98 
 99                 if (!was_enabled && dist->enabled)
100                         vgic_kick_vcpus(vcpu->kvm);
101                 break;
102         case GICD_TYPER:
103         case GICD_IIDR:
104                 return;
105         }
106 }
107 
108 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
109                                             gpa_t addr, unsigned int len)
110 {
111         int intid = VGIC_ADDR_TO_INTID(addr, 64);
112         struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
113         unsigned long ret = 0;
114 
115         if (!irq)
116                 return 0;
117 
118         /* The upper word is RAZ for us. */
119         if (!(addr & 4))
120                 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
121 
122         vgic_put_irq(vcpu->kvm, irq);
123         return ret;
124 }
125 
126 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
127                                     gpa_t addr, unsigned int len,
128                                     unsigned long val)
129 {
130         int intid = VGIC_ADDR_TO_INTID(addr, 64);
131         struct vgic_irq *irq;
132 
133         /* The upper word is WI for us since we don't implement Aff3. */
134         if (addr & 4)
135                 return;
136 
137         irq = vgic_get_irq(vcpu->kvm, NULL, intid);
138 
139         if (!irq)
140                 return;
141 
142         spin_lock(&irq->irq_lock);
143 
144         /* We only care about and preserve Aff0, Aff1 and Aff2. */
145         irq->mpidr = val & GENMASK(23, 0);
146         irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
147 
148         spin_unlock(&irq->irq_lock);
149         vgic_put_irq(vcpu->kvm, irq);
150 }
151 
152 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
153                                              gpa_t addr, unsigned int len)
154 {
155         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
156 
157         return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
158 }
159 
160 
161 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
162                                      gpa_t addr, unsigned int len,
163                                      unsigned long val)
164 {
165         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
166         bool was_enabled = vgic_cpu->lpis_enabled;
167 
168         if (!vgic_has_its(vcpu->kvm))
169                 return;
170 
171         vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
172 
173         if (!was_enabled && vgic_cpu->lpis_enabled)
174                 vgic_enable_lpis(vcpu);
175 }
176 
177 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
178                                               gpa_t addr, unsigned int len)
179 {
180         unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
181         int target_vcpu_id = vcpu->vcpu_id;
182         u64 value;
183 
184         value = (u64)(mpidr & GENMASK(23, 0)) << 32;
185         value |= ((target_vcpu_id & 0xffff) << 8);
186         if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
187                 value |= GICR_TYPER_LAST;
188         if (vgic_has_its(vcpu->kvm))
189                 value |= GICR_TYPER_PLPIS;
190 
191         return extract_bytes(value, addr & 7, len);
192 }
193 
194 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
195                                              gpa_t addr, unsigned int len)
196 {
197         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
198 }
199 
200 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
201                                               gpa_t addr, unsigned int len)
202 {
203         switch (addr & 0xffff) {
204         case GICD_PIDR2:
205                 /* report a GICv3 compliant implementation */
206                 return 0x3b;
207         }
208 
209         return 0;
210 }
211 
212 static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
213                                                   gpa_t addr, unsigned int len)
214 {
215         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
216         u32 value = 0;
217         int i;
218 
219         /*
220          * pending state of interrupt is latched in pending_latch variable.
221          * Userspace will save and restore pending state and line_level
222          * separately.
223          * Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
224          * for handling of ISPENDR and ICPENDR.
225          */
226         for (i = 0; i < len * 8; i++) {
227                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
228 
229                 if (irq->pending_latch)
230                         value |= (1U << i);
231 
232                 vgic_put_irq(vcpu->kvm, irq);
233         }
234 
235         return value;
236 }
237 
238 static void vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
239                                           gpa_t addr, unsigned int len,
240                                           unsigned long val)
241 {
242         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
243         int i;
244 
245         for (i = 0; i < len * 8; i++) {
246                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
247 
248                 spin_lock(&irq->irq_lock);
249                 if (test_bit(i, &val)) {
250                         /*
251                          * pending_latch is set irrespective of irq type
252                          * (level or edge) to avoid dependency that VM should
253                          * restore irq config before pending info.
254                          */
255                         irq->pending_latch = true;
256                         vgic_queue_irq_unlock(vcpu->kvm, irq);
257                 } else {
258                         irq->pending_latch = false;
259                         spin_unlock(&irq->irq_lock);
260                 }
261 
262                 vgic_put_irq(vcpu->kvm, irq);
263         }
264 }
265 
266 /* We want to avoid outer shareable. */
267 u64 vgic_sanitise_shareability(u64 field)
268 {
269         switch (field) {
270         case GIC_BASER_OuterShareable:
271                 return GIC_BASER_InnerShareable;
272         default:
273                 return field;
274         }
275 }
276 
277 /* Avoid any inner non-cacheable mapping. */
278 u64 vgic_sanitise_inner_cacheability(u64 field)
279 {
280         switch (field) {
281         case GIC_BASER_CACHE_nCnB:
282         case GIC_BASER_CACHE_nC:
283                 return GIC_BASER_CACHE_RaWb;
284         default:
285                 return field;
286         }
287 }
288 
289 /* Non-cacheable or same-as-inner are OK. */
290 u64 vgic_sanitise_outer_cacheability(u64 field)
291 {
292         switch (field) {
293         case GIC_BASER_CACHE_SameAsInner:
294         case GIC_BASER_CACHE_nC:
295                 return field;
296         default:
297                 return GIC_BASER_CACHE_nC;
298         }
299 }
300 
301 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
302                         u64 (*sanitise_fn)(u64))
303 {
304         u64 field = (reg & field_mask) >> field_shift;
305 
306         field = sanitise_fn(field) << field_shift;
307         return (reg & ~field_mask) | field;
308 }
309 
310 #define PROPBASER_RES0_MASK                                             \
311         (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
312 #define PENDBASER_RES0_MASK                                             \
313         (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) |      \
314          GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
315 
316 static u64 vgic_sanitise_pendbaser(u64 reg)
317 {
318         reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
319                                   GICR_PENDBASER_SHAREABILITY_SHIFT,
320                                   vgic_sanitise_shareability);
321         reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
322                                   GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
323                                   vgic_sanitise_inner_cacheability);
324         reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
325                                   GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
326                                   vgic_sanitise_outer_cacheability);
327 
328         reg &= ~PENDBASER_RES0_MASK;
329         reg &= ~GENMASK_ULL(51, 48);
330 
331         return reg;
332 }
333 
334 static u64 vgic_sanitise_propbaser(u64 reg)
335 {
336         reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
337                                   GICR_PROPBASER_SHAREABILITY_SHIFT,
338                                   vgic_sanitise_shareability);
339         reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
340                                   GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
341                                   vgic_sanitise_inner_cacheability);
342         reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
343                                   GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
344                                   vgic_sanitise_outer_cacheability);
345 
346         reg &= ~PROPBASER_RES0_MASK;
347         reg &= ~GENMASK_ULL(51, 48);
348         return reg;
349 }
350 
351 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
352                                              gpa_t addr, unsigned int len)
353 {
354         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
355 
356         return extract_bytes(dist->propbaser, addr & 7, len);
357 }
358 
359 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
360                                      gpa_t addr, unsigned int len,
361                                      unsigned long val)
362 {
363         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
364         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
365         u64 old_propbaser, propbaser;
366 
367         /* Storing a value with LPIs already enabled is undefined */
368         if (vgic_cpu->lpis_enabled)
369                 return;
370 
371         do {
372                 old_propbaser = dist->propbaser;
373                 propbaser = old_propbaser;
374                 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
375                 propbaser = vgic_sanitise_propbaser(propbaser);
376         } while (cmpxchg64(&dist->propbaser, old_propbaser,
377                            propbaser) != old_propbaser);
378 }
379 
380 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
381                                              gpa_t addr, unsigned int len)
382 {
383         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
384 
385         return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
386 }
387 
388 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
389                                      gpa_t addr, unsigned int len,
390                                      unsigned long val)
391 {
392         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
393         u64 old_pendbaser, pendbaser;
394 
395         /* Storing a value with LPIs already enabled is undefined */
396         if (vgic_cpu->lpis_enabled)
397                 return;
398 
399         do {
400                 old_pendbaser = vgic_cpu->pendbaser;
401                 pendbaser = old_pendbaser;
402                 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
403                 pendbaser = vgic_sanitise_pendbaser(pendbaser);
404         } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
405                            pendbaser) != old_pendbaser);
406 }
407 
408 /*
409  * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
410  * redistributors, while SPIs are covered by registers in the distributor
411  * block. Trying to set private IRQs in this block gets ignored.
412  * We take some special care here to fix the calculation of the register
413  * offset.
414  */
415 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
416         {                                                               \
417                 .reg_offset = off,                                      \
418                 .bits_per_irq = bpi,                                    \
419                 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,                \
420                 .access_flags = acc,                                    \
421                 .read = vgic_mmio_read_raz,                             \
422                 .write = vgic_mmio_write_wi,                            \
423         }, {                                                            \
424                 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,   \
425                 .bits_per_irq = bpi,                                    \
426                 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,       \
427                 .access_flags = acc,                                    \
428                 .read = rd,                                             \
429                 .write = wr,                                            \
430                 .uaccess_read = ur,                                     \
431                 .uaccess_write = uw,                                    \
432         }
433 
434 static const struct vgic_register_region vgic_v3_dist_registers[] = {
435         REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
436                 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
437                 VGIC_ACCESS_32bit),
438         REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
439                 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
440                 VGIC_ACCESS_32bit),
441         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
442                 vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,
443                 VGIC_ACCESS_32bit),
444         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
445                 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
446                 VGIC_ACCESS_32bit),
447         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
448                 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
449                 VGIC_ACCESS_32bit),
450         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
451                 vgic_mmio_read_pending, vgic_mmio_write_spending,
452                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
453                 VGIC_ACCESS_32bit),
454         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
455                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
456                 vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
457                 VGIC_ACCESS_32bit),
458         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
459                 vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1,
460                 VGIC_ACCESS_32bit),
461         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
462                 vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1,
463                 VGIC_ACCESS_32bit),
464         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
465                 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
466                 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
467         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
468                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
469                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
470         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
471                 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
472                 VGIC_ACCESS_32bit),
473         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
474                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
475                 VGIC_ACCESS_32bit),
476         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
477                 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
478                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
479         REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
480                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
481                 VGIC_ACCESS_32bit),
482 };
483 
484 static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
485         REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
486                 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
487                 VGIC_ACCESS_32bit),
488         REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
489                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
490                 VGIC_ACCESS_32bit),
491         REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
492                 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
493                 VGIC_ACCESS_32bit),
494         REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
495                 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
496                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
497         REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
498                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
499                 VGIC_ACCESS_32bit),
500         REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
501                 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
502                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
503         REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
504                 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
505                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
506         REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
507                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
508                 VGIC_ACCESS_32bit),
509 };
510 
511 static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
512         REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
513                 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
514                 VGIC_ACCESS_32bit),
515         REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
516                 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
517                 VGIC_ACCESS_32bit),
518         REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
519                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
520                 VGIC_ACCESS_32bit),
521         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
522                 vgic_mmio_read_pending, vgic_mmio_write_spending,
523                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
524                 VGIC_ACCESS_32bit),
525         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
526                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
527                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
528                 VGIC_ACCESS_32bit),
529         REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
530                 vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
531                 VGIC_ACCESS_32bit),
532         REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
533                 vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
534                 VGIC_ACCESS_32bit),
535         REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
536                 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
537                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
538         REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
539                 vgic_mmio_read_config, vgic_mmio_write_config, 8,
540                 VGIC_ACCESS_32bit),
541         REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
542                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
543                 VGIC_ACCESS_32bit),
544         REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
545                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
546                 VGIC_ACCESS_32bit),
547 };
548 
549 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
550 {
551         dev->regions = vgic_v3_dist_registers;
552         dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
553 
554         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
555 
556         return SZ_64K;
557 }
558 
559 /**
560  * vgic_register_redist_iodev - register a single redist iodev
561  * @vcpu:    The VCPU to which the redistributor belongs
562  *
563  * Register a KVM iodev for this VCPU's redistributor using the address
564  * provided.
565  *
566  * Return 0 on success, -ERRNO otherwise.
567  */
568 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
569 {
570         struct kvm *kvm = vcpu->kvm;
571         struct vgic_dist *vgic = &kvm->arch.vgic;
572         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
573         struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
574         gpa_t rd_base, sgi_base;
575         int ret;
576 
577         /*
578          * We may be creating VCPUs before having set the base address for the
579          * redistributor region, in which case we will come back to this
580          * function for all VCPUs when the base address is set.  Just return
581          * without doing any work for now.
582          */
583         if (IS_VGIC_ADDR_UNDEF(vgic->vgic_redist_base))
584                 return 0;
585 
586         if (!vgic_v3_check_base(kvm))
587                 return -EINVAL;
588 
589         rd_base = vgic->vgic_redist_base + vgic->vgic_redist_free_offset;
590         sgi_base = rd_base + SZ_64K;
591 
592         kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
593         rd_dev->base_addr = rd_base;
594         rd_dev->iodev_type = IODEV_REDIST;
595         rd_dev->regions = vgic_v3_rdbase_registers;
596         rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
597         rd_dev->redist_vcpu = vcpu;
598 
599         mutex_lock(&kvm->slots_lock);
600         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
601                                       SZ_64K, &rd_dev->dev);
602         mutex_unlock(&kvm->slots_lock);
603 
604         if (ret)
605                 return ret;
606 
607         kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
608         sgi_dev->base_addr = sgi_base;
609         sgi_dev->iodev_type = IODEV_REDIST;
610         sgi_dev->regions = vgic_v3_sgibase_registers;
611         sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
612         sgi_dev->redist_vcpu = vcpu;
613 
614         mutex_lock(&kvm->slots_lock);
615         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
616                                       SZ_64K, &sgi_dev->dev);
617         if (ret) {
618                 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
619                                           &rd_dev->dev);
620                 goto out;
621         }
622 
623         vgic->vgic_redist_free_offset += 2 * SZ_64K;
624 out:
625         mutex_unlock(&kvm->slots_lock);
626         return ret;
627 }
628 
629 static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
630 {
631         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
632         struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
633 
634         kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
635         kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &sgi_dev->dev);
636 }
637 
638 static int vgic_register_all_redist_iodevs(struct kvm *kvm)
639 {
640         struct kvm_vcpu *vcpu;
641         int c, ret = 0;
642 
643         kvm_for_each_vcpu(c, vcpu, kvm) {
644                 ret = vgic_register_redist_iodev(vcpu);
645                 if (ret)
646                         break;
647         }
648 
649         if (ret) {
650                 /* The current c failed, so we start with the previous one. */
651                 mutex_lock(&kvm->slots_lock);
652                 for (c--; c >= 0; c--) {
653                         vcpu = kvm_get_vcpu(kvm, c);
654                         vgic_unregister_redist_iodev(vcpu);
655                 }
656                 mutex_unlock(&kvm->slots_lock);
657         }
658 
659         return ret;
660 }
661 
662 int vgic_v3_set_redist_base(struct kvm *kvm, u64 addr)
663 {
664         struct vgic_dist *vgic = &kvm->arch.vgic;
665         int ret;
666 
667         /* vgic_check_ioaddr makes sure we don't do this twice */
668         ret = vgic_check_ioaddr(kvm, &vgic->vgic_redist_base, addr, SZ_64K);
669         if (ret)
670                 return ret;
671 
672         vgic->vgic_redist_base = addr;
673         if (!vgic_v3_check_base(kvm)) {
674                 vgic->vgic_redist_base = VGIC_ADDR_UNDEF;
675                 return -EINVAL;
676         }
677 
678         /*
679          * Register iodevs for each existing VCPU.  Adding more VCPUs
680          * afterwards will register the iodevs when needed.
681          */
682         ret = vgic_register_all_redist_iodevs(kvm);
683         if (ret)
684                 return ret;
685 
686         return 0;
687 }
688 
689 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
690 {
691         const struct vgic_register_region *region;
692         struct vgic_io_device iodev;
693         struct vgic_reg_attr reg_attr;
694         struct kvm_vcpu *vcpu;
695         gpa_t addr;
696         int ret;
697 
698         ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
699         if (ret)
700                 return ret;
701 
702         vcpu = reg_attr.vcpu;
703         addr = reg_attr.addr;
704 
705         switch (attr->group) {
706         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
707                 iodev.regions = vgic_v3_dist_registers;
708                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
709                 iodev.base_addr = 0;
710                 break;
711         case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
712                 iodev.regions = vgic_v3_rdbase_registers;
713                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
714                 iodev.base_addr = 0;
715                 break;
716         }
717         case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
718                 u64 reg, id;
719 
720                 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
721                 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, &reg);
722         }
723         default:
724                 return -ENXIO;
725         }
726 
727         /* We only support aligned 32-bit accesses. */
728         if (addr & 3)
729                 return -ENXIO;
730 
731         region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
732         if (!region)
733                 return -ENXIO;
734 
735         return 0;
736 }
737 /*
738  * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
739  * generation register ICC_SGI1R_EL1) with a given VCPU.
740  * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
741  * return -1.
742  */
743 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
744 {
745         unsigned long affinity;
746         int level0;
747 
748         /*
749          * Split the current VCPU's MPIDR into affinity level 0 and the
750          * rest as this is what we have to compare against.
751          */
752         affinity = kvm_vcpu_get_mpidr_aff(vcpu);
753         level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
754         affinity &= ~MPIDR_LEVEL_MASK;
755 
756         /* bail out if the upper three levels don't match */
757         if (sgi_aff != affinity)
758                 return -1;
759 
760         /* Is this VCPU's bit set in the mask ? */
761         if (!(sgi_cpu_mask & BIT(level0)))
762                 return -1;
763 
764         return level0;
765 }
766 
767 /*
768  * The ICC_SGI* registers encode the affinity differently from the MPIDR,
769  * so provide a wrapper to use the existing defines to isolate a certain
770  * affinity level.
771  */
772 #define SGI_AFFINITY_LEVEL(reg, level) \
773         ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
774         >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
775 
776 /**
777  * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
778  * @vcpu: The VCPU requesting a SGI
779  * @reg: The value written into the ICC_SGI1R_EL1 register by that VCPU
780  *
781  * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
782  * This will trap in sys_regs.c and call this function.
783  * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
784  * target processors as well as a bitmask of 16 Aff0 CPUs.
785  * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
786  * check for matching ones. If this bit is set, we signal all, but not the
787  * calling VCPU.
788  */
789 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
790 {
791         struct kvm *kvm = vcpu->kvm;
792         struct kvm_vcpu *c_vcpu;
793         u16 target_cpus;
794         u64 mpidr;
795         int sgi, c;
796         int vcpu_id = vcpu->vcpu_id;
797         bool broadcast;
798 
799         sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
800         broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
801         target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
802         mpidr = SGI_AFFINITY_LEVEL(reg, 3);
803         mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
804         mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
805 
806         /*
807          * We iterate over all VCPUs to find the MPIDRs matching the request.
808          * If we have handled one CPU, we clear its bit to detect early
809          * if we are already finished. This avoids iterating through all
810          * VCPUs when most of the times we just signal a single VCPU.
811          */
812         kvm_for_each_vcpu(c, c_vcpu, kvm) {
813                 struct vgic_irq *irq;
814 
815                 /* Exit early if we have dealt with all requested CPUs */
816                 if (!broadcast && target_cpus == 0)
817                         break;
818 
819                 /* Don't signal the calling VCPU */
820                 if (broadcast && c == vcpu_id)
821                         continue;
822 
823                 if (!broadcast) {
824                         int level0;
825 
826                         level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
827                         if (level0 == -1)
828                                 continue;
829 
830                         /* remove this matching VCPU from the mask */
831                         target_cpus &= ~BIT(level0);
832                 }
833 
834                 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
835 
836                 spin_lock(&irq->irq_lock);
837                 irq->pending_latch = true;
838 
839                 vgic_queue_irq_unlock(vcpu->kvm, irq);
840                 vgic_put_irq(vcpu->kvm, irq);
841         }
842 }
843 
844 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
845                          int offset, u32 *val)
846 {
847         struct vgic_io_device dev = {
848                 .regions = vgic_v3_dist_registers,
849                 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
850         };
851 
852         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
853 }
854 
855 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
856                            int offset, u32 *val)
857 {
858         struct vgic_io_device rd_dev = {
859                 .regions = vgic_v3_rdbase_registers,
860                 .nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers),
861         };
862 
863         struct vgic_io_device sgi_dev = {
864                 .regions = vgic_v3_sgibase_registers,
865                 .nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers),
866         };
867 
868         /* SGI_base is the next 64K frame after RD_base */
869         if (offset >= SZ_64K)
870                 return vgic_uaccess(vcpu, &sgi_dev, is_write, offset - SZ_64K,
871                                     val);
872         else
873                 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
874 }
875 
876 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
877                                     u32 intid, u64 *val)
878 {
879         if (intid % 32)
880                 return -EINVAL;
881 
882         if (is_write)
883                 vgic_write_irq_line_level_info(vcpu, intid, *val);
884         else
885                 *val = vgic_read_irq_line_level_info(vcpu, intid);
886 
887         return 0;
888 }
889 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp